2010-12-04 23:57:24 +00:00
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//===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
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2005-07-12 01:41:54 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-07-12 01:41:54 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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2011-07-01 21:01:15 +00:00
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// This file implements the X86 specific subclass of TargetSubtargetInfo.
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2005-07-12 01:41:54 +00:00
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//
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//===----------------------------------------------------------------------===//
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2009-01-03 04:04:46 +00:00
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#define DEBUG_TYPE "subtarget"
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2005-07-12 01:41:54 +00:00
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#include "X86Subtarget.h"
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2009-07-10 07:20:05 +00:00
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#include "X86InstrInfo.h"
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2013-02-15 22:31:27 +00:00
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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2013-01-02 11:36:10 +00:00
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#include "llvm/IR/GlobalValue.h"
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2009-01-03 04:04:46 +00:00
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#include "llvm/Support/Debug.h"
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2011-09-07 16:10:57 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2010-11-29 18:16:10 +00:00
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#include "llvm/Support/Host.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/Support/raw_ostream.h"
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2006-12-22 22:29:05 +00:00
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#include "llvm/Target/TargetMachine.h"
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2011-09-07 16:10:57 +00:00
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#include "llvm/Target/TargetOptions.h"
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2011-07-01 20:45:01 +00:00
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#define GET_SUBTARGETINFO_TARGET_DESC
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2011-07-08 01:53:10 +00:00
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#define GET_SUBTARGETINFO_CTOR
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2011-07-01 22:36:09 +00:00
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#include "X86GenSubtargetInfo.inc"
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2011-07-01 20:45:01 +00:00
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2005-07-12 01:41:54 +00:00
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using namespace llvm;
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2009-04-25 18:27:23 +00:00
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#if defined(_MSC_VER)
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2009-08-03 00:11:34 +00:00
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#include <intrin.h>
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2009-04-25 18:27:23 +00:00
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#endif
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2009-11-20 23:18:13 +00:00
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/// ClassifyBlockAddressReference - Classify a blockaddress reference for the
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/// current subtarget according to how we should reference it in a non-pcrel
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/// context.
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2013-04-02 23:06:40 +00:00
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unsigned char X86Subtarget::ClassifyBlockAddressReference() const {
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2009-11-20 23:18:13 +00:00
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if (isPICStyleGOT()) // 32-bit ELF targets.
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return X86II::MO_GOTOFF;
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2012-08-01 18:39:17 +00:00
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2009-11-20 23:18:13 +00:00
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if (isPICStyleStubPIC()) // Darwin/32 in PIC mode.
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return X86II::MO_PIC_BASE_OFFSET;
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2012-08-01 18:39:17 +00:00
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2009-11-20 23:18:13 +00:00
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// Direct static reference to label.
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return X86II::MO_NO_FLAG;
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}
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2009-07-10 07:20:05 +00:00
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/// ClassifyGlobalReference - Classify a global variable reference for the
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/// current subtarget according to how we should reference it in a non-pcrel
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/// context.
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unsigned char X86Subtarget::
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ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
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// DLLImport only exists on windows, it is implemented as a load from a
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// DLLIMPORT stub.
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2014-01-14 15:22:47 +00:00
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if (GV->hasDLLImportStorageClass())
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2009-07-10 07:20:05 +00:00
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return X86II::MO_DLLIMPORT;
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2010-06-14 20:11:56 +00:00
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// Determine whether this is a reference to a definition or a declaration.
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// Materializable GVs (in JIT lazy compilation mode) do not require an extra
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// load from stub.
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bool isDecl = GV->hasAvailableExternallyLinkage();
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if (GV->isDeclaration() && !GV->isMaterializable())
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isDecl = true;
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2009-07-16 22:53:10 +00:00
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2009-07-10 07:20:05 +00:00
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// X86-64 in PIC mode.
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if (isPICStyleRIPRel()) {
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// Large model never uses stubs.
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if (TM.getCodeModel() == CodeModel::Large)
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return X86II::MO_NO_FLAG;
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2012-08-01 18:39:17 +00:00
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2009-07-10 21:01:59 +00:00
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if (isTargetDarwin()) {
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// If symbol visibility is hidden, the extra load is not needed if
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// target is x86-64 or the symbol is definitely defined in the current
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// translation unit.
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if (GV->hasDefaultVisibility() &&
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2009-07-16 22:53:10 +00:00
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(isDecl || GV->isWeakForLinker()))
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2009-07-10 21:01:59 +00:00
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return X86II::MO_GOTPCREL;
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2010-08-21 17:21:11 +00:00
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} else if (!isTargetWin64()) {
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2009-07-10 21:01:59 +00:00
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assert(isTargetELF() && "Unknown rip-relative target");
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2009-07-10 07:20:05 +00:00
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2009-07-10 21:01:59 +00:00
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// Extra load is needed for all externally visible.
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if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
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return X86II::MO_GOTPCREL;
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}
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2009-07-10 07:20:05 +00:00
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return X86II::MO_NO_FLAG;
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}
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2012-08-01 18:39:17 +00:00
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2009-07-10 07:20:05 +00:00
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if (isPICStyleGOT()) { // 32-bit ELF targets.
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// Extra load is needed for all externally visible.
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if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
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return X86II::MO_GOTOFF;
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return X86II::MO_GOT;
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}
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2012-08-01 18:39:17 +00:00
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2009-07-10 21:00:45 +00:00
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if (isPICStyleStubPIC()) { // Darwin/32 in PIC mode.
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2009-07-10 20:53:38 +00:00
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// Determine whether we have a stub reference and/or whether the reference
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// is relative to the PIC base or not.
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2012-08-01 18:39:17 +00:00
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2009-07-10 07:20:05 +00:00
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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2009-07-16 22:53:10 +00:00
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if (!isDecl && !GV->isWeakForLinker())
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2009-07-10 20:53:38 +00:00
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return X86II::MO_PIC_BASE_OFFSET;
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2009-07-10 07:20:05 +00:00
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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2009-07-10 20:53:38 +00:00
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
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2012-08-01 18:39:17 +00:00
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2009-07-10 20:53:38 +00:00
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// If symbol visibility is hidden, we have a stub for common symbol
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// references and external declarations.
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2009-07-16 22:53:10 +00:00
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if (isDecl || GV->hasCommonLinkage()) {
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2009-07-10 20:53:38 +00:00
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// Hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
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2009-07-10 07:20:05 +00:00
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}
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2012-08-01 18:39:17 +00:00
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2009-07-10 20:53:38 +00:00
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// Otherwise, no stub.
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return X86II::MO_PIC_BASE_OFFSET;
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}
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2012-08-01 18:39:17 +00:00
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2009-07-10 21:00:45 +00:00
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if (isPICStyleStubNoDynamic()) { // Darwin/32 in -mdynamic-no-pic mode.
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2009-07-10 20:53:38 +00:00
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// Determine whether we have a stub reference.
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2012-08-01 18:39:17 +00:00
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2009-07-10 20:53:38 +00:00
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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2009-07-16 22:53:10 +00:00
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if (!isDecl && !GV->isWeakForLinker())
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2009-07-10 20:53:38 +00:00
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return X86II::MO_NO_FLAG;
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2012-08-01 18:39:17 +00:00
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2009-07-10 20:53:38 +00:00
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_NONLAZY;
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2009-09-03 07:04:02 +00:00
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2009-07-10 07:20:05 +00:00
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// Otherwise, no stub.
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2009-07-10 20:53:38 +00:00
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return X86II::MO_NO_FLAG;
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2009-07-10 07:20:05 +00:00
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}
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2012-08-01 18:39:17 +00:00
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2009-07-10 07:20:05 +00:00
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// Direct static reference to global.
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return X86II::MO_NO_FLAG;
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}
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2006-11-30 22:42:55 +00:00
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2008-09-30 21:22:07 +00:00
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/// getBZeroEntry - This function returns the name of a function which has an
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/// interface like the non-standard bzero function, if such a function exists on
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/// the current subtarget and it is considered prefereable over memset with zero
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/// passed as the second argument. Otherwise it returns null.
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2008-09-30 22:05:33 +00:00
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const char *X86Subtarget::getBZeroEntry() const {
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2008-04-01 20:38:36 +00:00
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// Darwin 10 has a __bzero entry point for this purpose.
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2011-04-20 00:14:25 +00:00
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if (getTargetTriple().isMacOSX() &&
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!getTargetTriple().isMacOSXVersionLT(10, 6))
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2008-09-30 22:05:33 +00:00
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return "__bzero";
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2008-04-01 20:38:36 +00:00
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return 0;
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}
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2013-01-29 02:32:37 +00:00
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bool X86Subtarget::hasSinCos() const {
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return getTargetTriple().isMacOSX() &&
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2013-01-30 22:56:35 +00:00
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!getTargetTriple().isMacOSXVersionLT(10, 9) &&
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is64Bit();
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2013-01-29 02:32:37 +00:00
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}
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2009-05-20 04:53:57 +00:00
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/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
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/// to immediate address.
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bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
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2014-03-28 21:40:47 +00:00
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// FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32
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// but WinCOFFObjectWriter::RecordRelocation cannot emit them. Once it does,
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// the following check for Win32 should be removed.
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if (In64BitMode || isTargetWin32())
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2009-05-20 04:53:57 +00:00
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return false;
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return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
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}
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2013-05-03 02:39:21 +00:00
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static bool OSHasAVXSupport() {
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2013-05-07 14:05:33 +00:00
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#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
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|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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2013-05-03 02:39:21 +00:00
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#if defined(__GNUC__)
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// Check xgetbv; this uses a .byte sequence instead of the instruction
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// directly because older assemblers do not include support for xgetbv and
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// there is no easy way to conditionally compile based on the assembler used.
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int rEAX, rEDX;
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__asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
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#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
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unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
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#else
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int rEAX = 0; // Ensures we return false
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#endif
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return (rEAX & 6) == 6;
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2013-05-03 02:52:21 +00:00
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#else
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return false;
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#endif
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2013-05-03 02:39:21 +00:00
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}
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2006-10-06 09:17:41 +00:00
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void X86Subtarget::AutoDetectSubtargetFeatures() {
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2006-01-27 19:30:30 +00:00
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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2011-10-16 00:21:51 +00:00
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unsigned MaxLevel;
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2006-01-28 18:47:32 +00:00
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union {
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2006-01-28 19:48:34 +00:00
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unsigned u[3];
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char c[12];
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2006-01-28 18:47:32 +00:00
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} text;
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2011-10-16 00:21:51 +00:00
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if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
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MaxLevel < 1)
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2006-10-06 08:21:07 +00:00
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return;
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2011-07-07 21:06:52 +00:00
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X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
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2011-10-16 00:21:51 +00:00
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2011-10-10 05:34:02 +00:00
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if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
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if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); }
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if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); }
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if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); }
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if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); }
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if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
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if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
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if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
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2013-05-03 02:39:21 +00:00
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if (((ECX >> 27) & 1) && ((ECX >> 28) & 1) && OSHasAVXSupport()) {
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X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX);
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}
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2006-01-28 18:09:06 +00:00
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2009-01-02 05:35:45 +00:00
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bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
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bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
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2009-06-26 22:46:54 +00:00
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2012-05-01 07:10:32 +00:00
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if ((ECX >> 1) & 0x1) {
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2012-05-31 14:34:17 +00:00
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HasPCLMUL = true;
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ToggleFeature(X86::FeaturePCLMUL);
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2011-10-10 05:34:02 +00:00
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}
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2012-06-01 06:10:14 +00:00
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if ((ECX >> 12) & 0x1) {
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2012-06-03 18:58:46 +00:00
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HasFMA = true;
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ToggleFeature(X86::FeatureFMA);
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2012-06-01 06:10:14 +00:00
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}
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2011-10-10 05:34:02 +00:00
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if (IsIntel && ((ECX >> 22) & 0x1)) {
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HasMOVBE = true;
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ToggleFeature(X86::FeatureMOVBE);
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}
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2012-05-01 07:10:32 +00:00
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if ((ECX >> 23) & 0x1) {
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2011-10-10 05:34:02 +00:00
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HasPOPCNT = true;
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ToggleFeature(X86::FeaturePOPCNT);
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}
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2012-05-01 07:10:32 +00:00
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if ((ECX >> 25) & 0x1) {
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2011-10-10 05:34:02 +00:00
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HasAES = true;
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ToggleFeature(X86::FeatureAES);
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}
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2012-05-01 07:10:32 +00:00
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if ((ECX >> 29) & 0x1) {
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2011-10-10 05:34:02 +00:00
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HasF16C = true;
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ToggleFeature(X86::FeatureF16C);
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}
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if (IsIntel && ((ECX >> 30) & 0x1)) {
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HasRDRAND = true;
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ToggleFeature(X86::FeatureRDRAND);
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}
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if ((ECX >> 13) & 0x1) {
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HasCmpxchg16b = true;
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ToggleFeature(X86::FeatureCMPXCHG16B);
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}
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2009-06-26 22:46:54 +00:00
|
|
|
|
2009-01-02 05:35:45 +00:00
|
|
|
if (IsIntel || IsAMD) {
|
|
|
|
// Determine if bit test memory instructions are slow.
|
|
|
|
unsigned Family = 0;
|
|
|
|
unsigned Model = 0;
|
2011-07-07 21:06:52 +00:00
|
|
|
X86_MC::DetectFamilyModel(EAX, Family, Model);
|
2011-07-11 03:57:24 +00:00
|
|
|
if (IsAMD || (Family == 6 && Model >= 13)) {
|
|
|
|
IsBTMemSlow = true;
|
|
|
|
ToggleFeature(X86::FeatureSlowBTMem);
|
|
|
|
}
|
2012-02-01 23:20:51 +00:00
|
|
|
|
SHLD/SHRD are VectorPath (microcode) instructions known to have poor latency on certain architectures. While generating SHLD/SHRD instructions is acceptable when optimizing for size, optimizing for speed on these platforms should be implemented using alternative sequences of instructions composed of add, adc, shr, shl, or and lea which are directPath instructions. These alternative instructions not only have a lower latency but they also increase the decode bandwidth by allowing simultaneous decoding of a third directPath instruction.
AMD's processors family K7, K8, K10, K12, K15 and K16 are known to have SHLD/SHRD instructions with very poor latency. Optimization guides for these processors recommend using an alternative sequence of instructions. For these AMD's processors, I disabled folding (or (x << c) | (y >> (64 - c))) when we are not optimizing for size.
It might be beneficial to disable this folding for some of the Intel's processors. However, since I couldn't find specific recommendations regarding using SHLD/SHRD instructions on Intel's processors, I haven't disabled this peephole for Intel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195383 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 23:21:26 +00:00
|
|
|
// Determine if SHLD/SHRD instructions have higher latency then the
|
|
|
|
// equivalent series of shifts/or instructions.
|
|
|
|
// FIXME: Add Intel's processors that have SHLD instructions with very
|
|
|
|
// poor latency.
|
|
|
|
if (IsAMD) {
|
|
|
|
IsSHLDSlow = true;
|
|
|
|
ToggleFeature(X86::FeatureSlowSHLD);
|
|
|
|
}
|
|
|
|
|
2012-12-10 09:18:44 +00:00
|
|
|
// If it's an Intel chip since Nehalem and not an Atom chip, unaligned
|
|
|
|
// memory access is fast. We hard code model numbers here because they
|
|
|
|
// aren't strictly increasing for Intel chips it seems.
|
|
|
|
if (IsIntel &&
|
|
|
|
((Family == 6 && Model == 0x1E) || // Nehalem: Clarksfield, Lynnfield,
|
|
|
|
// Jasper Froest
|
2012-12-10 18:22:40 +00:00
|
|
|
(Family == 6 && Model == 0x1A) || // Nehalem: Bloomfield, Nehalem-EP
|
2012-12-10 09:18:44 +00:00
|
|
|
(Family == 6 && Model == 0x2E) || // Nehalem: Nehalem-EX
|
|
|
|
(Family == 6 && Model == 0x25) || // Westmere: Arrandale, Clarksdale
|
|
|
|
(Family == 6 && Model == 0x2C) || // Westmere: Gulftown, Westmere-EP
|
|
|
|
(Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX
|
|
|
|
(Family == 6 && Model == 0x2A) || // SandyBridge
|
|
|
|
(Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E*
|
2013-11-25 09:52:59 +00:00
|
|
|
(Family == 6 && Model == 0x3A) || // IvyBridge
|
|
|
|
(Family == 6 && Model == 0x3E) || // IvyBridge EP
|
|
|
|
(Family == 6 && Model == 0x3C) || // Haswell
|
|
|
|
(Family == 6 && Model == 0x3F) || // ...
|
|
|
|
(Family == 6 && Model == 0x45) || // ...
|
|
|
|
(Family == 6 && Model == 0x46))) { // ...
|
2010-04-01 05:58:17 +00:00
|
|
|
IsUAMemFast = true;
|
2011-07-11 03:57:24 +00:00
|
|
|
ToggleFeature(X86::FeatureFastUAMem);
|
|
|
|
}
|
2009-01-02 05:35:45 +00:00
|
|
|
|
2013-09-13 19:23:28 +00:00
|
|
|
// Set processor type. Currently only Atom or Silvermont (SLM) is detected.
|
2012-05-02 21:38:46 +00:00
|
|
|
if (Family == 6 &&
|
2013-09-13 04:41:06 +00:00
|
|
|
(Model == 28 || Model == 38 || Model == 39 ||
|
|
|
|
Model == 53 || Model == 54)) {
|
2012-02-01 23:20:51 +00:00
|
|
|
X86ProcFamily = IntelAtom;
|
2012-04-26 19:52:27 +00:00
|
|
|
|
|
|
|
UseLeaForSP = true;
|
2012-02-07 22:50:41 +00:00
|
|
|
ToggleFeature(X86::FeatureLeaForSP);
|
2012-02-01 23:20:51 +00:00
|
|
|
}
|
2013-09-13 19:23:28 +00:00
|
|
|
else if (Family == 6 &&
|
|
|
|
(Model == 55 || Model == 74 || Model == 77)) {
|
|
|
|
X86ProcFamily = IntelSLM;
|
|
|
|
}
|
2012-02-01 23:20:51 +00:00
|
|
|
|
2011-10-16 00:21:51 +00:00
|
|
|
unsigned MaxExtLevel;
|
|
|
|
X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
|
|
|
|
|
|
|
|
if (MaxExtLevel >= 0x80000001) {
|
|
|
|
X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
|
|
|
|
if ((EDX >> 29) & 0x1) {
|
|
|
|
HasX86_64 = true;
|
|
|
|
ToggleFeature(X86::Feature64Bit);
|
|
|
|
}
|
|
|
|
if ((ECX >> 5) & 0x1) {
|
|
|
|
HasLZCNT = true;
|
|
|
|
ToggleFeature(X86::FeatureLZCNT);
|
|
|
|
}
|
2013-03-26 17:47:11 +00:00
|
|
|
if (IsIntel && ((ECX >> 8) & 0x1)) {
|
|
|
|
HasPRFCHW = true;
|
|
|
|
ToggleFeature(X86::FeaturePRFCHW);
|
|
|
|
}
|
2011-12-29 19:25:56 +00:00
|
|
|
if (IsAMD) {
|
|
|
|
if ((ECX >> 6) & 0x1) {
|
|
|
|
HasSSE4A = true;
|
|
|
|
ToggleFeature(X86::FeatureSSE4A);
|
|
|
|
}
|
|
|
|
if ((ECX >> 11) & 0x1) {
|
|
|
|
HasXOP = true;
|
|
|
|
ToggleFeature(X86::FeatureXOP);
|
|
|
|
}
|
|
|
|
if ((ECX >> 16) & 0x1) {
|
|
|
|
HasFMA4 = true;
|
|
|
|
ToggleFeature(X86::FeatureFMA4);
|
|
|
|
}
|
2011-10-16 00:21:51 +00:00
|
|
|
}
|
2011-07-11 03:57:24 +00:00
|
|
|
}
|
2011-10-16 00:21:51 +00:00
|
|
|
}
|
|
|
|
|
2012-05-01 07:10:32 +00:00
|
|
|
if (MaxLevel >= 7) {
|
2011-10-17 05:33:10 +00:00
|
|
|
if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
|
2012-05-01 07:10:32 +00:00
|
|
|
if (IsIntel && (EBX & 0x1)) {
|
2011-10-30 19:57:21 +00:00
|
|
|
HasFSGSBase = true;
|
|
|
|
ToggleFeature(X86::FeatureFSGSBase);
|
|
|
|
}
|
2011-10-17 05:33:10 +00:00
|
|
|
if ((EBX >> 3) & 0x1) {
|
|
|
|
HasBMI = true;
|
|
|
|
ToggleFeature(X86::FeatureBMI);
|
|
|
|
}
|
2013-03-26 22:46:02 +00:00
|
|
|
if ((EBX >> 4) & 0x1) {
|
|
|
|
HasHLE = true;
|
|
|
|
ToggleFeature(X86::FeatureHLE);
|
|
|
|
}
|
2012-05-01 07:10:32 +00:00
|
|
|
if (IsIntel && ((EBX >> 5) & 0x1)) {
|
2012-04-26 06:40:15 +00:00
|
|
|
X86SSELevel = AVX2;
|
|
|
|
ToggleFeature(X86::FeatureAVX2);
|
|
|
|
}
|
2012-05-01 07:10:32 +00:00
|
|
|
if (IsIntel && ((EBX >> 8) & 0x1)) {
|
2011-10-17 05:33:10 +00:00
|
|
|
HasBMI2 = true;
|
|
|
|
ToggleFeature(X86::FeatureBMI2);
|
|
|
|
}
|
2012-11-08 07:28:54 +00:00
|
|
|
if (IsIntel && ((EBX >> 11) & 0x1)) {
|
|
|
|
HasRTM = true;
|
|
|
|
ToggleFeature(X86::FeatureRTM);
|
|
|
|
}
|
2013-08-20 05:22:42 +00:00
|
|
|
if (IsIntel && ((EBX >> 16) & 0x1)) {
|
2013-08-21 03:57:57 +00:00
|
|
|
X86SSELevel = AVX512F;
|
2013-08-20 05:22:42 +00:00
|
|
|
ToggleFeature(X86::FeatureAVX512);
|
2013-03-28 22:29:53 +00:00
|
|
|
}
|
2013-03-28 23:41:26 +00:00
|
|
|
if (IsIntel && ((EBX >> 18) & 0x1)) {
|
|
|
|
HasRDSEED = true;
|
|
|
|
ToggleFeature(X86::FeatureRDSEED);
|
|
|
|
}
|
2013-08-20 05:22:42 +00:00
|
|
|
if (IsIntel && ((EBX >> 19) & 0x1)) {
|
|
|
|
HasADX = true;
|
|
|
|
ToggleFeature(X86::FeatureADX);
|
|
|
|
}
|
|
|
|
if (IsIntel && ((EBX >> 26) & 0x1)) {
|
|
|
|
HasPFI = true;
|
|
|
|
ToggleFeature(X86::FeaturePFI);
|
|
|
|
}
|
|
|
|
if (IsIntel && ((EBX >> 27) & 0x1)) {
|
|
|
|
HasERI = true;
|
|
|
|
ToggleFeature(X86::FeatureERI);
|
|
|
|
}
|
|
|
|
if (IsIntel && ((EBX >> 28) & 0x1)) {
|
|
|
|
HasCDI = true;
|
|
|
|
ToggleFeature(X86::FeatureCDI);
|
|
|
|
}
|
2013-09-12 15:51:31 +00:00
|
|
|
if (IsIntel && ((EBX >> 29) & 0x1)) {
|
|
|
|
HasSHA = true;
|
|
|
|
ToggleFeature(X86::FeatureSHA);
|
|
|
|
}
|
2011-10-16 07:55:05 +00:00
|
|
|
}
|
2013-09-24 18:21:52 +00:00
|
|
|
if (IsAMD && ((ECX >> 21) & 0x1)) {
|
|
|
|
HasTBM = true;
|
|
|
|
ToggleFeature(X86::FeatureTBM);
|
|
|
|
}
|
2007-04-16 21:59:44 +00:00
|
|
|
}
|
2006-01-26 09:53:06 +00:00
|
|
|
}
|
|
|
|
|
2013-02-15 22:31:27 +00:00
|
|
|
void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) {
|
|
|
|
AttributeSet FnAttrs = MF->getFunction()->getAttributes();
|
|
|
|
Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
|
|
|
|
"target-cpu");
|
|
|
|
Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
|
|
|
|
"target-features");
|
2013-02-27 05:56:20 +00:00
|
|
|
std::string CPU =
|
|
|
|
!CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
|
|
|
|
std::string FS =
|
2013-02-15 22:31:27 +00:00
|
|
|
!FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
|
2013-02-16 01:36:26 +00:00
|
|
|
if (!FS.empty()) {
|
|
|
|
initializeEnvironment();
|
2013-02-15 22:31:27 +00:00
|
|
|
resetSubtargetFeatures(CPU, FS);
|
2013-02-16 01:36:26 +00:00
|
|
|
}
|
2013-02-15 22:31:27 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void X86Subtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
|
2013-02-27 05:56:20 +00:00
|
|
|
std::string CPUName = CPU;
|
2011-07-08 22:30:25 +00:00
|
|
|
if (!FS.empty() || !CPU.empty()) {
|
2011-07-08 21:14:14 +00:00
|
|
|
if (CPUName.empty()) {
|
2012-01-30 23:10:32 +00:00
|
|
|
#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
|
|
|
|
|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
|
2011-07-08 21:14:14 +00:00
|
|
|
CPUName = sys::getHostCPUName();
|
|
|
|
#else
|
|
|
|
CPUName = "generic";
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2011-07-08 23:43:01 +00:00
|
|
|
// Make sure 64-bit features are available in 64-bit mode. (But make sure
|
|
|
|
// SSE2 can be turned off explicitly.)
|
|
|
|
std::string FullFS = FS;
|
|
|
|
if (In64BitMode) {
|
|
|
|
if (!FullFS.empty())
|
|
|
|
FullFS = "+64bit,+sse2," + FullFS;
|
|
|
|
else
|
|
|
|
FullFS = "+64bit,+sse2";
|
|
|
|
}
|
|
|
|
|
2006-10-06 09:17:41 +00:00
|
|
|
// If feature string is not empty, parse features string.
|
2011-07-08 23:43:01 +00:00
|
|
|
ParseSubtargetFeatures(CPUName, FullFS);
|
2006-11-20 18:16:05 +00:00
|
|
|
} else {
|
2012-02-01 23:20:51 +00:00
|
|
|
if (CPUName.empty()) {
|
|
|
|
#if defined (__x86_64__) || defined(__i386__)
|
|
|
|
CPUName = sys::getHostCPUName();
|
|
|
|
#else
|
|
|
|
CPUName = "generic";
|
|
|
|
#endif
|
|
|
|
}
|
2006-11-20 18:16:05 +00:00
|
|
|
// Otherwise, use CPUID to auto-detect feature set.
|
|
|
|
AutoDetectSubtargetFeatures();
|
2011-07-07 21:06:52 +00:00
|
|
|
|
2011-07-08 23:07:42 +00:00
|
|
|
// Make sure 64-bit features are available in 64-bit mode.
|
|
|
|
if (In64BitMode) {
|
2013-09-18 06:01:53 +00:00
|
|
|
if (!HasX86_64) { HasX86_64 = true; ToggleFeature(X86::Feature64Bit); }
|
|
|
|
if (!HasCMov) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
|
2011-07-08 23:07:42 +00:00
|
|
|
|
2012-01-09 09:02:13 +00:00
|
|
|
if (X86SSELevel < SSE2) {
|
2011-07-08 23:07:42 +00:00
|
|
|
X86SSELevel = SSE2;
|
2011-07-11 03:57:24 +00:00
|
|
|
ToggleFeature(X86::FeatureSSE1);
|
|
|
|
ToggleFeature(X86::FeatureSSE2);
|
|
|
|
}
|
2011-07-08 23:07:42 +00:00
|
|
|
}
|
2006-09-08 06:48:29 +00:00
|
|
|
}
|
2011-07-11 03:57:24 +00:00
|
|
|
|
2012-10-03 15:55:13 +00:00
|
|
|
// CPUName may have been set by the CPU detection code. Make sure the
|
|
|
|
// new MCSchedModel is used.
|
2013-09-18 05:54:09 +00:00
|
|
|
InitCPUSchedModel(CPUName);
|
2012-10-03 15:55:13 +00:00
|
|
|
|
2013-09-13 19:23:28 +00:00
|
|
|
if (X86ProcFamily == IntelAtom || X86ProcFamily == IntelSLM)
|
2012-02-01 23:20:51 +00:00
|
|
|
PostRAScheduler = true;
|
2012-08-07 00:25:30 +00:00
|
|
|
|
|
|
|
InstrItins = getInstrItineraryForCPU(CPUName);
|
2012-02-01 23:20:51 +00:00
|
|
|
|
2011-07-11 03:57:24 +00:00
|
|
|
// It's important to keep the MCSubtargetInfo feature bits in sync with
|
|
|
|
// target data structure which is shared with MC code emitter, etc.
|
|
|
|
if (In64BitMode)
|
|
|
|
ToggleFeature(X86::Mode64Bit);
|
2014-01-06 04:55:54 +00:00
|
|
|
else if (In32BitMode)
|
|
|
|
ToggleFeature(X86::Mode32Bit);
|
|
|
|
else if (In16BitMode)
|
|
|
|
ToggleFeature(X86::Mode16Bit);
|
|
|
|
else
|
|
|
|
llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
|
2011-07-11 03:57:24 +00:00
|
|
|
|
2010-01-05 01:29:13 +00:00
|
|
|
DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
|
2009-08-03 00:11:34 +00:00
|
|
|
<< ", 3DNowLevel " << X863DNowLevel
|
|
|
|
<< ", 64bit " << HasX86_64 << "\n");
|
2011-07-07 21:06:52 +00:00
|
|
|
assert((!In64BitMode || HasX86_64) &&
|
2009-02-03 00:04:43 +00:00
|
|
|
"64-bit code requested on a subtarget that doesn't support it!");
|
2006-09-08 06:48:29 +00:00
|
|
|
|
2012-11-09 20:10:44 +00:00
|
|
|
// Stack alignment is 16 bytes on Darwin, Linux and Solaris (both
|
2011-02-22 17:30:05 +00:00
|
|
|
// 32 and 64 bit) and for all 64-bit targets.
|
2011-06-23 17:54:54 +00:00
|
|
|
if (StackAlignOverride)
|
|
|
|
stackAlignment = StackAlignOverride;
|
2012-11-09 20:10:44 +00:00
|
|
|
else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
|
|
|
|
In64BitMode)
|
2005-07-12 01:41:54 +00:00
|
|
|
stackAlignment = 16;
|
2010-05-27 18:43:40 +00:00
|
|
|
}
|
2012-02-01 23:20:51 +00:00
|
|
|
|
2013-02-16 01:36:26 +00:00
|
|
|
void X86Subtarget::initializeEnvironment() {
|
|
|
|
X86SSELevel = NoMMXSSE;
|
|
|
|
X863DNowLevel = NoThreeDNow;
|
|
|
|
HasCMov = false;
|
|
|
|
HasX86_64 = false;
|
|
|
|
HasPOPCNT = false;
|
|
|
|
HasSSE4A = false;
|
|
|
|
HasAES = false;
|
|
|
|
HasPCLMUL = false;
|
|
|
|
HasFMA = false;
|
|
|
|
HasFMA4 = false;
|
|
|
|
HasXOP = false;
|
2013-09-24 18:21:52 +00:00
|
|
|
HasTBM = false;
|
2013-02-16 01:36:26 +00:00
|
|
|
HasMOVBE = false;
|
|
|
|
HasRDRAND = false;
|
|
|
|
HasF16C = false;
|
|
|
|
HasFSGSBase = false;
|
|
|
|
HasLZCNT = false;
|
|
|
|
HasBMI = false;
|
|
|
|
HasBMI2 = false;
|
|
|
|
HasRTM = false;
|
2013-03-26 22:46:02 +00:00
|
|
|
HasHLE = false;
|
2013-07-28 08:28:38 +00:00
|
|
|
HasERI = false;
|
|
|
|
HasCDI = false;
|
2013-08-20 05:23:59 +00:00
|
|
|
HasPFI = false;
|
2013-02-16 01:36:26 +00:00
|
|
|
HasADX = false;
|
2013-09-12 15:51:31 +00:00
|
|
|
HasSHA = false;
|
2013-03-26 17:47:11 +00:00
|
|
|
HasPRFCHW = false;
|
2013-03-28 23:41:26 +00:00
|
|
|
HasRDSEED = false;
|
2013-02-16 01:36:26 +00:00
|
|
|
IsBTMemSlow = false;
|
SHLD/SHRD are VectorPath (microcode) instructions known to have poor latency on certain architectures. While generating SHLD/SHRD instructions is acceptable when optimizing for size, optimizing for speed on these platforms should be implemented using alternative sequences of instructions composed of add, adc, shr, shl, or and lea which are directPath instructions. These alternative instructions not only have a lower latency but they also increase the decode bandwidth by allowing simultaneous decoding of a third directPath instruction.
AMD's processors family K7, K8, K10, K12, K15 and K16 are known to have SHLD/SHRD instructions with very poor latency. Optimization guides for these processors recommend using an alternative sequence of instructions. For these AMD's processors, I disabled folding (or (x << c) | (y >> (64 - c))) when we are not optimizing for size.
It might be beneficial to disable this folding for some of the Intel's processors. However, since I couldn't find specific recommendations regarding using SHLD/SHRD instructions on Intel's processors, I haven't disabled this peephole for Intel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195383 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 23:21:26 +00:00
|
|
|
IsSHLDSlow = false;
|
2013-02-16 01:36:26 +00:00
|
|
|
IsUAMemFast = false;
|
|
|
|
HasVectorUAMem = false;
|
|
|
|
HasCmpxchg16b = false;
|
|
|
|
UseLeaForSP = false;
|
|
|
|
HasSlowDivide = false;
|
|
|
|
PostRAScheduler = false;
|
|
|
|
PadShortFunctions = false;
|
2013-03-27 19:14:02 +00:00
|
|
|
CallRegIndirect = false;
|
2013-04-25 20:29:37 +00:00
|
|
|
LEAUsesAG = false;
|
2013-02-16 01:36:26 +00:00
|
|
|
stackAlignment = 4;
|
|
|
|
// FIXME: this is a known good value for Yonah. How about others?
|
|
|
|
MaxInlineSizeThreshold = 128;
|
|
|
|
}
|
|
|
|
|
2013-02-15 22:31:27 +00:00
|
|
|
X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
|
|
|
|
const std::string &FS,
|
2014-01-08 00:08:50 +00:00
|
|
|
unsigned StackAlignOverride)
|
2013-02-15 22:31:27 +00:00
|
|
|
: X86GenSubtargetInfo(TT, CPU, FS)
|
|
|
|
, X86ProcFamily(Others)
|
2013-02-15 23:22:32 +00:00
|
|
|
, PICStyle(PICStyles::None)
|
2013-02-15 22:31:27 +00:00
|
|
|
, TargetTriple(TT)
|
|
|
|
, StackAlignOverride(StackAlignOverride)
|
2014-01-08 00:08:50 +00:00
|
|
|
, In64BitMode(TargetTriple.getArch() == Triple::x86_64)
|
2014-01-20 12:02:25 +00:00
|
|
|
, In32BitMode(TargetTriple.getArch() == Triple::x86 &&
|
|
|
|
TargetTriple.getEnvironment() != Triple::CODE16)
|
|
|
|
, In16BitMode(TargetTriple.getArch() == Triple::x86 &&
|
|
|
|
TargetTriple.getEnvironment() == Triple::CODE16) {
|
2013-02-16 01:36:26 +00:00
|
|
|
initializeEnvironment();
|
2013-02-15 22:31:27 +00:00
|
|
|
resetSubtargetFeatures(CPU, FS);
|
|
|
|
}
|
|
|
|
|
2012-02-01 23:20:51 +00:00
|
|
|
bool X86Subtarget::enablePostRAScheduler(
|
|
|
|
CodeGenOpt::Level OptLevel,
|
|
|
|
TargetSubtargetInfo::AntiDepBreakMode& Mode,
|
|
|
|
RegClassVector& CriticalPathRCs) const {
|
2012-04-23 21:39:35 +00:00
|
|
|
Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
|
2012-02-01 23:20:51 +00:00
|
|
|
CriticalPathRCs.clear();
|
|
|
|
return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
|
|
|
|
}
|