2005-08-17 19:33:03 +00:00
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//===-- PPC32ISelDAGToDAG.cpp - PPC32 pattern matching inst selector ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for 32 bit PowerPC,
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// converting from a legalized dag to a PPC dag.
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//
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//===----------------------------------------------------------------------===//
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#include "PowerPC.h"
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#include "PPC32TargetMachine.h"
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#include "PPC32ISelLowering.h"
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2005-08-19 22:38:53 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SSARegMap.h"
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2005-08-17 19:33:03 +00:00
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/Statistic.h"
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2005-08-25 04:47:18 +00:00
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#include "llvm/Constants.h"
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2005-08-19 22:38:53 +00:00
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#include "llvm/GlobalValue.h"
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2005-08-17 19:33:03 +00:00
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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namespace {
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Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
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Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
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//===--------------------------------------------------------------------===//
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/// PPC32DAGToDAGISel - PPC32 specific code to select PPC32 machine
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/// instructions for SelectionDAG operations.
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///
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class PPC32DAGToDAGISel : public SelectionDAGISel {
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PPC32TargetLowering PPC32Lowering;
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unsigned GlobalBaseReg;
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2005-08-17 19:33:03 +00:00
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public:
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PPC32DAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {}
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2005-08-19 22:38:53 +00:00
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virtual bool runOnFunction(Function &Fn) {
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// Make sure we re-emit a set of the global base reg if necessary
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GlobalBaseReg = 0;
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return SelectionDAGISel::runOnFunction(Fn);
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}
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2005-08-17 19:33:03 +00:00
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
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inline SDOperand getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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2005-08-19 22:38:53 +00:00
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/// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
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/// base register. Return the virtual register that holds this value.
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2005-08-21 22:31:09 +00:00
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SDOperand getGlobalBaseReg();
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2005-08-17 19:33:03 +00:00
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDOperand Select(SDOperand Op);
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SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
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unsigned OCHi, unsigned OCLo,
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bool IsArithmetic = false,
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bool Negate = false);
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2005-08-19 00:38:14 +00:00
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SDNode *SelectBitfieldInsert(SDNode *N);
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2005-08-21 18:50:37 +00:00
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/// SelectCC - Select a comparison of the specified values with the
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/// specified condition code, returning the CR# of the expression.
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SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
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2005-08-21 22:31:09 +00:00
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/// SelectAddr - Given the specified address, return the two operands for a
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/// load/store instruction, and return true if it should be an indexed [r+r]
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/// operation.
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bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
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2005-08-25 22:04:30 +00:00
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SDOperand BuildSDIVSequence(SDNode *N);
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SDOperand BuildUDIVSequence(SDNode *N);
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2005-08-17 19:33:03 +00:00
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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2005-08-18 18:46:06 +00:00
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// Select target instructions for the DAG.
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2005-08-29 01:07:02 +00:00
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DAG.setRoot(Select(DAG.getRoot()));
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2005-08-17 19:33:03 +00:00
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DAG.RemoveDeadNodes();
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2005-08-18 18:46:06 +00:00
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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2005-08-17 19:33:03 +00:00
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}
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virtual const char *getPassName() const {
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return "PowerPC DAG->DAG Pattern Instruction Selection";
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}
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};
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}
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2005-08-19 22:38:53 +00:00
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/// getGlobalBaseReg - Output the instructions required to put the
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/// base address to use for accessing globals into a register.
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///
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SDOperand PPC32DAGToDAGISel::getGlobalBaseReg() {
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2005-08-19 22:38:53 +00:00
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if (!GlobalBaseReg) {
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// Insert the set of GlobalBaseReg into the first MBB of the function
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MachineBasicBlock &FirstMBB = BB->getParent()->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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SSARegMap *RegMap = BB->getParent()->getSSARegMap();
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GlobalBaseReg = RegMap->createVirtualRegister(PPC32::GPRCRegisterClass);
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BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
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BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
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}
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2005-08-21 22:31:09 +00:00
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return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
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2005-08-19 22:38:53 +00:00
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}
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2005-08-18 05:00:13 +00:00
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// isIntImmediate - This method tests to see if a constant operand.
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// If so Imm will receive the 32 bit value.
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static bool isIntImmediate(SDNode *N, unsigned& Imm) {
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if (N->getOpcode() == ISD::Constant) {
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Imm = cast<ConstantSDNode>(N)->getValue();
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return true;
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}
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return false;
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}
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2005-08-18 07:30:46 +00:00
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// isOprShiftImm - Returns true if the specified operand is a shift opcode with
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// a immediate shift count less than 32.
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static bool isOprShiftImm(SDNode *N, unsigned& Opc, unsigned& SH) {
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Opc = N->getOpcode();
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return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
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isIntImmediate(N->getOperand(1).Val, SH) && SH < 32;
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}
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// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
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// any number of 0s on either side. The 1s are allowed to wrap from LSB to
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// MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
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// not, since all 1s are not contiguous.
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static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
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if (isShiftedMask_32(Val)) {
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// look for the first non-zero bit
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MB = CountLeadingZeros_32(Val);
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// look for the first zero bit after the run of ones
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ME = CountLeadingZeros_32((Val - 1) ^ Val);
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return true;
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2005-08-25 04:47:18 +00:00
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} else {
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Val = ~Val; // invert mask
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if (isShiftedMask_32(Val)) {
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// effectively look for the first zero bit
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ME = CountLeadingZeros_32(Val) - 1;
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// effectively look for the first one bit after the run of zeros
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MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
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return true;
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}
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2005-08-18 07:30:46 +00:00
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}
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// no run present
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return false;
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}
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// isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate
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// and mask opcode and mask operation.
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static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
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unsigned &SH, unsigned &MB, unsigned &ME) {
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unsigned Shift = 32;
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unsigned Indeterminant = ~0; // bit mask marking indeterminant results
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unsigned Opcode = N->getOpcode();
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2005-08-30 00:59:16 +00:00
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if (N->getNumOperands() != 2 ||
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!isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
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2005-08-18 07:30:46 +00:00
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return false;
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if (Opcode == ISD::SHL) {
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// apply shift left to mask if it comes first
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if (IsShiftMask) Mask = Mask << Shift;
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// determine which bits are made indeterminant by shift
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Indeterminant = ~(0xFFFFFFFFu << Shift);
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} else if (Opcode == ISD::SRA || Opcode == ISD::SRL) {
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// apply shift right to mask if it comes first
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if (IsShiftMask) Mask = Mask >> Shift;
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// determine which bits are made indeterminant by shift
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Indeterminant = ~(0xFFFFFFFFu >> Shift);
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// adjust for the left rotate
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Shift = 32 - Shift;
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} else {
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return false;
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}
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// if the mask doesn't intersect any Indeterminant bits
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if (Mask && !(Mask & Indeterminant)) {
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SH = Shift;
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// make sure the mask is still a mask (wrap arounds may not be)
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return isRunOfOnes(Mask, MB, ME);
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}
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return false;
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}
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2005-08-18 05:00:13 +00:00
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// isOpcWithIntImmediate - This method tests to see if the node is a specific
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// opcode and that it has a immediate integer right operand.
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// If so Imm will receive the 32 bit value.
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static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
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return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
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}
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// isOprNot - Returns true if the specified operand is an xor with immediate -1.
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static bool isOprNot(SDNode *N) {
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unsigned Imm;
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return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1;
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}
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2005-08-17 19:33:03 +00:00
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// Immediate constant composers.
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// Lo16 - grabs the lo 16 bits from a 32 bit constant.
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// Hi16 - grabs the hi 16 bits from a 32 bit constant.
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// HA16 - computes the hi bits required if the lo bits are add/subtracted in
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// arithmethically.
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static unsigned Lo16(unsigned x) { return x & 0x0000FFFF; }
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static unsigned Hi16(unsigned x) { return Lo16(x >> 16); }
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static unsigned HA16(unsigned x) { return Hi16((signed)x - (signed short)x); }
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// isIntImmediate - This method tests to see if a constant operand.
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// If so Imm will receive the 32 bit value.
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static bool isIntImmediate(SDOperand N, unsigned& Imm) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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Imm = (unsigned)CN->getSignExtended();
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return true;
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}
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return false;
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}
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2005-08-19 00:38:14 +00:00
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/// SelectBitfieldInsert - turn an or of two masked values into
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/// the rotate left word immediate then mask insert (rlwimi) instruction.
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/// Returns true on success, false if the caller still needs to select OR.
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///
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/// Patterns matched:
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/// 1. or shl, and 5. or and, and
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/// 2. or and, shl 6. or shl, shr
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/// 3. or shr, and 7. or shr, shl
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/// 4. or and, shr
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SDNode *PPC32DAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
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bool IsRotate = false;
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unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
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unsigned Value;
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SDOperand Op0 = N->getOperand(0);
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SDOperand Op1 = N->getOperand(1);
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unsigned Op0Opc = Op0.getOpcode();
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unsigned Op1Opc = Op1.getOpcode();
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// Verify that we have the correct opcodes
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if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
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return false;
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if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
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return false;
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// Generate Mask value for Target
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if (isIntImmediate(Op0.getOperand(1), Value)) {
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switch(Op0Opc) {
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2005-08-30 18:37:48 +00:00
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case ISD::SHL: TgtMask <<= Value; break;
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case ISD::SRL: TgtMask >>= Value; break;
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case ISD::AND: TgtMask &= Value; break;
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2005-08-19 00:38:14 +00:00
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}
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} else {
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return 0;
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}
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// Generate Mask value for Insert
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2005-08-30 18:37:48 +00:00
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if (!isIntImmediate(Op1.getOperand(1), Value))
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2005-08-19 00:38:14 +00:00
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return 0;
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2005-08-30 18:37:48 +00:00
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switch(Op1Opc) {
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case ISD::SHL:
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SH = Value;
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InsMask <<= SH;
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if (Op0Opc == ISD::SRL) IsRotate = true;
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break;
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case ISD::SRL:
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SH = Value;
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InsMask >>= SH;
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SH = 32-SH;
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if (Op0Opc == ISD::SHL) IsRotate = true;
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break;
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case ISD::AND:
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InsMask &= Value;
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break;
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2005-08-19 00:38:14 +00:00
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}
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// If both of the inputs are ANDs and one of them has a logical shift by
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// constant as its input, make that AND the inserted value so that we can
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// combine the shift into the rotate part of the rlwimi instruction
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bool IsAndWithShiftOp = false;
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if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
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if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
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Op1.getOperand(0).getOpcode() == ISD::SRL) {
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if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
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SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
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IsAndWithShiftOp = true;
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}
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} else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
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Op0.getOperand(0).getOpcode() == ISD::SRL) {
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if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
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std::swap(Op0, Op1);
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std::swap(TgtMask, InsMask);
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SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
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IsAndWithShiftOp = true;
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}
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}
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}
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// Verify that the Target mask and Insert mask together form a full word mask
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// and that the Insert mask is a run of set bits (which implies both are runs
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// of set bits). Given that, Select the arguments and generate the rlwimi
|
|
|
|
// instruction.
|
|
|
|
unsigned MB, ME;
|
|
|
|
if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) {
|
|
|
|
bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
|
|
|
|
bool Op0IsAND = Op0Opc == ISD::AND;
|
|
|
|
// Check for rotlwi / rotrwi here, a special case of bitfield insert
|
|
|
|
// where both bitfield halves are sourced from the same value.
|
|
|
|
if (IsRotate && fullMask &&
|
|
|
|
N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
|
|
|
|
Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32,
|
|
|
|
Select(N->getOperand(0).getOperand(0)),
|
|
|
|
getI32Imm(SH), getI32Imm(0), getI32Imm(31));
|
|
|
|
return Op0.Val;
|
|
|
|
}
|
|
|
|
SDOperand Tmp1 = (Op0IsAND && fullMask) ? Select(Op0.getOperand(0))
|
|
|
|
: Select(Op0);
|
|
|
|
SDOperand Tmp2 = IsAndWithShiftOp ? Select(Op1.getOperand(0).getOperand(0))
|
|
|
|
: Select(Op1.getOperand(0));
|
|
|
|
Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
|
|
|
|
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
|
|
|
|
return Op0.Val;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-08-17 19:33:03 +00:00
|
|
|
// SelectIntImmediateExpr - Choose code for integer operations with an immediate
|
|
|
|
// operand.
|
|
|
|
SDNode *PPC32DAGToDAGISel::SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
|
|
|
|
unsigned OCHi, unsigned OCLo,
|
|
|
|
bool IsArithmetic,
|
|
|
|
bool Negate) {
|
|
|
|
// Check to make sure this is a constant.
|
|
|
|
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS);
|
|
|
|
// Exit if not a constant.
|
|
|
|
if (!CN) return 0;
|
|
|
|
// Extract immediate.
|
|
|
|
unsigned C = (unsigned)CN->getValue();
|
|
|
|
// Negate if required (ISD::SUB).
|
|
|
|
if (Negate) C = -C;
|
|
|
|
// Get the hi and lo portions of constant.
|
|
|
|
unsigned Hi = IsArithmetic ? HA16(C) : Hi16(C);
|
|
|
|
unsigned Lo = Lo16(C);
|
|
|
|
|
|
|
|
// If two instructions are needed and usage indicates it would be better to
|
|
|
|
// load immediate into a register, bail out.
|
|
|
|
if (Hi && Lo && CN->use_size() > 2) return false;
|
|
|
|
|
|
|
|
// Select the first operand.
|
|
|
|
SDOperand Opr0 = Select(LHS);
|
|
|
|
|
|
|
|
if (Lo) // Add in the lo-part.
|
|
|
|
Opr0 = CurDAG->getTargetNode(OCLo, MVT::i32, Opr0, getI32Imm(Lo));
|
|
|
|
if (Hi) // Add in the hi-part.
|
|
|
|
Opr0 = CurDAG->getTargetNode(OCHi, MVT::i32, Opr0, getI32Imm(Hi));
|
|
|
|
return Opr0.Val;
|
|
|
|
}
|
|
|
|
|
2005-08-21 22:31:09 +00:00
|
|
|
/// SelectAddr - Given the specified address, return the two operands for a
|
|
|
|
/// load/store instruction, and return true if it should be an indexed [r+r]
|
|
|
|
/// operation.
|
|
|
|
bool PPC32DAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
|
|
|
|
SDOperand &Op2) {
|
|
|
|
unsigned imm = 0;
|
|
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
|
|
|
if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) {
|
|
|
|
Op1 = getI32Imm(Lo16(imm));
|
2005-08-25 00:45:43 +00:00
|
|
|
if (FrameIndexSDNode *FI =
|
|
|
|
dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
|
2005-08-21 22:31:09 +00:00
|
|
|
++FrameOff;
|
2005-08-25 00:45:43 +00:00
|
|
|
Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
|
2005-08-21 22:31:09 +00:00
|
|
|
} else {
|
|
|
|
Op2 = Select(Addr.getOperand(0));
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
Op1 = Select(Addr.getOperand(0));
|
|
|
|
Op2 = Select(Addr.getOperand(1));
|
|
|
|
return true; // [r+r]
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Now check if we're dealing with a global, and whether or not we should emit
|
|
|
|
// an optimized load or store for statics.
|
|
|
|
if (GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Addr)) {
|
|
|
|
GlobalValue *GV = GN->getGlobal();
|
|
|
|
if (!GV->hasWeakLinkage() && !GV->isExternal()) {
|
|
|
|
Op1 = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
|
|
|
|
if (PICEnabled)
|
|
|
|
Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),
|
|
|
|
Op1);
|
|
|
|
else
|
|
|
|
Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
|
|
|
|
return false;
|
|
|
|
}
|
2005-08-25 00:45:43 +00:00
|
|
|
} else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
|
2005-08-21 22:31:09 +00:00
|
|
|
Op1 = getI32Imm(0);
|
2005-08-25 00:45:43 +00:00
|
|
|
Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
|
2005-08-21 22:31:09 +00:00
|
|
|
return false;
|
|
|
|
} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Addr)) {
|
|
|
|
Op1 = Addr;
|
|
|
|
if (PICEnabled)
|
|
|
|
Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),Op1);
|
|
|
|
else
|
|
|
|
Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
Op1 = getI32Imm(0);
|
|
|
|
Op2 = Select(Addr);
|
|
|
|
return false;
|
|
|
|
}
|
2005-08-17 19:33:03 +00:00
|
|
|
|
2005-08-21 18:50:37 +00:00
|
|
|
/// SelectCC - Select a comparison of the specified values with the specified
|
|
|
|
/// condition code, returning the CR# of the expression.
|
|
|
|
SDOperand PPC32DAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
|
|
|
|
ISD::CondCode CC) {
|
|
|
|
// Always select the LHS.
|
|
|
|
LHS = Select(LHS);
|
|
|
|
|
|
|
|
// Use U to determine whether the SETCC immediate range is signed or not.
|
|
|
|
if (MVT::isInteger(LHS.getValueType())) {
|
|
|
|
bool U = ISD::isUnsignedIntSetCC(CC);
|
|
|
|
unsigned Imm;
|
|
|
|
if (isIntImmediate(RHS, Imm) &&
|
|
|
|
((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
|
|
|
|
return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32,
|
|
|
|
LHS, getI32Imm(Lo16(Imm)));
|
|
|
|
return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
|
|
|
|
LHS, Select(RHS));
|
|
|
|
} else {
|
|
|
|
return CurDAG->getTargetNode(PPC::FCMPU, MVT::i32, LHS, Select(RHS));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
|
|
|
|
/// to Condition.
|
|
|
|
static unsigned getBCCForSetCC(ISD::CondCode CC) {
|
|
|
|
switch (CC) {
|
|
|
|
default: assert(0 && "Unknown condition!"); abort();
|
|
|
|
case ISD::SETEQ: return PPC::BEQ;
|
|
|
|
case ISD::SETNE: return PPC::BNE;
|
|
|
|
case ISD::SETULT:
|
|
|
|
case ISD::SETLT: return PPC::BLT;
|
|
|
|
case ISD::SETULE:
|
|
|
|
case ISD::SETLE: return PPC::BLE;
|
|
|
|
case ISD::SETUGT:
|
|
|
|
case ISD::SETGT: return PPC::BGT;
|
|
|
|
case ISD::SETUGE:
|
|
|
|
case ISD::SETGE: return PPC::BGE;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-08-25 20:08:18 +00:00
|
|
|
/// getCRIdxForSetCC - Return the index of the condition register field
|
|
|
|
/// associated with the SetCC condition, and whether or not the field is
|
|
|
|
/// treated as inverted. That is, lt = 0; ge = 0 inverted.
|
|
|
|
static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
|
|
|
|
switch (CC) {
|
|
|
|
default: assert(0 && "Unknown condition!"); abort();
|
|
|
|
case ISD::SETULT:
|
|
|
|
case ISD::SETLT: Inv = false; return 0;
|
|
|
|
case ISD::SETUGE:
|
|
|
|
case ISD::SETGE: Inv = true; return 0;
|
|
|
|
case ISD::SETUGT:
|
|
|
|
case ISD::SETGT: Inv = false; return 1;
|
|
|
|
case ISD::SETULE:
|
|
|
|
case ISD::SETLE: Inv = true; return 1;
|
|
|
|
case ISD::SETEQ: Inv = false; return 2;
|
|
|
|
case ISD::SETNE: Inv = true; return 2;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
2005-08-21 22:31:09 +00:00
|
|
|
|
2005-08-25 22:04:30 +00:00
|
|
|
// Structure used to return the necessary information to codegen an SDIV as
|
|
|
|
// a multiply.
|
|
|
|
struct ms {
|
|
|
|
int m; // magic number
|
|
|
|
int s; // shift amount
|
|
|
|
};
|
|
|
|
|
|
|
|
struct mu {
|
|
|
|
unsigned int m; // magic number
|
|
|
|
int a; // add indicator
|
|
|
|
int s; // shift amount
|
|
|
|
};
|
|
|
|
|
|
|
|
/// magic - calculate the magic numbers required to codegen an integer sdiv as
|
|
|
|
/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
|
|
|
|
/// or -1.
|
|
|
|
static struct ms magic(int d) {
|
|
|
|
int p;
|
|
|
|
unsigned int ad, anc, delta, q1, r1, q2, r2, t;
|
|
|
|
const unsigned int two31 = 0x80000000U;
|
|
|
|
struct ms mag;
|
|
|
|
|
|
|
|
ad = abs(d);
|
|
|
|
t = two31 + ((unsigned int)d >> 31);
|
|
|
|
anc = t - 1 - t%ad; // absolute value of nc
|
|
|
|
p = 31; // initialize p
|
|
|
|
q1 = two31/anc; // initialize q1 = 2p/abs(nc)
|
|
|
|
r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
|
|
|
|
q2 = two31/ad; // initialize q2 = 2p/abs(d)
|
|
|
|
r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
|
|
|
|
do {
|
|
|
|
p = p + 1;
|
|
|
|
q1 = 2*q1; // update q1 = 2p/abs(nc)
|
|
|
|
r1 = 2*r1; // update r1 = rem(2p/abs(nc))
|
|
|
|
if (r1 >= anc) { // must be unsigned comparison
|
|
|
|
q1 = q1 + 1;
|
|
|
|
r1 = r1 - anc;
|
|
|
|
}
|
|
|
|
q2 = 2*q2; // update q2 = 2p/abs(d)
|
|
|
|
r2 = 2*r2; // update r2 = rem(2p/abs(d))
|
|
|
|
if (r2 >= ad) { // must be unsigned comparison
|
|
|
|
q2 = q2 + 1;
|
|
|
|
r2 = r2 - ad;
|
|
|
|
}
|
|
|
|
delta = ad - r2;
|
|
|
|
} while (q1 < delta || (q1 == delta && r1 == 0));
|
|
|
|
|
|
|
|
mag.m = q2 + 1;
|
|
|
|
if (d < 0) mag.m = -mag.m; // resulting magic number
|
|
|
|
mag.s = p - 32; // resulting shift
|
|
|
|
return mag;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// magicu - calculate the magic numbers required to codegen an integer udiv as
|
|
|
|
/// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
|
|
|
|
static struct mu magicu(unsigned d)
|
|
|
|
{
|
|
|
|
int p;
|
|
|
|
unsigned int nc, delta, q1, r1, q2, r2;
|
|
|
|
struct mu magu;
|
|
|
|
magu.a = 0; // initialize "add" indicator
|
|
|
|
nc = - 1 - (-d)%d;
|
|
|
|
p = 31; // initialize p
|
|
|
|
q1 = 0x80000000/nc; // initialize q1 = 2p/nc
|
|
|
|
r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
|
|
|
|
q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
|
|
|
|
r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
|
|
|
|
do {
|
|
|
|
p = p + 1;
|
|
|
|
if (r1 >= nc - r1 ) {
|
|
|
|
q1 = 2*q1 + 1; // update q1
|
|
|
|
r1 = 2*r1 - nc; // update r1
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
q1 = 2*q1; // update q1
|
|
|
|
r1 = 2*r1; // update r1
|
|
|
|
}
|
|
|
|
if (r2 + 1 >= d - r2) {
|
|
|
|
if (q2 >= 0x7FFFFFFF) magu.a = 1;
|
|
|
|
q2 = 2*q2 + 1; // update q2
|
|
|
|
r2 = 2*r2 + 1 - d; // update r2
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
if (q2 >= 0x80000000) magu.a = 1;
|
|
|
|
q2 = 2*q2; // update q2
|
|
|
|
r2 = 2*r2 + 1; // update r2
|
|
|
|
}
|
|
|
|
delta = d - 1 - r2;
|
|
|
|
} while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
|
|
|
|
magu.m = q2 + 1; // resulting magic number
|
|
|
|
magu.s = p - 32; // resulting shift
|
|
|
|
return magu;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
|
|
|
|
/// return a DAG expression to select that will generate the same value by
|
|
|
|
/// multiplying by a magic number. See:
|
|
|
|
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
|
|
|
|
SDOperand PPC32DAGToDAGISel::BuildSDIVSequence(SDNode *N) {
|
|
|
|
int d = (int)cast<ConstantSDNode>(N->getOperand(1))->getValue();
|
|
|
|
ms magics = magic(d);
|
|
|
|
// Multiply the numerator (operand 0) by the magic value
|
|
|
|
SDOperand Q = CurDAG->getNode(ISD::MULHS, MVT::i32, N->getOperand(0),
|
|
|
|
CurDAG->getConstant(magics.m, MVT::i32));
|
|
|
|
// If d > 0 and m < 0, add the numerator
|
|
|
|
if (d > 0 && magics.m < 0)
|
|
|
|
Q = CurDAG->getNode(ISD::ADD, MVT::i32, Q, N->getOperand(0));
|
|
|
|
// If d < 0 and m > 0, subtract the numerator.
|
|
|
|
if (d < 0 && magics.m > 0)
|
|
|
|
Q = CurDAG->getNode(ISD::SUB, MVT::i32, Q, N->getOperand(0));
|
|
|
|
// Shift right algebraic if shift value is nonzero
|
|
|
|
if (magics.s > 0)
|
|
|
|
Q = CurDAG->getNode(ISD::SRA, MVT::i32, Q,
|
|
|
|
CurDAG->getConstant(magics.s, MVT::i32));
|
|
|
|
// Extract the sign bit and add it to the quotient
|
|
|
|
SDOperand T =
|
|
|
|
CurDAG->getNode(ISD::SRL, MVT::i32, Q, CurDAG->getConstant(31, MVT::i32));
|
|
|
|
return CurDAG->getNode(ISD::ADD, MVT::i32, Q, T);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
|
|
|
|
/// return a DAG expression to select that will generate the same value by
|
|
|
|
/// multiplying by a magic number. See:
|
|
|
|
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
|
|
|
|
SDOperand PPC32DAGToDAGISel::BuildUDIVSequence(SDNode *N) {
|
|
|
|
unsigned d = (unsigned)cast<ConstantSDNode>(N->getOperand(1))->getValue();
|
|
|
|
mu magics = magicu(d);
|
|
|
|
// Multiply the numerator (operand 0) by the magic value
|
|
|
|
SDOperand Q = CurDAG->getNode(ISD::MULHU, MVT::i32, N->getOperand(0),
|
|
|
|
CurDAG->getConstant(magics.m, MVT::i32));
|
|
|
|
if (magics.a == 0) {
|
|
|
|
return CurDAG->getNode(ISD::SRL, MVT::i32, Q,
|
|
|
|
CurDAG->getConstant(magics.s, MVT::i32));
|
|
|
|
} else {
|
|
|
|
SDOperand NPQ = CurDAG->getNode(ISD::SUB, MVT::i32, N->getOperand(0), Q);
|
|
|
|
NPQ = CurDAG->getNode(ISD::SRL, MVT::i32, NPQ,
|
|
|
|
CurDAG->getConstant(1, MVT::i32));
|
|
|
|
NPQ = CurDAG->getNode(ISD::ADD, MVT::i32, NPQ, Q);
|
|
|
|
return CurDAG->getNode(ISD::SRL, MVT::i32, NPQ,
|
|
|
|
CurDAG->getConstant(magics.s-1, MVT::i32));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-08-17 19:33:03 +00:00
|
|
|
// Select - Convert the specified operand from a target-independent to a
|
|
|
|
// target-specific node if it hasn't already been changed.
|
|
|
|
SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
|
|
|
|
SDNode *N = Op.Val;
|
2005-08-26 20:25:03 +00:00
|
|
|
if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
|
|
|
|
N->getOpcode() < PPCISD::FIRST_NUMBER)
|
2005-08-17 19:33:03 +00:00
|
|
|
return Op; // Already selected.
|
|
|
|
|
|
|
|
switch (N->getOpcode()) {
|
|
|
|
default:
|
|
|
|
std::cerr << "Cannot yet select: ";
|
|
|
|
N->dump();
|
|
|
|
std::cerr << "\n";
|
|
|
|
abort();
|
|
|
|
case ISD::EntryToken: // These leaves remain the same.
|
|
|
|
return Op;
|
2005-08-31 18:08:46 +00:00
|
|
|
case ISD::AssertSext:
|
|
|
|
case ISD::AssertZext:
|
|
|
|
return Select(N->getOperand(0));
|
2005-08-17 19:33:03 +00:00
|
|
|
case ISD::TokenFactor: {
|
|
|
|
SDOperand New;
|
|
|
|
if (N->getNumOperands() == 2) {
|
|
|
|
SDOperand Op0 = Select(N->getOperand(0));
|
|
|
|
SDOperand Op1 = Select(N->getOperand(1));
|
|
|
|
New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
|
|
|
|
} else {
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
|
2005-08-19 21:33:02 +00:00
|
|
|
Ops.push_back(Select(N->getOperand(i)));
|
2005-08-17 19:33:03 +00:00
|
|
|
New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (New.Val != N) {
|
2005-08-26 18:37:23 +00:00
|
|
|
CurDAG->ReplaceAllUsesWith(Op, New);
|
2005-08-17 19:33:03 +00:00
|
|
|
N = New.Val;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::CopyFromReg: {
|
|
|
|
SDOperand Chain = Select(N->getOperand(0));
|
|
|
|
if (Chain == N->getOperand(0)) return Op; // No change
|
|
|
|
SDOperand New = CurDAG->getCopyFromReg(Chain,
|
|
|
|
cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
|
|
|
|
return New.getValue(Op.ResNo);
|
|
|
|
}
|
|
|
|
case ISD::CopyToReg: {
|
|
|
|
SDOperand Chain = Select(N->getOperand(0));
|
|
|
|
SDOperand Reg = N->getOperand(1);
|
|
|
|
SDOperand Val = Select(N->getOperand(2));
|
|
|
|
if (Chain != N->getOperand(0) || Val != N->getOperand(2)) {
|
|
|
|
SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
|
|
|
|
Chain, Reg, Val);
|
2005-08-26 18:37:23 +00:00
|
|
|
CurDAG->ReplaceAllUsesWith(Op, New);
|
2005-08-17 19:33:03 +00:00
|
|
|
N = New.Val;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::Constant: {
|
|
|
|
assert(N->getValueType(0) == MVT::i32);
|
|
|
|
unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
|
2005-08-29 01:01:01 +00:00
|
|
|
|
|
|
|
// NOTE: This doesn't use SelectNodeTo, because doing that will prevent
|
|
|
|
// folding shared immediates into other the second instruction that
|
|
|
|
// uses it.
|
2005-09-01 19:38:28 +00:00
|
|
|
if (isInt16(v))
|
2005-08-29 01:01:01 +00:00
|
|
|
return CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(v));
|
2005-09-01 19:38:28 +00:00
|
|
|
|
|
|
|
unsigned Hi = Hi16(v);
|
|
|
|
unsigned Lo = Lo16(v);
|
|
|
|
|
|
|
|
if (!Lo)
|
|
|
|
return CurDAG->getTargetNode(PPC::LIS, MVT::i32, getI32Imm(Hi));
|
|
|
|
|
|
|
|
SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32, getI32Imm(Hi));
|
|
|
|
return CurDAG->getTargetNode(PPC::ORI, MVT::i32, Top, getI32Imm(Lo));
|
2005-08-17 19:33:03 +00:00
|
|
|
}
|
2005-08-24 23:08:16 +00:00
|
|
|
case ISD::UNDEF:
|
|
|
|
if (N->getValueType(0) == MVT::i32)
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32);
|
2005-08-24 23:08:16 +00:00
|
|
|
else
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_FP, N->getValueType(0));
|
2005-08-24 23:08:16 +00:00
|
|
|
break;
|
2005-08-25 00:45:43 +00:00
|
|
|
case ISD::FrameIndex: {
|
|
|
|
int FI = cast<FrameIndexSDNode>(N)->getIndex();
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
|
2005-08-25 00:45:43 +00:00
|
|
|
CurDAG->getTargetFrameIndex(FI, MVT::i32),
|
|
|
|
getI32Imm(0));
|
|
|
|
break;
|
|
|
|
}
|
2005-08-25 05:04:11 +00:00
|
|
|
case ISD::ConstantPool: {
|
2005-08-26 17:15:30 +00:00
|
|
|
Constant *C = cast<ConstantPoolSDNode>(N)->get();
|
|
|
|
SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i32);
|
2005-08-25 05:04:11 +00:00
|
|
|
if (PICEnabled)
|
|
|
|
Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
|
|
|
|
else
|
|
|
|
Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
|
2005-08-25 05:04:11 +00:00
|
|
|
break;
|
|
|
|
}
|
2005-08-19 22:38:53 +00:00
|
|
|
case ISD::GlobalAddress: {
|
|
|
|
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
|
|
|
|
SDOperand Tmp;
|
|
|
|
SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
|
2005-08-21 22:31:09 +00:00
|
|
|
if (PICEnabled)
|
|
|
|
Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), GA);
|
|
|
|
else
|
2005-08-19 22:38:53 +00:00
|
|
|
Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, GA);
|
2005-08-21 22:31:09 +00:00
|
|
|
|
2005-08-19 22:38:53 +00:00
|
|
|
if (GV->hasWeakLinkage() || GV->isExternal())
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::LWZ, MVT::i32, GA, Tmp);
|
2005-08-19 22:38:53 +00:00
|
|
|
else
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, GA);
|
2005-08-19 22:38:53 +00:00
|
|
|
break;
|
|
|
|
}
|
2005-08-29 23:30:11 +00:00
|
|
|
case ISD::DYNAMIC_STACKALLOC: {
|
|
|
|
// FIXME: We are currently ignoring the requested alignment for handling
|
|
|
|
// greater than the stack alignment. This will need to be revisited at some
|
|
|
|
// point. Align = N.getOperand(2);
|
|
|
|
if (!isa<ConstantSDNode>(N->getOperand(2)) ||
|
|
|
|
cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
|
|
|
|
std::cerr << "Cannot allocate stack object with greater alignment than"
|
|
|
|
<< " the stack alignment yet!";
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
SDOperand Chain = Select(N->getOperand(0));
|
|
|
|
SDOperand Amt = Select(N->getOperand(1));
|
|
|
|
|
|
|
|
SDOperand R1Reg = CurDAG->getRegister(PPC::R1, MVT::i32);
|
|
|
|
|
Implement dynamic allocas correctly. In particular, because we were copying
directly out of R1 (without using a CopyFromReg, which uses a chain), multiple
allocas were getting CSE'd together, producing bogus code. For this:
int %foo(bool %X, int %A, int %B) {
br bool %X, label %T, label %F
F:
%G = alloca int
%H = alloca int
store int %A, int* %G
store int %B, int* %H
%R = load int* %G
ret int %R
T:
ret int 0
}
We were generating:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
li r2, 16
subf r2, r2, r1 ;; One alloca
or r1, r2, r2
or r3, r1, r1
or r1, r2, r2
or r2, r1, r1
stw r4, 0(r3)
stw r5, 0(r2)
lwz r3, 0(r3)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
Now we generate:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
or r2, r1, r1
li r3, 16
subf r2, r3, r2 ;; Alloca 1
or r1, r2, r2
or r2, r1, r1
or r6, r1, r1
subf r3, r3, r6 ;; Alloca 2
or r1, r3, r3
or r3, r1, r1
stw r4, 0(r2)
stw r5, 0(r3)
lwz r3, 0(r2)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
This fixes Povray and SPASS with the dag isel, the last two failing cases.
Tommorow we will hopefully turn it on by default! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23190 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-01 21:31:30 +00:00
|
|
|
SDOperand R1Val = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
|
|
|
|
Chain = R1Val.getValue(1);
|
|
|
|
|
2005-08-29 23:30:11 +00:00
|
|
|
// Subtract the amount (guaranteed to be a multiple of the stack alignment)
|
|
|
|
// from the stack pointer, giving us the result pointer.
|
Implement dynamic allocas correctly. In particular, because we were copying
directly out of R1 (without using a CopyFromReg, which uses a chain), multiple
allocas were getting CSE'd together, producing bogus code. For this:
int %foo(bool %X, int %A, int %B) {
br bool %X, label %T, label %F
F:
%G = alloca int
%H = alloca int
store int %A, int* %G
store int %B, int* %H
%R = load int* %G
ret int %R
T:
ret int 0
}
We were generating:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
li r2, 16
subf r2, r2, r1 ;; One alloca
or r1, r2, r2
or r3, r1, r1
or r1, r2, r2
or r2, r1, r1
stw r4, 0(r3)
stw r5, 0(r2)
lwz r3, 0(r3)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
Now we generate:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
or r2, r1, r1
li r3, 16
subf r2, r3, r2 ;; Alloca 1
or r1, r2, r2
or r2, r1, r1
or r6, r1, r1
subf r3, r3, r6 ;; Alloca 2
or r1, r3, r3
or r3, r1, r1
stw r4, 0(r2)
stw r5, 0(r3)
lwz r3, 0(r2)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
This fixes Povray and SPASS with the dag isel, the last two failing cases.
Tommorow we will hopefully turn it on by default! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23190 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-01 21:31:30 +00:00
|
|
|
SDOperand Result = CurDAG->getTargetNode(PPC::SUBF, MVT::i32, Amt, R1Val);
|
2005-08-29 23:30:11 +00:00
|
|
|
|
|
|
|
// Copy this result back into R1.
|
|
|
|
Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R1Reg, Result);
|
|
|
|
|
|
|
|
// Copy this result back out of R1 to make sure we're not using the stack
|
|
|
|
// space without decrementing the stack pointer.
|
|
|
|
Result = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
|
|
|
|
|
|
|
|
// Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
|
|
|
|
CurDAG->ReplaceAllUsesWith(N, Result.Val);
|
|
|
|
N = Result.Val;
|
|
|
|
break;
|
|
|
|
}
|
2005-08-18 03:04:18 +00:00
|
|
|
case ISD::SIGN_EXTEND_INREG:
|
|
|
|
switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
|
|
|
|
default: assert(0 && "Illegal type in SIGN_EXTEND_INREG"); break;
|
|
|
|
case MVT::i16:
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::EXTSH, MVT::i32, Select(N->getOperand(0)));
|
2005-08-18 03:04:18 +00:00
|
|
|
break;
|
|
|
|
case MVT::i8:
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::EXTSB, MVT::i32, Select(N->getOperand(0)));
|
2005-08-18 03:04:18 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ISD::CTLZ:
|
|
|
|
assert(N->getValueType(0) == MVT::i32);
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::CNTLZW, MVT::i32, Select(N->getOperand(0)));
|
2005-08-18 03:04:18 +00:00
|
|
|
break;
|
2005-08-26 20:25:03 +00:00
|
|
|
case PPCISD::FSEL:
|
|
|
|
CurDAG->SelectNodeTo(N, PPC::FSEL, N->getValueType(0),
|
|
|
|
Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1)),
|
|
|
|
Select(N->getOperand(2)));
|
|
|
|
break;
|
2005-08-31 21:09:52 +00:00
|
|
|
case PPCISD::FCTIWZ:
|
|
|
|
CurDAG->SelectNodeTo(N, PPC::FCTIWZ, N->getValueType(0),
|
|
|
|
Select(N->getOperand(0)));
|
|
|
|
break;
|
2005-08-17 19:33:03 +00:00
|
|
|
case ISD::ADD: {
|
|
|
|
MVT::ValueType Ty = N->getValueType(0);
|
|
|
|
if (Ty == MVT::i32) {
|
|
|
|
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
|
|
|
|
PPC::ADDIS, PPC::ADDI, true)) {
|
2005-08-26 18:37:23 +00:00
|
|
|
CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
|
2005-08-17 19:33:03 +00:00
|
|
|
N = I;
|
|
|
|
} else {
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::ADD, MVT::i32, Select(N->getOperand(0)),
|
2005-08-17 19:33:03 +00:00
|
|
|
Select(N->getOperand(1)));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!NoExcessFPPrecision) { // Match FMA ops
|
|
|
|
if (N->getOperand(0).getOpcode() == ISD::MUL &&
|
|
|
|
N->getOperand(0).Val->hasOneUse()) {
|
|
|
|
++FusedFP; // Statistic
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
|
2005-08-17 19:33:03 +00:00
|
|
|
Select(N->getOperand(0).getOperand(0)),
|
|
|
|
Select(N->getOperand(0).getOperand(1)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
} else if (N->getOperand(1).getOpcode() == ISD::MUL &&
|
|
|
|
N->getOperand(1).hasOneUse()) {
|
|
|
|
++FusedFP; // Statistic
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
|
2005-08-17 19:33:03 +00:00
|
|
|
Select(N->getOperand(1).getOperand(0)),
|
|
|
|
Select(N->getOperand(1).getOperand(1)),
|
|
|
|
Select(N->getOperand(0)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS, Ty,
|
2005-08-17 19:33:03 +00:00
|
|
|
Select(N->getOperand(0)), Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::SUB: {
|
|
|
|
MVT::ValueType Ty = N->getValueType(0);
|
|
|
|
if (Ty == MVT::i32) {
|
|
|
|
unsigned Imm;
|
|
|
|
if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
|
2005-08-24 05:03:20 +00:00
|
|
|
if (0 == Imm)
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::NEG, Ty, Select(N->getOperand(1)));
|
2005-08-24 05:03:20 +00:00
|
|
|
else
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::SUBFIC, Ty, Select(N->getOperand(1)),
|
2005-08-24 05:03:20 +00:00
|
|
|
getI32Imm(Lo16(Imm)));
|
2005-08-17 19:33:03 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
|
|
|
|
PPC::ADDIS, PPC::ADDI, true, true)) {
|
2005-08-26 18:37:23 +00:00
|
|
|
CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
|
2005-08-17 19:33:03 +00:00
|
|
|
N = I;
|
|
|
|
} else {
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::SUBF, Ty, Select(N->getOperand(1)),
|
2005-08-17 19:33:03 +00:00
|
|
|
Select(N->getOperand(0)));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!NoExcessFPPrecision) { // Match FMA ops
|
|
|
|
if (N->getOperand(0).getOpcode() == ISD::MUL &&
|
|
|
|
N->getOperand(0).Val->hasOneUse()) {
|
|
|
|
++FusedFP; // Statistic
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS, Ty,
|
2005-08-17 19:33:03 +00:00
|
|
|
Select(N->getOperand(0).getOperand(0)),
|
|
|
|
Select(N->getOperand(0).getOperand(1)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
} else if (N->getOperand(1).getOpcode() == ISD::MUL &&
|
|
|
|
N->getOperand(1).Val->hasOneUse()) {
|
|
|
|
++FusedFP; // Statistic
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS, Ty,
|
2005-08-17 19:33:03 +00:00
|
|
|
Select(N->getOperand(1).getOperand(0)),
|
|
|
|
Select(N->getOperand(1).getOperand(1)),
|
|
|
|
Select(N->getOperand(0)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS, Ty,
|
2005-08-17 19:33:03 +00:00
|
|
|
Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
2005-08-17 23:46:35 +00:00
|
|
|
}
|
2005-08-18 00:21:41 +00:00
|
|
|
case ISD::MUL: {
|
|
|
|
unsigned Imm, Opc;
|
|
|
|
if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::MULLI, MVT::i32,
|
2005-08-18 00:21:41 +00:00
|
|
|
Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
switch (N->getValueType(0)) {
|
|
|
|
default: assert(0 && "Unhandled multiply type!");
|
|
|
|
case MVT::i32: Opc = PPC::MULLW; break;
|
|
|
|
case MVT::f32: Opc = PPC::FMULS; break;
|
|
|
|
case MVT::f64: Opc = PPC::FMUL; break;
|
|
|
|
}
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
|
2005-08-18 00:21:41 +00:00
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
}
|
2005-08-25 17:50:06 +00:00
|
|
|
case ISD::SDIV: {
|
|
|
|
unsigned Imm;
|
|
|
|
if (isIntImmediate(N->getOperand(1), Imm)) {
|
|
|
|
if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
|
|
|
|
SDOperand Op =
|
|
|
|
CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
|
|
|
|
Select(N->getOperand(0)),
|
|
|
|
getI32Imm(Log2_32(Imm)));
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
|
2005-08-25 17:50:06 +00:00
|
|
|
Op.getValue(0), Op.getValue(1));
|
|
|
|
break;
|
|
|
|
} else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
|
|
|
|
SDOperand Op =
|
2005-08-30 17:13:58 +00:00
|
|
|
CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
|
2005-08-25 17:50:06 +00:00
|
|
|
Select(N->getOperand(0)),
|
|
|
|
getI32Imm(Log2_32(-Imm)));
|
|
|
|
SDOperand PT =
|
2005-08-30 17:13:58 +00:00
|
|
|
CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(0),
|
|
|
|
Op.getValue(1));
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
|
2005-08-25 17:50:06 +00:00
|
|
|
break;
|
2005-08-25 22:04:30 +00:00
|
|
|
} else if (Imm) {
|
|
|
|
SDOperand Result = Select(BuildSDIVSequence(N));
|
|
|
|
assert(Result.ResNo == 0);
|
2005-08-26 18:37:23 +00:00
|
|
|
CurDAG->ReplaceAllUsesWith(Op, Result);
|
2005-08-25 22:04:30 +00:00
|
|
|
N = Result.Val;
|
|
|
|
break;
|
2005-08-25 17:50:06 +00:00
|
|
|
}
|
|
|
|
}
|
2005-08-25 22:04:30 +00:00
|
|
|
|
|
|
|
unsigned Opc;
|
|
|
|
switch (N->getValueType(0)) {
|
2005-08-26 16:38:51 +00:00
|
|
|
default: assert(0 && "Unknown type to ISD::SDIV");
|
2005-08-25 22:04:30 +00:00
|
|
|
case MVT::i32: Opc = PPC::DIVW; break;
|
|
|
|
case MVT::f32: Opc = PPC::FDIVS; break;
|
|
|
|
case MVT::f64: Opc = PPC::FDIV; break;
|
|
|
|
}
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
|
2005-08-25 22:04:30 +00:00
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::UDIV: {
|
|
|
|
// If this is a divide by constant, we can emit code using some magic
|
|
|
|
// constants to implement it as a multiply instead.
|
|
|
|
unsigned Imm;
|
2005-08-25 23:21:06 +00:00
|
|
|
if (isIntImmediate(N->getOperand(1), Imm) && Imm) {
|
2005-08-25 22:04:30 +00:00
|
|
|
SDOperand Result = Select(BuildUDIVSequence(N));
|
|
|
|
assert(Result.ResNo == 0);
|
2005-08-26 18:37:23 +00:00
|
|
|
CurDAG->ReplaceAllUsesWith(Op, Result);
|
2005-08-25 22:04:30 +00:00
|
|
|
N = Result.Val;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::DIVWU, MVT::i32, Select(N->getOperand(0)),
|
2005-08-25 22:04:30 +00:00
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
}
|
2005-08-18 03:04:18 +00:00
|
|
|
case ISD::MULHS:
|
2005-08-18 00:21:41 +00:00
|
|
|
assert(N->getValueType(0) == MVT::i32);
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::MULHW, MVT::i32, Select(N->getOperand(0)),
|
2005-08-18 03:04:18 +00:00
|
|
|
Select(N->getOperand(1)));
|
2005-08-18 00:21:41 +00:00
|
|
|
break;
|
2005-08-18 03:04:18 +00:00
|
|
|
case ISD::MULHU:
|
2005-08-18 00:21:41 +00:00
|
|
|
assert(N->getValueType(0) == MVT::i32);
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::MULHWU, MVT::i32, Select(N->getOperand(0)),
|
2005-08-18 03:04:18 +00:00
|
|
|
Select(N->getOperand(1)));
|
2005-08-18 00:21:41 +00:00
|
|
|
break;
|
2005-08-18 07:30:46 +00:00
|
|
|
case ISD::AND: {
|
2005-08-18 18:01:39 +00:00
|
|
|
unsigned Imm;
|
2005-08-18 07:30:46 +00:00
|
|
|
// If this is an and of a value rotated between 0 and 31 bits and then and'd
|
|
|
|
// with a mask, emit rlwinm
|
|
|
|
if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
|
|
|
|
isShiftedMask_32(~Imm))) {
|
|
|
|
SDOperand Val;
|
2005-08-18 18:01:39 +00:00
|
|
|
unsigned SH, MB, ME;
|
2005-08-18 07:30:46 +00:00
|
|
|
if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
|
|
|
|
Val = Select(N->getOperand(0).getOperand(0));
|
|
|
|
} else {
|
|
|
|
Val = Select(N->getOperand(0));
|
|
|
|
isRunOfOnes(Imm, MB, ME);
|
|
|
|
SH = 0;
|
|
|
|
}
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, getI32Imm(SH),
|
2005-08-18 07:30:46 +00:00
|
|
|
getI32Imm(MB), getI32Imm(ME));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// Finally, check for the case where we are being asked to select
|
|
|
|
// and (not(a), b) or and (a, not(b)) which can be selected as andc.
|
|
|
|
if (isOprNot(N->getOperand(0).Val))
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::ANDC, MVT::i32, Select(N->getOperand(1)),
|
2005-08-18 07:30:46 +00:00
|
|
|
Select(N->getOperand(0).getOperand(0)));
|
|
|
|
else if (isOprNot(N->getOperand(1).Val))
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::ANDC, MVT::i32, Select(N->getOperand(0)),
|
2005-08-18 07:30:46 +00:00
|
|
|
Select(N->getOperand(1).getOperand(0)));
|
|
|
|
else
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::AND, MVT::i32, Select(N->getOperand(0)),
|
2005-08-18 07:30:46 +00:00
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
}
|
2005-08-19 00:38:14 +00:00
|
|
|
case ISD::OR:
|
|
|
|
if (SDNode *I = SelectBitfieldInsert(N)) {
|
2005-08-26 18:37:23 +00:00
|
|
|
CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
|
2005-08-19 00:38:14 +00:00
|
|
|
N = I;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
|
|
|
|
N->getOperand(1),
|
|
|
|
PPC::ORIS, PPC::ORI)) {
|
2005-08-26 18:37:23 +00:00
|
|
|
CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
|
2005-08-19 00:38:14 +00:00
|
|
|
N = I;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// Finally, check for the case where we are being asked to select
|
|
|
|
// 'or (not(a), b)' or 'or (a, not(b))' which can be selected as orc.
|
|
|
|
if (isOprNot(N->getOperand(0).Val))
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::ORC, MVT::i32, Select(N->getOperand(1)),
|
2005-08-19 00:38:14 +00:00
|
|
|
Select(N->getOperand(0).getOperand(0)));
|
|
|
|
else if (isOprNot(N->getOperand(1).Val))
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::ORC, MVT::i32, Select(N->getOperand(0)),
|
2005-08-19 00:38:14 +00:00
|
|
|
Select(N->getOperand(1).getOperand(0)));
|
|
|
|
else
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Select(N->getOperand(0)),
|
2005-08-19 00:38:14 +00:00
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
2005-08-18 05:00:13 +00:00
|
|
|
case ISD::XOR:
|
|
|
|
// Check whether or not this node is a logical 'not'. This is represented
|
|
|
|
// by llvm as a xor with the constant value -1 (all bits set). If this is a
|
|
|
|
// 'not', then fold 'or' into 'nor', and so forth for the supported ops.
|
|
|
|
if (isOprNot(N)) {
|
|
|
|
unsigned Opc;
|
2005-08-18 05:44:50 +00:00
|
|
|
SDOperand Val = Select(N->getOperand(0));
|
2005-08-28 23:39:22 +00:00
|
|
|
switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) {
|
2005-08-18 05:00:13 +00:00
|
|
|
default: Opc = 0; break;
|
2005-08-18 05:44:50 +00:00
|
|
|
case PPC::OR: Opc = PPC::NOR; break;
|
|
|
|
case PPC::AND: Opc = PPC::NAND; break;
|
|
|
|
case PPC::XOR: Opc = PPC::EQV; break;
|
2005-08-18 05:00:13 +00:00
|
|
|
}
|
|
|
|
if (Opc)
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Opc, MVT::i32, Val.getOperand(0),
|
2005-08-18 05:44:50 +00:00
|
|
|
Val.getOperand(1));
|
2005-08-18 05:00:13 +00:00
|
|
|
else
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::NOR, MVT::i32, Val, Val);
|
2005-08-18 05:00:13 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
// If this is a xor with an immediate other than -1, then codegen it as high
|
|
|
|
// and low 16 bit immediate xors.
|
|
|
|
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
|
|
|
|
N->getOperand(1),
|
|
|
|
PPC::XORIS, PPC::XORI)) {
|
2005-08-26 18:37:23 +00:00
|
|
|
CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
|
2005-08-18 05:00:13 +00:00
|
|
|
N = I;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// Finally, check for the case where we are being asked to select
|
|
|
|
// xor (not(a), b) which is equivalent to not(xor a, b), which is eqv
|
|
|
|
if (isOprNot(N->getOperand(0).Val))
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::EQV, MVT::i32,
|
2005-08-18 05:00:13 +00:00
|
|
|
Select(N->getOperand(0).getOperand(0)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
else
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::XOR, MVT::i32, Select(N->getOperand(0)),
|
2005-08-18 05:00:13 +00:00
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
2005-08-18 23:38:00 +00:00
|
|
|
case ISD::SHL: {
|
|
|
|
unsigned Imm, SH, MB, ME;
|
|
|
|
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
|
|
|
|
isRotateAndMask(N, Imm, true, SH, MB, ME))
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
|
2005-08-18 23:38:00 +00:00
|
|
|
Select(N->getOperand(0).getOperand(0)),
|
|
|
|
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
|
|
|
|
else if (isIntImmediate(N->getOperand(1), Imm))
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)),
|
2005-08-18 23:38:00 +00:00
|
|
|
getI32Imm(Imm), getI32Imm(0), getI32Imm(31-Imm));
|
|
|
|
else
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::SLW, MVT::i32, Select(N->getOperand(0)),
|
2005-08-18 23:38:00 +00:00
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::SRL: {
|
|
|
|
unsigned Imm, SH, MB, ME;
|
|
|
|
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
|
|
|
|
isRotateAndMask(N, Imm, true, SH, MB, ME))
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
|
2005-08-18 23:38:00 +00:00
|
|
|
Select(N->getOperand(0).getOperand(0)),
|
|
|
|
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
|
|
|
|
else if (isIntImmediate(N->getOperand(1), Imm))
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)),
|
2005-08-18 23:38:00 +00:00
|
|
|
getI32Imm(32-Imm), getI32Imm(Imm), getI32Imm(31));
|
|
|
|
else
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::SRW, MVT::i32, Select(N->getOperand(0)),
|
2005-08-18 23:38:00 +00:00
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::SRA: {
|
|
|
|
unsigned Imm, SH, MB, ME;
|
|
|
|
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
|
|
|
|
isRotateAndMask(N, Imm, true, SH, MB, ME))
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
|
2005-08-18 23:38:00 +00:00
|
|
|
Select(N->getOperand(0).getOperand(0)),
|
|
|
|
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
|
|
|
|
else if (isIntImmediate(N->getOperand(1), Imm))
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::SRAWI, MVT::i32, Select(N->getOperand(0)),
|
2005-08-18 23:38:00 +00:00
|
|
|
getI32Imm(Imm));
|
|
|
|
else
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::SRAW, MVT::i32, Select(N->getOperand(0)),
|
2005-08-18 23:38:00 +00:00
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
}
|
2005-08-18 03:04:18 +00:00
|
|
|
case ISD::FABS:
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::FABS, N->getValueType(0),
|
2005-08-18 00:53:47 +00:00
|
|
|
Select(N->getOperand(0)));
|
|
|
|
break;
|
2005-08-30 00:30:43 +00:00
|
|
|
case ISD::FP_EXTEND:
|
2005-08-18 03:04:18 +00:00
|
|
|
assert(MVT::f64 == N->getValueType(0) &&
|
|
|
|
MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND");
|
2005-08-30 00:30:43 +00:00
|
|
|
// We need to emit an FMR to make sure that the result has the right value
|
|
|
|
// type.
|
|
|
|
CurDAG->SelectNodeTo(N, PPC::FMR, MVT::f64, Select(N->getOperand(0)));
|
|
|
|
break;
|
2005-08-18 03:04:18 +00:00
|
|
|
case ISD::FP_ROUND:
|
|
|
|
assert(MVT::f32 == N->getValueType(0) &&
|
|
|
|
MVT::f64 == N->getOperand(0).getValueType() && "Illegal FP_ROUND");
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::FRSP, MVT::f32, Select(N->getOperand(0)));
|
2005-08-18 03:04:18 +00:00
|
|
|
break;
|
2005-08-17 23:46:35 +00:00
|
|
|
case ISD::FNEG: {
|
|
|
|
SDOperand Val = Select(N->getOperand(0));
|
|
|
|
MVT::ValueType Ty = N->getValueType(0);
|
|
|
|
if (Val.Val->hasOneUse()) {
|
|
|
|
unsigned Opc;
|
2005-08-28 23:39:22 +00:00
|
|
|
switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) {
|
2005-08-17 23:46:35 +00:00
|
|
|
default: Opc = 0; break;
|
|
|
|
case PPC::FABS: Opc = PPC::FNABS; break;
|
|
|
|
case PPC::FMADD: Opc = PPC::FNMADD; break;
|
|
|
|
case PPC::FMADDS: Opc = PPC::FNMADDS; break;
|
|
|
|
case PPC::FMSUB: Opc = PPC::FNMSUB; break;
|
|
|
|
case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
|
|
|
|
}
|
|
|
|
// If we inverted the opcode, then emit the new instruction with the
|
|
|
|
// inverted opcode and the original instruction's operands. Otherwise,
|
|
|
|
// fall through and generate a fneg instruction.
|
|
|
|
if (Opc) {
|
|
|
|
if (PPC::FNABS == Opc)
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0));
|
2005-08-17 23:46:35 +00:00
|
|
|
else
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0),
|
2005-08-17 23:46:35 +00:00
|
|
|
Val.getOperand(1), Val.getOperand(2));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::FNEG, Ty, Val);
|
2005-08-17 23:46:35 +00:00
|
|
|
break;
|
|
|
|
}
|
2005-08-18 00:53:47 +00:00
|
|
|
case ISD::FSQRT: {
|
|
|
|
MVT::ValueType Ty = N->getValueType(0);
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS, Ty,
|
2005-08-18 00:53:47 +00:00
|
|
|
Select(N->getOperand(0)));
|
|
|
|
break;
|
|
|
|
}
|
2005-08-25 23:21:06 +00:00
|
|
|
|
|
|
|
case ISD::ADD_PARTS: {
|
|
|
|
SDOperand LHSL = Select(N->getOperand(0));
|
|
|
|
SDOperand LHSH = Select(N->getOperand(1));
|
|
|
|
|
|
|
|
unsigned Imm;
|
2005-08-26 16:38:51 +00:00
|
|
|
bool ME = false, ZE = false;
|
2005-08-25 23:21:06 +00:00
|
|
|
if (isIntImmediate(N->getOperand(3), Imm)) {
|
|
|
|
ME = (signed)Imm == -1;
|
|
|
|
ZE = Imm == 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
std::vector<SDOperand> Result;
|
|
|
|
SDOperand CarryFromLo;
|
|
|
|
if (isIntImmediate(N->getOperand(2), Imm) &&
|
|
|
|
((signed)Imm >= -32768 || (signed)Imm < 32768)) {
|
|
|
|
// Codegen the low 32 bits of the add. Interestingly, there is no
|
|
|
|
// shifted form of add immediate carrying.
|
|
|
|
CarryFromLo = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
|
|
|
|
LHSL, getI32Imm(Imm));
|
|
|
|
} else {
|
|
|
|
CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
|
|
|
|
LHSL, Select(N->getOperand(2)));
|
|
|
|
}
|
|
|
|
CarryFromLo = CarryFromLo.getValue(1);
|
|
|
|
|
|
|
|
// Codegen the high 32 bits, adding zero, minus one, or the full value
|
|
|
|
// along with the carry flag produced by addc/addic.
|
|
|
|
SDOperand ResultHi;
|
|
|
|
if (ZE)
|
|
|
|
ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo);
|
|
|
|
else if (ME)
|
|
|
|
ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo);
|
|
|
|
else
|
|
|
|
ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH,
|
|
|
|
Select(N->getOperand(3)), CarryFromLo);
|
2005-08-25 23:36:49 +00:00
|
|
|
Result.push_back(CarryFromLo.getValue(0));
|
2005-08-30 17:40:13 +00:00
|
|
|
Result.push_back(ResultHi);
|
2005-08-25 23:21:06 +00:00
|
|
|
CurDAG->ReplaceAllUsesWith(N, Result);
|
|
|
|
return Result[Op.ResNo];
|
|
|
|
}
|
|
|
|
case ISD::SUB_PARTS: {
|
|
|
|
SDOperand LHSL = Select(N->getOperand(0));
|
|
|
|
SDOperand LHSH = Select(N->getOperand(1));
|
|
|
|
SDOperand RHSL = Select(N->getOperand(2));
|
|
|
|
SDOperand RHSH = Select(N->getOperand(3));
|
|
|
|
|
|
|
|
std::vector<SDOperand> Result;
|
|
|
|
Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag,
|
|
|
|
RHSL, LHSL));
|
|
|
|
Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH,
|
|
|
|
Result[0].getValue(1)));
|
|
|
|
CurDAG->ReplaceAllUsesWith(N, Result);
|
|
|
|
return Result[Op.ResNo];
|
|
|
|
}
|
|
|
|
|
2005-08-21 22:31:09 +00:00
|
|
|
case ISD::LOAD:
|
|
|
|
case ISD::EXTLOAD:
|
|
|
|
case ISD::ZEXTLOAD:
|
|
|
|
case ISD::SEXTLOAD: {
|
|
|
|
SDOperand Op1, Op2;
|
|
|
|
bool isIdx = SelectAddr(N->getOperand(1), Op1, Op2);
|
|
|
|
|
|
|
|
MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
|
|
|
|
N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
|
|
|
|
unsigned Opc;
|
|
|
|
switch (TypeBeingLoaded) {
|
|
|
|
default: N->dump(); assert(0 && "Cannot load this type!");
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8: Opc = isIdx ? PPC::LBZX : PPC::LBZ; break;
|
|
|
|
case MVT::i16:
|
|
|
|
if (N->getOpcode() == ISD::SEXTLOAD) { // SEXT load?
|
|
|
|
Opc = isIdx ? PPC::LHAX : PPC::LHA;
|
|
|
|
} else {
|
|
|
|
Opc = isIdx ? PPC::LHZX : PPC::LHZ;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MVT::i32: Opc = isIdx ? PPC::LWZX : PPC::LWZ; break;
|
|
|
|
case MVT::f32: Opc = isIdx ? PPC::LFSX : PPC::LFS; break;
|
|
|
|
case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break;
|
|
|
|
}
|
|
|
|
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
|
2005-08-21 22:31:09 +00:00
|
|
|
Op1, Op2, Select(N->getOperand(0)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2005-08-22 01:27:59 +00:00
|
|
|
case ISD::TRUNCSTORE:
|
|
|
|
case ISD::STORE: {
|
|
|
|
SDOperand AddrOp1, AddrOp2;
|
|
|
|
bool isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2);
|
|
|
|
|
|
|
|
unsigned Opc;
|
|
|
|
if (N->getOpcode() == ISD::STORE) {
|
|
|
|
switch (N->getOperand(1).getValueType()) {
|
|
|
|
default: assert(0 && "unknown Type in store");
|
|
|
|
case MVT::i32: Opc = isIdx ? PPC::STWX : PPC::STW; break;
|
|
|
|
case MVT::f64: Opc = isIdx ? PPC::STFDX : PPC::STFD; break;
|
|
|
|
case MVT::f32: Opc = isIdx ? PPC::STFSX : PPC::STFS; break;
|
|
|
|
}
|
|
|
|
} else { //ISD::TRUNCSTORE
|
|
|
|
switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
|
|
|
|
default: assert(0 && "unknown Type in store");
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8: Opc = isIdx ? PPC::STBX : PPC::STB; break;
|
|
|
|
case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break;
|
|
|
|
}
|
|
|
|
}
|
2005-08-24 22:45:17 +00:00
|
|
|
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(1)),
|
2005-08-22 01:27:59 +00:00
|
|
|
AddrOp1, AddrOp2, Select(N->getOperand(0)));
|
|
|
|
break;
|
2005-08-24 00:47:15 +00:00
|
|
|
}
|
2005-08-25 20:08:18 +00:00
|
|
|
|
|
|
|
case ISD::SETCC: {
|
|
|
|
unsigned Imm;
|
|
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
|
|
|
|
if (isIntImmediate(N->getOperand(1), Imm)) {
|
|
|
|
// We can codegen setcc op, imm very efficiently compared to a brcond.
|
|
|
|
// Check for those cases here.
|
|
|
|
// setcc op, 0
|
|
|
|
if (Imm == 0) {
|
|
|
|
SDOperand Op = Select(N->getOperand(0));
|
|
|
|
switch (CC) {
|
|
|
|
default: assert(0 && "Unhandled SetCC condition"); abort();
|
|
|
|
case ISD::SETEQ:
|
|
|
|
Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
|
2005-08-25 20:08:18 +00:00
|
|
|
getI32Imm(5), getI32Imm(31));
|
|
|
|
break;
|
|
|
|
case ISD::SETNE: {
|
|
|
|
SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
|
|
|
|
Op, getI32Imm(~0U));
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
|
2005-08-25 20:08:18 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::SETLT:
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
|
2005-08-25 20:08:18 +00:00
|
|
|
getI32Imm(31), getI32Imm(31));
|
|
|
|
break;
|
|
|
|
case ISD::SETGT: {
|
|
|
|
SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
|
|
|
|
T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
|
2005-08-25 20:08:18 +00:00
|
|
|
getI32Imm(31), getI32Imm(31));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
} else if (Imm == ~0U) { // setcc op, -1
|
|
|
|
SDOperand Op = Select(N->getOperand(0));
|
|
|
|
switch (CC) {
|
|
|
|
default: assert(0 && "Unhandled SetCC condition"); abort();
|
|
|
|
case ISD::SETEQ:
|
|
|
|
Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
|
|
|
|
Op, getI32Imm(1));
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
|
2005-08-25 20:08:18 +00:00
|
|
|
CurDAG->getTargetNode(PPC::LI, MVT::i32,
|
|
|
|
getI32Imm(0)),
|
|
|
|
Op.getValue(1));
|
|
|
|
break;
|
|
|
|
case ISD::SETNE: {
|
|
|
|
Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
|
2005-08-29 23:49:25 +00:00
|
|
|
SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
|
|
|
|
Op, getI32Imm(~0U));
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
|
2005-08-25 20:08:18 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::SETLT: {
|
|
|
|
SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
|
|
|
|
getI32Imm(1));
|
|
|
|
SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
|
2005-08-25 20:08:18 +00:00
|
|
|
getI32Imm(31), getI32Imm(31));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::SETGT:
|
|
|
|
Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
|
|
|
|
getI32Imm(31), getI32Imm(31));
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
|
2005-08-25 20:08:18 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
bool Inv;
|
|
|
|
unsigned Idx = getCRIdxForSetCC(CC, Inv);
|
2005-09-01 19:20:44 +00:00
|
|
|
SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
|
2005-08-25 20:08:18 +00:00
|
|
|
SDOperand IntCR;
|
2005-08-25 21:39:42 +00:00
|
|
|
|
|
|
|
// Force the ccreg into CR7.
|
|
|
|
SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
|
|
|
|
|
|
|
|
std::vector<MVT::ValueType> VTs;
|
|
|
|
VTs.push_back(MVT::Other);
|
|
|
|
VTs.push_back(MVT::Flag); // NONSTANDARD CopyToReg node: defines a flag
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(CurDAG->getEntryNode());
|
|
|
|
Ops.push_back(CR7Reg);
|
|
|
|
Ops.push_back(CCReg);
|
|
|
|
CCReg = CurDAG->getNode(ISD::CopyToReg, VTs, Ops).getValue(1);
|
|
|
|
|
|
|
|
if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
|
|
|
|
IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
|
|
|
|
else
|
|
|
|
IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
|
2005-08-25 20:08:18 +00:00
|
|
|
|
|
|
|
if (!Inv) {
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
|
2005-08-25 20:08:18 +00:00
|
|
|
getI32Imm(32-(3-Idx)), getI32Imm(31), getI32Imm(31));
|
|
|
|
} else {
|
|
|
|
SDOperand Tmp =
|
|
|
|
CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
|
|
|
|
getI32Imm(32-(3-Idx)), getI32Imm(31),getI32Imm(31));
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
|
2005-08-25 20:08:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
2005-08-24 00:47:15 +00:00
|
|
|
|
2005-08-26 18:46:49 +00:00
|
|
|
case ISD::SELECT_CC: {
|
|
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
|
|
|
|
|
|
|
|
// handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
|
|
|
|
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
|
|
|
|
if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
|
|
|
|
if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
|
|
|
|
if (N1C->isNullValue() && N3C->isNullValue() &&
|
|
|
|
N2C->getValue() == 1ULL && CC == ISD::SETNE) {
|
|
|
|
SDOperand LHS = Select(N->getOperand(0));
|
|
|
|
SDOperand Tmp =
|
|
|
|
CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
|
|
|
|
LHS, getI32Imm(~0U));
|
|
|
|
CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, Tmp, LHS,
|
|
|
|
Tmp.getValue(1));
|
|
|
|
break;
|
|
|
|
}
|
2005-08-26 21:23:58 +00:00
|
|
|
|
2005-09-01 19:20:44 +00:00
|
|
|
SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
|
2005-08-26 21:23:58 +00:00
|
|
|
unsigned BROpc = getBCCForSetCC(CC);
|
|
|
|
|
|
|
|
bool isFP = MVT::isFloatingPoint(N->getValueType(0));
|
|
|
|
unsigned SelectCCOp = isFP ? PPC::SELECT_CC_FP : PPC::SELECT_CC_Int;
|
|
|
|
CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
|
|
|
|
Select(N->getOperand(2)), Select(N->getOperand(3)),
|
|
|
|
getI32Imm(BROpc));
|
|
|
|
break;
|
2005-08-26 18:46:49 +00:00
|
|
|
}
|
|
|
|
|
2005-08-24 00:47:15 +00:00
|
|
|
case ISD::CALLSEQ_START:
|
|
|
|
case ISD::CALLSEQ_END: {
|
|
|
|
unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
|
|
|
|
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
|
|
|
|
PPC::ADJCALLSTACKDOWN : PPC::ADJCALLSTACKUP;
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, Opc, MVT::Other,
|
2005-08-24 22:45:17 +00:00
|
|
|
getI32Imm(Amt), Select(N->getOperand(0)));
|
2005-08-24 00:47:15 +00:00
|
|
|
break;
|
2005-08-22 01:27:59 +00:00
|
|
|
}
|
2005-08-24 22:45:17 +00:00
|
|
|
case ISD::CALL:
|
|
|
|
case ISD::TAILCALL: {
|
|
|
|
SDOperand Chain = Select(N->getOperand(0));
|
|
|
|
|
|
|
|
unsigned CallOpcode;
|
|
|
|
std::vector<SDOperand> CallOperands;
|
|
|
|
|
|
|
|
if (GlobalAddressSDNode *GASD =
|
|
|
|
dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
|
|
|
|
CallOpcode = PPC::CALLpcrel;
|
|
|
|
CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
|
|
|
|
MVT::i32));
|
|
|
|
} else if (ExternalSymbolSDNode *ESSDN =
|
|
|
|
dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
|
|
|
|
CallOpcode = PPC::CALLpcrel;
|
|
|
|
CallOperands.push_back(N->getOperand(1));
|
|
|
|
} else {
|
|
|
|
// Copy the callee address into the CTR register.
|
|
|
|
SDOperand Callee = Select(N->getOperand(1));
|
|
|
|
Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain);
|
|
|
|
|
|
|
|
// Copy the callee address into R12 on darwin.
|
|
|
|
SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
|
2005-08-29 00:26:57 +00:00
|
|
|
Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee);
|
2005-08-24 22:45:17 +00:00
|
|
|
|
|
|
|
CallOperands.push_back(getI32Imm(20)); // Information to encode indcall
|
|
|
|
CallOperands.push_back(getI32Imm(0)); // Information to encode indcall
|
|
|
|
CallOperands.push_back(R12);
|
|
|
|
CallOpcode = PPC::CALLindirect;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned GPR_idx = 0, FPR_idx = 0;
|
|
|
|
static const unsigned GPR[] = {
|
|
|
|
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
|
|
|
|
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
|
|
|
|
};
|
|
|
|
static const unsigned FPR[] = {
|
|
|
|
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
|
|
|
|
PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
|
|
|
|
};
|
|
|
|
|
2005-08-30 01:57:02 +00:00
|
|
|
SDOperand InFlag; // Null incoming flag value.
|
|
|
|
|
2005-08-29 22:22:57 +00:00
|
|
|
for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
|
|
|
|
unsigned DestReg = 0;
|
2005-08-30 22:59:48 +00:00
|
|
|
MVT::ValueType RegTy = N->getOperand(i).getValueType();
|
|
|
|
if (RegTy == MVT::i32) {
|
2005-08-29 22:22:57 +00:00
|
|
|
assert(GPR_idx < 8 && "Too many int args");
|
|
|
|
DestReg = GPR[GPR_idx++];
|
|
|
|
} else {
|
|
|
|
assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
|
|
|
|
"Unpromoted integer arg?");
|
|
|
|
assert(FPR_idx < 13 && "Too many fp args");
|
|
|
|
DestReg = FPR[FPR_idx++];
|
|
|
|
}
|
|
|
|
|
2005-08-24 22:45:17 +00:00
|
|
|
if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
|
2005-08-30 21:28:19 +00:00
|
|
|
SDOperand Val = Select(N->getOperand(i));
|
|
|
|
Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
|
2005-08-30 01:57:02 +00:00
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
|
2005-08-24 22:45:17 +00:00
|
|
|
}
|
2005-08-29 22:22:57 +00:00
|
|
|
}
|
2005-08-24 22:45:17 +00:00
|
|
|
|
|
|
|
// Finally, once everything is in registers to pass to the call, emit the
|
|
|
|
// call itself.
|
2005-08-30 01:57:02 +00:00
|
|
|
if (InFlag.Val)
|
|
|
|
CallOperands.push_back(InFlag); // Strong dep on register copies.
|
|
|
|
else
|
|
|
|
CallOperands.push_back(Chain); // Weak dep on whatever occurs before
|
|
|
|
Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
|
|
|
|
CallOperands);
|
2005-08-24 22:45:17 +00:00
|
|
|
|
|
|
|
std::vector<SDOperand> CallResults;
|
|
|
|
|
|
|
|
// If the call has results, copy the values out of the ret val registers.
|
|
|
|
switch (N->getValueType(0)) {
|
|
|
|
default: assert(0 && "Unexpected ret value!");
|
|
|
|
case MVT::Other: break;
|
|
|
|
case MVT::i32:
|
|
|
|
if (N->getValueType(1) == MVT::i32) {
|
2005-08-30 01:57:02 +00:00
|
|
|
Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32,
|
|
|
|
Chain.getValue(1)).getValue(1);
|
2005-08-24 22:45:17 +00:00
|
|
|
CallResults.push_back(Chain.getValue(0));
|
2005-08-30 01:57:02 +00:00
|
|
|
Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
|
|
|
|
Chain.getValue(1)).getValue(1);
|
2005-08-24 22:45:17 +00:00
|
|
|
CallResults.push_back(Chain.getValue(0));
|
|
|
|
} else {
|
2005-08-30 01:57:02 +00:00
|
|
|
Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
|
|
|
|
Chain.getValue(1)).getValue(1);
|
2005-08-24 22:45:17 +00:00
|
|
|
CallResults.push_back(Chain.getValue(0));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MVT::f32:
|
|
|
|
case MVT::f64:
|
2005-08-30 22:59:48 +00:00
|
|
|
Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0),
|
2005-08-30 01:57:02 +00:00
|
|
|
Chain.getValue(1)).getValue(1);
|
2005-08-30 22:59:48 +00:00
|
|
|
CallResults.push_back(Chain.getValue(0));
|
2005-08-24 22:45:17 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
CallResults.push_back(Chain);
|
|
|
|
CurDAG->ReplaceAllUsesWith(N, CallResults);
|
|
|
|
return CallResults[Op.ResNo];
|
|
|
|
}
|
2005-08-17 19:33:03 +00:00
|
|
|
case ISD::RET: {
|
|
|
|
SDOperand Chain = Select(N->getOperand(0)); // Token chain.
|
|
|
|
|
2005-08-31 01:34:29 +00:00
|
|
|
if (N->getNumOperands() == 2) {
|
2005-08-17 19:33:03 +00:00
|
|
|
SDOperand Val = Select(N->getOperand(1));
|
2005-08-30 22:59:48 +00:00
|
|
|
if (N->getOperand(1).getValueType() == MVT::i32) {
|
2005-08-17 19:33:03 +00:00
|
|
|
Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
|
2005-08-30 22:59:48 +00:00
|
|
|
} else {
|
|
|
|
assert(MVT::isFloatingPoint(N->getOperand(1).getValueType()));
|
|
|
|
Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
|
2005-08-17 19:33:03 +00:00
|
|
|
}
|
2005-08-31 01:34:29 +00:00
|
|
|
} else if (N->getNumOperands() > 1) {
|
|
|
|
assert(N->getOperand(1).getValueType() == MVT::i32 &&
|
|
|
|
N->getOperand(2).getValueType() == MVT::i32 &&
|
|
|
|
N->getNumOperands() == 3 && "Unknown two-register ret value!");
|
|
|
|
Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Select(N->getOperand(1)));
|
|
|
|
Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Select(N->getOperand(2)));
|
2005-08-17 19:33:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Finally, select this to a blr (return) instruction.
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::BLR, MVT::Other, Chain);
|
2005-08-17 19:33:03 +00:00
|
|
|
break;
|
|
|
|
}
|
2005-08-25 00:29:58 +00:00
|
|
|
case ISD::BR:
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(1),
|
2005-08-25 00:29:58 +00:00
|
|
|
Select(N->getOperand(0)));
|
|
|
|
break;
|
2005-08-21 18:50:37 +00:00
|
|
|
case ISD::BR_CC:
|
|
|
|
case ISD::BRTWOWAY_CC: {
|
|
|
|
SDOperand Chain = Select(N->getOperand(0));
|
|
|
|
MachineBasicBlock *Dest =
|
|
|
|
cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock();
|
|
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
|
|
|
|
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
|
|
|
|
unsigned Opc = getBCCForSetCC(CC);
|
|
|
|
|
|
|
|
// If this is a two way branch, then grab the fallthrough basic block
|
|
|
|
// argument and build a PowerPC branch pseudo-op, suitable for long branch
|
|
|
|
// conversion if necessary by the branch selection pass. Otherwise, emit a
|
|
|
|
// standard conditional branch.
|
|
|
|
if (N->getOpcode() == ISD::BRTWOWAY_CC) {
|
|
|
|
MachineBasicBlock *Fallthrough =
|
|
|
|
cast<BasicBlockSDNode>(N->getOperand(5))->getBasicBlock();
|
|
|
|
SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
|
|
|
|
CondCode, getI32Imm(Opc),
|
|
|
|
N->getOperand(4), N->getOperand(5),
|
|
|
|
Chain);
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(5), CB);
|
2005-08-21 18:50:37 +00:00
|
|
|
} else {
|
|
|
|
// Iterate to the next basic block
|
|
|
|
ilist<MachineBasicBlock>::iterator It = BB;
|
|
|
|
++It;
|
|
|
|
|
|
|
|
// If the fallthrough path is off the end of the function, which would be
|
|
|
|
// undefined behavior, set it to be the same as the current block because
|
|
|
|
// we have nothing better to set it to, and leaving it alone will cause
|
|
|
|
// the PowerPC Branch Selection pass to crash.
|
|
|
|
if (It == BB->getParent()->end()) It = Dest;
|
2005-08-26 16:36:26 +00:00
|
|
|
CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode,
|
2005-08-21 18:50:37 +00:00
|
|
|
getI32Imm(Opc), N->getOperand(4),
|
|
|
|
CurDAG->getBasicBlock(It), Chain);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2005-08-17 19:33:03 +00:00
|
|
|
}
|
2005-08-22 00:59:14 +00:00
|
|
|
return SDOperand(N, Op.ResNo);
|
2005-08-17 19:33:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/// createPPC32ISelDag - This pass converts a legalized DAG into a
|
|
|
|
/// PowerPC-specific DAG, ready for instruction scheduling.
|
|
|
|
///
|
|
|
|
FunctionPass *llvm::createPPC32ISelDag(TargetMachine &TM) {
|
|
|
|
return new PPC32DAGToDAGISel(TM);
|
|
|
|
}
|
|
|
|
|