2007-01-19 07:51:42 +00:00
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//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-01-19 07:51:42 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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2011-07-01 21:01:15 +00:00
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// This file declares the ARM specific subclass of TargetSubtargetInfo.
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2007-01-19 07:51:42 +00:00
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMSUBTARGET_H
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#define ARMSUBTARGET_H
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2011-07-07 00:08:19 +00:00
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#include "MCTargetDesc/ARMMCTargetDesc.h"
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2011-07-01 21:01:15 +00:00
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#include "llvm/Target/TargetSubtargetInfo.h"
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2011-06-29 01:14:12 +00:00
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#include "llvm/MC/MCInstrItineraries.h"
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2011-01-11 21:46:47 +00:00
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#include "llvm/ADT/Triple.h"
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2007-01-19 07:51:42 +00:00
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#include <string>
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2011-07-01 20:45:01 +00:00
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#define GET_SUBTARGETINFO_HEADER
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2011-07-01 22:36:09 +00:00
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#include "ARMGenSubtargetInfo.inc"
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2011-07-01 20:45:01 +00:00
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2007-01-19 07:51:42 +00:00
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namespace llvm {
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2009-08-28 23:18:09 +00:00
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class GlobalValue;
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2011-07-07 07:07:08 +00:00
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class StringRef;
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2007-01-19 07:51:42 +00:00
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2011-07-01 20:45:01 +00:00
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class ARMSubtarget : public ARMGenSubtargetInfo {
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2007-01-19 07:51:42 +00:00
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protected:
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2010-09-10 01:29:16 +00:00
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enum ARMProcFamilyEnum {
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Others, CortexA8, CortexA9
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};
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/// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
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ARMProcFamilyEnum ARMProcFamily;
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2011-07-07 03:55:05 +00:00
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/// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
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/// Specify whether target support specific ARM ISA variants.
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bool HasV4TOps;
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bool HasV5TOps;
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bool HasV5TEOps;
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bool HasV6Ops;
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bool HasV6T2Ops;
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bool HasV7Ops;
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2012-01-22 12:07:33 +00:00
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/// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON, HasNEONVFPv4 - Specify what
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/// floating point ISAs are supported.
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2011-07-07 03:55:05 +00:00
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bool HasVFPv2;
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bool HasVFPv3;
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2012-01-22 12:07:33 +00:00
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bool HasVFPv4;
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2011-07-07 03:55:05 +00:00
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bool HasNEON;
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2012-01-22 12:07:33 +00:00
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bool HasNEONVFPv4;
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2007-01-19 07:51:42 +00:00
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2009-08-05 16:01:19 +00:00
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/// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
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/// specified. Use the method useNEONForSinglePrecisionFP() to
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/// determine if NEON should actually be used.
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2009-08-04 17:53:06 +00:00
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bool UseNEONForSinglePrecisionFP;
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2010-12-05 22:04:16 +00:00
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/// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
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/// whether the FP VML[AS] instructions are slow (if so, don't use them).
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bool SlowFPVMLx;
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2010-03-24 22:31:46 +00:00
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2011-03-31 19:38:48 +00:00
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/// HasVMLxForwarding - If true, NEON has special multiplier accumulator
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/// forwarding to allow mul + mla being issued back to back.
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bool HasVMLxForwarding;
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2010-07-13 19:21:50 +00:00
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/// SlowFPBrcc - True if floating point compare + branch is slow.
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bool SlowFPBrcc;
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2011-07-07 19:09:06 +00:00
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/// InThumbMode - True if compiling for Thumb, false for ARM.
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2011-07-07 19:05:12 +00:00
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bool InThumbMode;
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2009-06-01 20:00:48 +00:00
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2011-07-07 00:08:19 +00:00
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/// HasThumb2 - True if Thumb2 instructions are supported.
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bool HasThumb2;
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2007-01-19 07:51:42 +00:00
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2011-09-28 14:21:38 +00:00
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/// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs -
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/// v6m, v7m for example.
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bool IsMClass;
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2010-08-11 07:17:46 +00:00
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/// NoARM - True if subtarget does not support ARM mode execution.
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bool NoARM;
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2009-09-30 00:10:16 +00:00
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/// PostRAScheduler - True if using post-register-allocation scheduler.
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bool PostRAScheduler;
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2007-01-19 07:51:42 +00:00
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/// IsR9Reserved - True if R9 is a not available as general purpose register.
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bool IsR9Reserved;
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2007-02-13 19:52:28 +00:00
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2009-11-24 00:44:37 +00:00
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/// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
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/// imms (including global addresses).
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bool UseMovt;
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2011-10-07 17:17:49 +00:00
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/// SupportsTailCall - True if the OS supports tail call. The dynamic linker
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/// must be able to synthesize call stubs for interworking between ARM and
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/// Thumb.
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bool SupportsTailCall;
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2010-03-14 18:42:38 +00:00
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/// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
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/// only so far)
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bool HasFP16;
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2010-10-12 16:22:47 +00:00
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/// HasD16 - True if subtarget is limited to 16 double precision
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/// FP registers for VFPv3.
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bool HasD16;
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2010-05-05 23:44:43 +00:00
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/// HasHardwareDivide - True if subtarget supports [su]div
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bool HasHardwareDivide;
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/// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
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/// instructions.
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bool HasT2ExtractPack;
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2010-08-11 06:22:01 +00:00
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/// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
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/// instructions.
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bool HasDataBarrier;
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2010-08-09 18:35:19 +00:00
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/// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
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/// over 16-bit ones.
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bool Pref32BitThumb;
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2011-04-19 18:11:49 +00:00
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/// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
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/// that partially update CPSR and add false dependency on the previous
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/// CPSR setting instruction.
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bool AvoidCPSRPartialUpdate;
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2010-11-03 06:34:55 +00:00
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/// HasMPExtension - True if the subtarget supports Multiprocessing
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/// extension (ARMv7 only).
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bool HasMPExtension;
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2010-08-11 15:44:15 +00:00
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/// FPOnlySP - If true, the floating point unit only supports single
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/// precision.
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bool FPOnlySP;
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2010-09-28 04:09:35 +00:00
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/// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
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/// accesses for some types. For details, see
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/// ARMTargetLowering::allowsUnalignedMemoryAccesses().
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bool AllowsUnalignedMem;
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2011-07-01 21:12:19 +00:00
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/// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
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/// and such) instructions in Thumb2 code.
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bool Thumb2DSP;
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2007-01-19 07:51:42 +00:00
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// entry to the function and which must be maintained by every function.
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unsigned stackAlignment;
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2009-05-23 19:50:50 +00:00
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/// CPUString - String name of used CPU.
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std::string CPUString;
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2011-01-11 21:46:47 +00:00
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/// TargetTriple - What processor and OS we're targeting.
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Triple TargetTriple;
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2009-06-19 01:51:50 +00:00
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/// Selected instruction itineraries (one entry per itinerary class.)
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InstrItineraryData InstrItins;
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2009-08-11 15:33:49 +00:00
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2007-01-19 07:51:42 +00:00
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public:
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2007-01-19 19:22:40 +00:00
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enum {
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isELF, isDarwin
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} TargetType;
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2007-02-13 19:52:28 +00:00
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enum {
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ARM_ABI_APCS,
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ARM_ABI_AAPCS // ARM EABI
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} TargetABI;
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2007-01-19 07:51:42 +00:00
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/// This constructor initializes the data members to match that
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2009-08-02 22:11:08 +00:00
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/// of the specified triple.
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2007-01-19 07:51:42 +00:00
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///
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2011-06-30 01:53:36 +00:00
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ARMSubtarget(const std::string &TT, const std::string &CPU,
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2011-07-07 00:08:19 +00:00
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const std::string &FS);
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2007-01-19 07:51:42 +00:00
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Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-12 04:36:06 +00:00
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/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
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/// that still makes it profitable to inline the call.
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2007-10-31 14:39:58 +00:00
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unsigned getMaxInlineSizeThreshold() const {
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2010-03-11 00:20:49 +00:00
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// FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
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// Change this once Thumb1 ldmia / stmia support is added.
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return isThumb1Only() ? 0 : 64;
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2007-10-31 14:39:58 +00:00
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}
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2009-05-23 19:51:43 +00:00
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/// ParseSubtargetFeatures - Parses features string setting specified
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2007-01-19 07:51:42 +00:00
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/// subtarget options. Definition of function is auto generated by tblgen.
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2011-07-07 07:07:08 +00:00
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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2007-01-19 07:51:42 +00:00
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
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void computeIssueWidth();
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2011-07-07 03:55:05 +00:00
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bool hasV4TOps() const { return HasV4TOps; }
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bool hasV5TOps() const { return HasV5TOps; }
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bool hasV5TEOps() const { return HasV5TEOps; }
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bool hasV6Ops() const { return HasV6Ops; }
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bool hasV6T2Ops() const { return HasV6T2Ops; }
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bool hasV7Ops() const { return HasV7Ops; }
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2007-01-19 07:51:42 +00:00
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2010-09-10 01:29:16 +00:00
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bool isCortexA8() const { return ARMProcFamily == CortexA8; }
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bool isCortexA9() const { return ARMProcFamily == CortexA9; }
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2011-11-09 01:57:03 +00:00
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bool isCortexM3() const { return CPUString == "cortex-m3"; }
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2010-09-10 01:29:16 +00:00
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2010-08-11 07:17:46 +00:00
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bool hasARMOps() const { return !NoARM; }
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2011-07-07 03:55:05 +00:00
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bool hasVFP2() const { return HasVFPv2; }
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bool hasVFP3() const { return HasVFPv3; }
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2012-01-22 12:07:33 +00:00
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bool hasVFP4() const { return HasVFPv4; }
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2011-07-07 03:55:05 +00:00
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bool hasNEON() const { return HasNEON; }
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2012-01-22 12:07:33 +00:00
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bool hasNEONVFP4() const { return HasNEONVFPv4; }
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2009-08-11 15:33:49 +00:00
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bool useNEONForSinglePrecisionFP() const {
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2009-08-04 17:53:06 +00:00
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return hasNEON() && UseNEONForSinglePrecisionFP; }
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2011-07-07 03:55:05 +00:00
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2010-05-06 14:57:47 +00:00
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bool hasDivide() const { return HasHardwareDivide; }
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bool hasT2ExtractPack() const { return HasT2ExtractPack; }
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2010-08-11 06:22:01 +00:00
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bool hasDataBarrier() const { return HasDataBarrier; }
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2010-12-05 22:04:16 +00:00
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bool useFPVMLx() const { return !SlowFPVMLx; }
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2011-03-31 19:38:48 +00:00
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bool hasVMLxForwarding() const { return HasVMLxForwarding; }
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2010-07-13 19:21:50 +00:00
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bool isFPBrccSlow() const { return SlowFPBrcc; }
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2010-08-11 15:44:15 +00:00
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bool isFPOnlySP() const { return FPOnlySP; }
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2010-08-09 18:35:19 +00:00
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bool prefers32BitThumb() const { return Pref32BitThumb; }
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2011-04-19 18:11:49 +00:00
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bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
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2010-11-03 06:34:55 +00:00
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bool hasMPExtension() const { return HasMPExtension; }
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2011-07-01 21:12:19 +00:00
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bool hasThumb2DSP() const { return Thumb2DSP; }
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2009-08-11 15:33:49 +00:00
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2010-03-14 18:42:38 +00:00
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bool hasFP16() const { return HasFP16; }
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2010-10-12 16:22:47 +00:00
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bool hasD16() const { return HasD16; }
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2010-03-14 18:42:38 +00:00
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2011-04-20 22:20:12 +00:00
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const Triple &getTargetTriple() const { return TargetTriple; }
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2011-12-20 18:26:50 +00:00
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bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; }
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2011-04-19 21:14:45 +00:00
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bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
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2011-09-05 21:51:43 +00:00
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bool isTargetNaCl() const {
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return TargetTriple.getOS() == Triple::NativeClient;
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}
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2011-01-11 21:46:47 +00:00
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bool isTargetELF() const { return !isTargetDarwin(); }
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2007-01-19 19:22:40 +00:00
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2007-02-13 19:52:28 +00:00
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bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
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bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
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2011-07-07 19:05:12 +00:00
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bool isThumb() const { return InThumbMode; }
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bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
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bool isThumb2() const { return InThumbMode && HasThumb2; }
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2011-07-07 00:08:19 +00:00
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bool hasThumb2() const { return HasThumb2; }
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2011-09-28 14:21:38 +00:00
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bool isMClass() const { return IsMClass; }
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bool isARClass() const { return !IsMClass; }
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2007-01-19 07:51:42 +00:00
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bool isR9Reserved() const { return IsR9Reserved; }
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2009-11-24 00:44:37 +00:00
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bool useMovt() const { return UseMovt && hasV6T2Ops(); }
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2011-10-07 17:17:49 +00:00
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bool supportsTailCall() const { return SupportsTailCall; }
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2009-11-24 00:44:37 +00:00
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2010-09-28 04:09:35 +00:00
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bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
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2009-05-23 19:50:50 +00:00
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const std::string & getCPUString() const { return CPUString; }
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2009-11-24 00:44:37 +00:00
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2010-09-28 21:57:50 +00:00
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unsigned getMispredictionPenalty() const;
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2010-12-24 04:28:06 +00:00
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2009-11-10 00:48:55 +00:00
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/// enablePostRAScheduler - True at 'More' optimization.
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2009-10-22 23:19:17 +00:00
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bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
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2011-07-01 21:01:15 +00:00
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TargetSubtargetInfo::AntiDepBreakMode& Mode,
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2009-11-13 19:52:48 +00:00
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RegClassVector& CriticalPathRCs) const;
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2009-05-23 19:50:50 +00:00
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2009-08-11 15:33:49 +00:00
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/// getInstrItins - Return the instruction itineraies based on subtarget
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2009-06-19 01:51:50 +00:00
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/// selection.
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const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
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2007-01-19 07:51:42 +00:00
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/// getStackAlignment - Returns the minimum alignment known to hold of the
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/// stack frame on entry to the function and which must be maintained by every
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/// function for this subtarget.
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unsigned getStackAlignment() const { return stackAlignment; }
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2009-08-28 23:18:09 +00:00
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/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
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/// symbol.
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2010-04-15 01:51:59 +00:00
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bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
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2007-01-19 07:51:42 +00:00
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};
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} // End llvm namespace
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#endif // ARMSUBTARGET_H
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