2006-05-14 22:18:28 +00:00
|
|
|
//===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file was developed by the "Instituto Nokia de Tecnologia" and
|
|
|
|
// is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This file contains the ARM implementation of the MRegisterInfo class.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#ifndef ARMREGISTERINFO_H
|
|
|
|
#define ARMREGISTERINFO_H
|
|
|
|
|
|
|
|
#include "llvm/Target/MRegisterInfo.h"
|
|
|
|
#include "ARMGenRegisterInfo.h.inc"
|
|
|
|
|
|
|
|
namespace llvm {
|
2007-01-19 07:51:42 +00:00
|
|
|
class ARMSubtarget;
|
2007-02-27 21:12:35 +00:00
|
|
|
class TargetInstrInfo;
|
2007-01-19 07:51:42 +00:00
|
|
|
class Type;
|
2006-05-14 22:18:28 +00:00
|
|
|
|
|
|
|
struct ARMRegisterInfo : public ARMGenRegisterInfo {
|
2006-11-27 23:37:22 +00:00
|
|
|
const TargetInstrInfo &TII;
|
2007-01-19 07:51:42 +00:00
|
|
|
const ARMSubtarget &STI;
|
|
|
|
private:
|
|
|
|
/// FramePtr - ARM physical register used as frame ptr.
|
|
|
|
unsigned FramePtr;
|
|
|
|
|
|
|
|
public:
|
|
|
|
ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
|
2006-05-14 22:18:28 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
/// getRegisterNumbering - Given the enum value for some register, e.g.
|
|
|
|
/// ARM::LR, return the number that it corresponds to (e.g. 14).
|
|
|
|
static unsigned getRegisterNumbering(unsigned RegEnum);
|
2006-05-14 22:18:28 +00:00
|
|
|
|
|
|
|
/// Code Generation virtual methods...
|
2007-01-19 07:51:42 +00:00
|
|
|
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MI,
|
|
|
|
const std::vector<CalleeSavedInfo> &CSI) const;
|
|
|
|
|
|
|
|
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MI,
|
|
|
|
const std::vector<CalleeSavedInfo> &CSI) const;
|
|
|
|
|
2006-05-14 22:18:28 +00:00
|
|
|
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MBBI,
|
|
|
|
unsigned SrcReg, int FrameIndex,
|
|
|
|
const TargetRegisterClass *RC) const;
|
|
|
|
|
|
|
|
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MBBI,
|
|
|
|
unsigned DestReg, int FrameIndex,
|
|
|
|
const TargetRegisterClass *RC) const;
|
|
|
|
|
|
|
|
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
|
|
unsigned DestReg, unsigned SrcReg,
|
|
|
|
const TargetRegisterClass *RC) const;
|
|
|
|
|
2007-03-20 08:09:38 +00:00
|
|
|
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
|
|
unsigned DestReg, const MachineInstr *Orig) const;
|
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
|
|
|
|
int FrameIndex) const;
|
2006-05-14 22:18:28 +00:00
|
|
|
|
2007-08-30 05:52:20 +00:00
|
|
|
MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
|
|
|
|
MachineInstr* LoadMI) const {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-14 14:06:15 +00:00
|
|
|
const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
|
2006-05-18 00:12:58 +00:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
const TargetRegisterClass* const*
|
|
|
|
getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
|
2006-05-18 00:12:58 +00:00
|
|
|
|
2007-02-19 21:49:54 +00:00
|
|
|
BitVector getReservedRegs(const MachineFunction &MF) const;
|
|
|
|
|
2007-03-06 10:03:56 +00:00
|
|
|
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
|
|
|
|
|
2007-02-28 00:59:19 +00:00
|
|
|
bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
2007-02-28 00:21:17 +00:00
|
|
|
|
2007-01-23 00:57:47 +00:00
|
|
|
bool hasFP(const MachineFunction &MF) const;
|
|
|
|
|
2007-05-01 00:52:08 +00:00
|
|
|
bool hasReservedCallFrame(MachineFunction &MF) const;
|
|
|
|
|
2006-05-14 22:18:28 +00:00
|
|
|
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
|
|
|
MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator I) const;
|
|
|
|
|
2007-02-28 00:21:17 +00:00
|
|
|
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
2007-05-01 09:13:03 +00:00
|
|
|
int SPAdj, RegScavenger *RS = NULL) const;
|
2006-05-14 22:18:28 +00:00
|
|
|
|
2007-03-06 10:03:56 +00:00
|
|
|
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
|
|
|
RegScavenger *RS = NULL) const;
|
2006-05-14 22:18:28 +00:00
|
|
|
|
|
|
|
void emitPrologue(MachineFunction &MF) const;
|
|
|
|
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
|
|
|
|
|
|
|
// Debug information queries.
|
|
|
|
unsigned getRARegister() const;
|
|
|
|
unsigned getFrameRegister(MachineFunction &MF) const;
|
2007-02-21 22:54:50 +00:00
|
|
|
|
|
|
|
// Exception handling queries.
|
|
|
|
unsigned getEHExceptionRegister() const;
|
|
|
|
unsigned getEHHandlerRegister() const;
|
2006-05-14 22:18:28 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
} // end namespace llvm
|
|
|
|
|
|
|
|
#endif
|