2002-08-09 20:08:06 +00:00
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//===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
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2001-11-08 04:55:13 +00:00
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//
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2002-08-09 20:08:06 +00:00
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// This file defines stuff that is to be private to the Sparc backend, but is
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// shared among different portions of the backend.
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//
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//===----------------------------------------------------------------------===//
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2001-09-14 03:56:45 +00:00
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#ifndef SPARC_INTERNALS_H
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#define SPARC_INTERNALS_H
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2003-05-24 00:09:50 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2001-09-18 22:52:44 +00:00
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#include "llvm/Target/TargetMachine.h"
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2002-12-29 03:13:05 +00:00
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#include "llvm/Target/TargetSchedInfo.h"
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2002-12-28 21:00:25 +00:00
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#include "llvm/Target/TargetFrameInfo.h"
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2002-12-29 02:50:33 +00:00
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#include "llvm/Target/TargetCacheInfo.h"
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2002-12-29 03:13:05 +00:00
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#include "llvm/Target/TargetRegInfo.h"
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2002-12-29 02:50:33 +00:00
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#include "llvm/Target/TargetOptInfo.h"
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#include "llvm/Type.h"
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2003-05-24 00:09:50 +00:00
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#include "SparcRegClassInfo.h"
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2003-06-30 21:59:07 +00:00
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#include "Config/sys/types.h"
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2001-09-14 03:56:45 +00:00
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2002-02-03 23:42:19 +00:00
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class LiveRange;
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2001-09-14 04:32:55 +00:00
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class UltraSparc;
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class PhyRegAlloc;
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class Pass;
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enum SparcInstrSchedClass {
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SPARC_NONE, /* Instructions with no scheduling restrictions */
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SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
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SPARC_IEU0, /* Integer class IEU0 */
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SPARC_IEU1, /* Integer class IEU1 */
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SPARC_FPM, /* FP Multiply or Divide instructions */
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SPARC_FPA, /* All other FP instructions */
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SPARC_CTI, /* Control-transfer instructions */
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SPARC_LD, /* Load instructions */
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SPARC_ST, /* Store instructions */
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SPARC_SINGLE, /* Instructions that must issue by themselves */
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SPARC_INV, /* This should stay at the end for the next value */
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SPARC_NUM_SCHED_CLASSES = SPARC_INV
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};
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//---------------------------------------------------------------------------
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// enum SparcMachineOpCode.
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// const TargetInstrDescriptor SparcMachineInstrDesc[]
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//
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// Purpose:
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// Description of UltraSparc machine instructions.
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//
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//---------------------------------------------------------------------------
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2003-05-20 20:32:24 +00:00
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namespace V9 {
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enum SparcMachineOpCode {
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2001-09-19 15:56:23 +00:00
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#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
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ENUM,
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#include "SparcInstr.def"
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// End-of-array marker
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INVALID_OPCODE,
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NUM_REAL_OPCODES = PHI, // number of valid opcodes
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NUM_TOTAL_OPCODES = INVALID_OPCODE
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};
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}
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2001-09-14 03:56:45 +00:00
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2001-09-19 15:56:23 +00:00
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// Array of machine instruction descriptions...
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extern const TargetInstrDescriptor SparcMachineInstrDesc[];
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//---------------------------------------------------------------------------
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// class UltraSparcInstrInfo
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//
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// Purpose:
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// Information about individual instructions.
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// Most information is stored in the SparcMachineInstrDesc array above.
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// Other information is computed on demand, and most such functions
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// default to member functions in base class TargetInstrInfo.
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//---------------------------------------------------------------------------
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struct UltraSparcInstrInfo : public TargetInstrInfo {
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UltraSparcInstrInfo();
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//
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// All immediate constants are in position 1 except the
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// store instructions and SETxx.
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//
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virtual int getImmedConstantPos(MachineOpCode opCode) const {
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bool ignore;
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if (this->maxImmedConstant(opCode, ignore) != 0) {
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// 1st store opcode
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assert(! this->isStore((MachineOpCode) V9::STBr - 1));
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// last store opcode
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assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1));
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if (opCode == V9::SETSW || opCode == V9::SETUW ||
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opCode == V9::SETX || opCode == V9::SETHI)
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return 0;
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if (opCode >= V9::STBr && opCode <= V9::STXFSRi)
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return 2;
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return 1;
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}
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2001-11-14 18:48:36 +00:00
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else
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return -1;
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}
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2003-05-24 00:09:50 +00:00
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/// createNOPinstr - returns the target's implementation of NOP, which is
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/// usually a pseudo-instruction, implemented by a degenerate version of
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2003-05-27 22:01:10 +00:00
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/// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi 0, g0
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///
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MachineInstr* createNOPinstr() const {
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return BuildMI(V9::SETHI, 2).addZImm(0).addReg(SparcIntRegClass::g0);
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}
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2003-05-24 01:08:43 +00:00
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/// isNOPinstr - not having a special NOP opcode, we need to know if a given
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/// instruction is interpreted as an `official' NOP instr, i.e., there may be
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/// more than one way to `do nothing' but only one canonical way to slack off.
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///
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bool isNOPinstr(const MachineInstr &MI) const {
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// Make sure the instruction is EXACTLY `sethi g0, 0'
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if (MI.getOpcode() == V9::SETHI && MI.getNumOperands() == 2) {
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const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
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if (op0.isImmediate() && op0.getImmedValue() == 0 &&
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op1.isMachineRegister() &&
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op1.getMachineRegNum() == SparcIntRegClass::g0)
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{
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return true;
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}
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}
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return false;
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}
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2001-09-14 03:56:45 +00:00
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2003-05-20 20:32:24 +00:00
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virtual bool hasResultInterlock(MachineOpCode opCode) const
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{
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// All UltraSPARC instructions have interlocks (note that delay slots
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// are not considered here).
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// However, instructions that use the result of an FCMP produce a
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// 9-cycle stall if they are issued less than 3 cycles after the FCMP.
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// Force the compiler to insert a software interlock (i.e., gap of
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// 2 other groups, including NOPs if necessary).
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2003-05-20 20:32:24 +00:00
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return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
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2001-09-14 03:56:45 +00:00
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}
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2002-09-16 15:39:26 +00:00
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//-------------------------------------------------------------------------
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// Queries about representation of LLVM quantities (e.g., constants)
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//-------------------------------------------------------------------------
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virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
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const Instruction* I) const;
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2001-10-18 00:02:06 +00:00
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//-------------------------------------------------------------------------
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// Code generation support for creating individual machine instructions
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//-------------------------------------------------------------------------
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2002-09-20 00:52:09 +00:00
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// Get certain common op codes for the current target. This and all the
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// Create* methods below should be moved to a machine code generation class
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//
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virtual MachineOpCode getNOPOpCode() const { return V9::NOP; }
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2002-09-20 00:52:09 +00:00
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2001-10-18 00:02:06 +00:00
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// Create an instruction sequence to put the constant `val' into
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2002-05-19 15:25:51 +00:00
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// the virtual register `dest'. `val' may be a Constant or a
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// GlobalValue, viz., the constant address of a global variable or function.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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2001-10-18 00:02:06 +00:00
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//
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2002-05-19 15:25:51 +00:00
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virtual void CreateCodeToLoadConst(const TargetMachine& target,
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Function* F,
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Value* val,
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2001-10-18 00:02:06 +00:00
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Instruction* dest,
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2002-05-19 15:25:51 +00:00
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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2001-09-14 03:56:45 +00:00
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2001-11-09 02:15:52 +00:00
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// Create an instruction sequence to copy an integer value `val'
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// to a floating point value `dest' by copying to memory and back.
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// val must be an integral type. dest must be a Float or Double.
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2002-05-19 15:25:51 +00:00
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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2001-11-08 04:55:13 +00:00
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//
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2002-05-19 15:25:51 +00:00
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virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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2001-11-09 02:15:52 +00:00
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// Similarly, create an instruction sequence to copy an FP value
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// `val' to an integer value `dest' by copying to memory and back.
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2002-05-19 15:25:51 +00:00
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create instruction(s) to copy src to dest, for arbitrary types
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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2001-11-09 02:15:52 +00:00
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//
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virtual void CreateCopyInstructionsByType(const TargetMachine& target,
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Function* F,
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Value* src,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create instruction sequence to produce a sign-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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2002-09-05 18:34:31 +00:00
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// The generated instructions are appended to `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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2002-05-19 15:25:51 +00:00
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateSignExtensionInstructions(const TargetMachine& target,
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Function* F,
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Value* srcVal,
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Value* destVal,
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unsigned int numLowBits,
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2002-09-05 18:34:31 +00:00
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create instruction sequence to produce a zero-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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// The generated instructions are appended to `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
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Function* F,
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Value* srcVal,
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2002-09-27 14:29:45 +00:00
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Value* destVal,
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unsigned int numLowBits,
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2002-05-19 15:25:51 +00:00
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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2001-11-08 04:55:13 +00:00
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};
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2001-10-28 18:15:12 +00:00
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//----------------------------------------------------------------------------
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// class UltraSparcRegInfo
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//
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2002-12-29 03:13:05 +00:00
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// This class implements the virtual class TargetRegInfo for Sparc.
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2002-01-07 20:28:49 +00:00
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//
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2001-10-28 18:15:12 +00:00
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//----------------------------------------------------------------------------
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2002-12-29 03:13:05 +00:00
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class UltraSparcRegInfo : public TargetRegInfo {
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2003-07-06 19:53:59 +00:00
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public:
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2001-09-30 23:19:57 +00:00
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// The actual register classes in the Sparc
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2002-01-07 20:28:49 +00:00
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//
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2003-07-06 19:53:59 +00:00
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// **** WARNING: If this enum order is changed, also modify
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// getRegisterClassOfValue method below since it assumes this particular
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// order for efficiency.
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//
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2001-09-15 00:30:44 +00:00
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enum RegClassIDs {
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IntRegClassID, // Integer
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FloatRegClassID, // Float (both single/double)
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IntCCRegClassID, // Int Condition Code
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2003-05-27 00:02:22 +00:00
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FloatCCRegClassID, // Float Condition code
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SpecialRegClassID // Special (unallocated) registers
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2001-09-15 00:30:44 +00:00
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};
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2003-07-06 19:53:59 +00:00
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private:
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2001-09-14 03:56:45 +00:00
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2002-01-07 20:28:49 +00:00
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// Number of registers used for passing int args (usually 6: %o0 - %o5)
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//
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2001-09-14 03:56:45 +00:00
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unsigned const NumOfIntArgRegs;
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2002-01-07 20:28:49 +00:00
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// Number of registers used for passing float args (usually 32: %f0 - %f31)
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//
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2001-09-14 03:56:45 +00:00
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unsigned const NumOfFloatArgRegs;
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2001-10-28 18:15:12 +00:00
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2002-01-07 20:28:49 +00:00
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// ======================== Private Methods =============================
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2001-09-18 22:52:44 +00:00
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2002-01-07 20:28:49 +00:00
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// The following methods are used to color special live ranges (e.g.
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2002-04-27 06:56:12 +00:00
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// function args and return values etc.) with specific hardware registers
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2002-01-07 20:28:49 +00:00
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// as required. See SparcRegInfo.cpp for the implementation.
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//
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2002-07-08 23:34:10 +00:00
|
|
|
void suggestReg4RetAddr(MachineInstr *RetMI,
|
2002-02-04 05:59:25 +00:00
|
|
|
LiveRangeInfo &LRI) const;
|
2001-10-15 16:25:28 +00:00
|
|
|
|
2002-09-28 16:56:59 +00:00
|
|
|
void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
|
2002-07-08 23:34:10 +00:00
|
|
|
|
|
|
|
void InitializeOutgoingArg(MachineInstr* CallMI, AddedInstrns *CallAI,
|
2002-05-19 15:25:51 +00:00
|
|
|
PhyRegAlloc &PRA, LiveRange* LR,
|
|
|
|
unsigned regType, unsigned RegClassID,
|
|
|
|
int UniArgReg, unsigned int argNo,
|
|
|
|
std::vector<MachineInstr *>& AddedInstrnsBefore)
|
|
|
|
const;
|
2003-05-31 07:32:01 +00:00
|
|
|
|
|
|
|
// Helper used by the all the getRegType() functions.
|
2003-05-27 00:02:22 +00:00
|
|
|
int getRegTypeForClassAndType(unsigned regClassID, const Type* type) const;
|
2001-11-03 19:59:59 +00:00
|
|
|
|
2002-01-07 20:28:49 +00:00
|
|
|
// Used to generate a copy instruction based on the register class of
|
|
|
|
// value.
|
|
|
|
//
|
2002-02-04 05:59:25 +00:00
|
|
|
MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
|
|
|
|
int RegType) const;
|
2001-11-10 21:20:43 +00:00
|
|
|
|
|
|
|
|
2002-01-07 20:28:49 +00:00
|
|
|
// The following 2 methods are used to order the instructions addeed by
|
2002-04-27 06:56:12 +00:00
|
|
|
// the register allocator in association with function calling. See
|
2002-01-07 20:28:49 +00:00
|
|
|
// SparcRegInfo.cpp for more details
|
|
|
|
//
|
2002-01-20 22:54:45 +00:00
|
|
|
void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
|
|
|
|
MachineInstr *UnordInst,
|
|
|
|
PhyRegAlloc &PRA) const;
|
2001-11-10 21:20:43 +00:00
|
|
|
|
2002-01-20 22:54:45 +00:00
|
|
|
void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
|
|
|
|
std::vector<MachineInstr *> &OrdVec,
|
|
|
|
PhyRegAlloc &PRA) const;
|
2001-11-10 21:20:43 +00:00
|
|
|
|
2002-02-04 05:59:25 +00:00
|
|
|
public:
|
2003-05-30 20:12:42 +00:00
|
|
|
// Type of registers available in Sparc. There can be several reg types
|
|
|
|
// in the same class. For instace, the float reg class has Single/Double
|
|
|
|
// types
|
|
|
|
//
|
|
|
|
enum RegTypes {
|
|
|
|
IntRegType,
|
|
|
|
FPSingleRegType,
|
|
|
|
FPDoubleRegType,
|
|
|
|
IntCCRegType,
|
|
|
|
FloatCCRegType,
|
|
|
|
SpecialRegType
|
|
|
|
};
|
|
|
|
|
2002-02-04 05:59:25 +00:00
|
|
|
UltraSparcRegInfo(const UltraSparc &tgt);
|
2002-01-07 20:28:49 +00:00
|
|
|
|
2002-03-18 03:02:42 +00:00
|
|
|
// To find the register class used for a specified Type
|
2002-01-07 20:28:49 +00:00
|
|
|
//
|
2002-07-08 23:34:10 +00:00
|
|
|
unsigned getRegClassIDOfType(const Type *type,
|
|
|
|
bool isCCReg = false) const;
|
2001-09-15 00:30:44 +00:00
|
|
|
|
2002-07-08 23:34:10 +00:00
|
|
|
// To find the register class to which a specified register belongs
|
|
|
|
//
|
|
|
|
unsigned getRegClassIDOfRegType(int regType) const;
|
2002-03-18 03:02:42 +00:00
|
|
|
|
2002-02-04 05:59:25 +00:00
|
|
|
// getZeroRegNum - returns the register that contains always zero this is the
|
|
|
|
// unified register number
|
2002-01-07 20:28:49 +00:00
|
|
|
//
|
2002-02-04 05:59:25 +00:00
|
|
|
virtual int getZeroRegNum() const;
|
2001-09-18 22:52:44 +00:00
|
|
|
|
2002-02-04 05:59:25 +00:00
|
|
|
// getCallAddressReg - returns the reg used for pushing the address when a
|
2002-04-27 06:56:12 +00:00
|
|
|
// function is called. This can be used for other purposes between calls
|
2002-01-07 20:28:49 +00:00
|
|
|
//
|
2002-02-04 05:59:25 +00:00
|
|
|
unsigned getCallAddressReg() const;
|
2001-09-18 22:52:44 +00:00
|
|
|
|
2002-01-07 20:28:49 +00:00
|
|
|
// Returns the register containing the return address.
|
|
|
|
// It should be made sure that this register contains the return
|
|
|
|
// value when a return instruction is reached.
|
|
|
|
//
|
2002-02-04 05:59:25 +00:00
|
|
|
unsigned getReturnAddressReg() const;
|
2001-09-18 22:52:44 +00:00
|
|
|
|
2002-05-19 15:25:51 +00:00
|
|
|
// Number of registers used for passing int args (usually 6: %o0 - %o5)
|
|
|
|
// and float args (usually 32: %f0 - %f31)
|
|
|
|
//
|
2003-05-25 15:59:47 +00:00
|
|
|
unsigned const getNumOfIntArgRegs() const { return NumOfIntArgRegs; }
|
|
|
|
unsigned const getNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
|
2002-05-19 15:25:51 +00:00
|
|
|
|
2003-05-31 07:32:01 +00:00
|
|
|
// Compute which register can be used for an argument, if any
|
|
|
|
//
|
|
|
|
int regNumForIntArg(bool inCallee, bool isVarArgsCall,
|
|
|
|
unsigned argNo, unsigned& regClassId) const;
|
|
|
|
|
|
|
|
int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
|
|
|
|
unsigned argNo, unsigned& regClassId) const;
|
|
|
|
|
2002-01-07 20:28:49 +00:00
|
|
|
// The following methods are used to color special live ranges (e.g.
|
2002-04-27 06:56:12 +00:00
|
|
|
// function args and return values etc.) with specific hardware registers
|
2002-01-07 20:28:49 +00:00
|
|
|
// as required. See SparcRegInfo.cpp for the implementation for Sparc.
|
|
|
|
//
|
2002-04-08 22:03:57 +00:00
|
|
|
void suggestRegs4MethodArgs(const Function *Meth,
|
2001-09-30 23:19:57 +00:00
|
|
|
LiveRangeInfo& LRI) const;
|
|
|
|
|
2002-07-08 23:34:10 +00:00
|
|
|
void suggestRegs4CallArgs(MachineInstr *CallMI,
|
2002-09-28 16:56:59 +00:00
|
|
|
LiveRangeInfo& LRI) const;
|
2001-09-30 23:19:57 +00:00
|
|
|
|
2002-07-08 23:34:10 +00:00
|
|
|
void suggestReg4RetValue(MachineInstr *RetMI,
|
2002-01-20 22:54:45 +00:00
|
|
|
LiveRangeInfo& LRI) const;
|
2002-07-08 23:34:10 +00:00
|
|
|
|
2002-04-08 22:03:57 +00:00
|
|
|
void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
|
2002-02-04 05:59:25 +00:00
|
|
|
AddedInstrns *FirstAI) const;
|
2001-09-14 03:56:45 +00:00
|
|
|
|
2002-07-08 23:34:10 +00:00
|
|
|
void colorCallArgs(MachineInstr *CallMI, LiveRangeInfo &LRI,
|
2002-02-04 05:59:25 +00:00
|
|
|
AddedInstrns *CallAI, PhyRegAlloc &PRA,
|
2002-01-07 19:20:28 +00:00
|
|
|
const BasicBlock *BB) const;
|
2001-09-18 22:52:44 +00:00
|
|
|
|
2002-07-08 23:34:10 +00:00
|
|
|
void colorRetValue(MachineInstr *RetI, LiveRangeInfo& LRI,
|
2002-02-04 05:59:25 +00:00
|
|
|
AddedInstrns *RetAI) const;
|
2001-09-30 23:19:57 +00:00
|
|
|
|
|
|
|
|
2002-01-07 20:28:49 +00:00
|
|
|
// method used for printing a register for debugging purposes
|
|
|
|
//
|
2003-05-27 00:02:22 +00:00
|
|
|
void printReg(const LiveRange *LR) const;
|
2002-07-08 23:34:10 +00:00
|
|
|
|
2002-01-07 20:28:49 +00:00
|
|
|
// returns the # of bytes of stack space allocated for each register
|
|
|
|
// type. For Sparc, currently we allocate 8 bytes on stack for all
|
|
|
|
// register types. We can optimize this later if necessary to save stack
|
|
|
|
// space (However, should make sure that stack alignment is correct)
|
|
|
|
//
|
2002-02-04 05:59:25 +00:00
|
|
|
inline int getSpilledRegSize(int RegType) const {
|
2002-01-07 19:20:28 +00:00
|
|
|
return 8;
|
|
|
|
}
|
|
|
|
|
2002-01-07 20:28:49 +00:00
|
|
|
|
2002-03-31 19:04:50 +00:00
|
|
|
// To obtain the return value and the indirect call address (if any)
|
|
|
|
// contained in a CALL machine instruction
|
2002-01-07 20:28:49 +00:00
|
|
|
//
|
2001-10-21 16:43:41 +00:00
|
|
|
const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
|
2002-03-31 19:04:50 +00:00
|
|
|
const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
|
2001-10-21 16:43:41 +00:00
|
|
|
|
2002-01-07 20:28:49 +00:00
|
|
|
// The following methods are used to generate "copy" machine instructions
|
|
|
|
// for an architecture.
|
|
|
|
//
|
2002-07-08 23:34:10 +00:00
|
|
|
// The function regTypeNeedsScratchReg() can be used to check whether a
|
|
|
|
// scratch register is needed to copy a register of type `regType' to
|
|
|
|
// or from memory. If so, such a scratch register can be provided by
|
|
|
|
// the caller (e.g., if it knows which regsiters are free); otherwise
|
|
|
|
// an arbitrary one will be chosen and spilled by the copy instructions.
|
|
|
|
//
|
|
|
|
bool regTypeNeedsScratchReg(int RegType,
|
|
|
|
int& scratchRegClassId) const;
|
|
|
|
|
|
|
|
void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
|
|
|
|
unsigned SrcReg, unsigned DestReg,
|
|
|
|
int RegType) const;
|
|
|
|
|
|
|
|
void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
|
|
|
|
unsigned SrcReg, unsigned DestPtrReg,
|
|
|
|
int Offset, int RegType, int scratchReg = -1) const;
|
2001-10-16 01:23:19 +00:00
|
|
|
|
2002-07-08 23:34:10 +00:00
|
|
|
void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
|
|
|
|
unsigned SrcPtrReg, int Offset, unsigned DestReg,
|
|
|
|
int RegType, int scratchReg = -1) const;
|
2001-11-03 17:13:27 +00:00
|
|
|
|
2002-05-19 15:25:51 +00:00
|
|
|
void cpValue2Value(Value *Src, Value *Dest,
|
2002-06-25 20:55:50 +00:00
|
|
|
std::vector<MachineInstr*>& mvec) const;
|
2001-11-03 17:13:27 +00:00
|
|
|
|
2002-01-07 20:28:49 +00:00
|
|
|
// To see whether a register is a volatile (i.e., whehter it must be
|
|
|
|
// preserved acorss calls)
|
|
|
|
//
|
2002-02-04 05:59:25 +00:00
|
|
|
inline bool isRegVolatile(int RegClassID, int Reg) const {
|
|
|
|
return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
|
2001-10-16 01:23:19 +00:00
|
|
|
}
|
|
|
|
|
2003-05-31 07:32:01 +00:00
|
|
|
// Get the register type for a register identified different ways.
|
|
|
|
int getRegType(const Type* type) const;
|
|
|
|
int getRegType(const LiveRange *LR) const;
|
|
|
|
int getRegType(int unifiedRegNum) const;
|
2001-10-16 01:23:19 +00:00
|
|
|
|
2002-02-04 05:59:25 +00:00
|
|
|
virtual unsigned getFramePointer() const;
|
|
|
|
virtual unsigned getStackPointer() const;
|
2001-10-16 01:23:19 +00:00
|
|
|
|
2002-01-07 20:28:49 +00:00
|
|
|
// This method inserts the caller saving code for call instructions
|
|
|
|
//
|
2002-07-11 00:16:28 +00:00
|
|
|
void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
|
|
|
|
std::vector<MachineInstr*>& instrnsAfter,
|
2002-07-10 21:42:42 +00:00
|
|
|
MachineInstr *MInst,
|
2001-10-28 18:15:12 +00:00
|
|
|
const BasicBlock *BB, PhyRegAlloc &PRA ) const;
|
2001-09-14 03:56:45 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
// class UltraSparcSchedInfo
|
|
|
|
//
|
|
|
|
// Purpose:
|
|
|
|
// Interface to instruction scheduling information for UltraSPARC.
|
|
|
|
// The parameter values above are based on UltraSPARC IIi.
|
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
2002-12-29 03:13:05 +00:00
|
|
|
class UltraSparcSchedInfo: public TargetSchedInfo {
|
2001-09-14 03:56:45 +00:00
|
|
|
public:
|
2002-02-04 05:59:25 +00:00
|
|
|
UltraSparcSchedInfo(const TargetMachine &tgt);
|
2001-09-14 03:56:45 +00:00
|
|
|
protected:
|
2002-02-04 05:59:25 +00:00
|
|
|
virtual void initializeResources();
|
2001-09-14 03:56:45 +00:00
|
|
|
};
|
|
|
|
|
2001-09-14 04:32:55 +00:00
|
|
|
|
2001-10-22 13:31:53 +00:00
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
// class UltraSparcFrameInfo
|
|
|
|
//
|
|
|
|
// Purpose:
|
|
|
|
// Interface to stack frame layout info for the UltraSPARC.
|
2001-11-12 23:26:35 +00:00
|
|
|
// Starting offsets for each area of the stack frame are aligned at
|
|
|
|
// a multiple of getStackFrameSizeAlignment().
|
2001-10-22 13:31:53 +00:00
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
2002-12-28 20:20:24 +00:00
|
|
|
class UltraSparcFrameInfo: public TargetFrameInfo {
|
|
|
|
const TargetMachine ⌖
|
2001-10-22 13:31:53 +00:00
|
|
|
public:
|
2002-12-28 20:20:24 +00:00
|
|
|
UltraSparcFrameInfo(const TargetMachine &TM)
|
|
|
|
: TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {}
|
2001-11-08 04:55:13 +00:00
|
|
|
|
|
|
|
public:
|
2002-09-16 15:39:26 +00:00
|
|
|
// These methods provide constant parameters of the frame layout.
|
|
|
|
//
|
2002-04-27 06:56:12 +00:00
|
|
|
int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
|
|
|
|
int getMinStackFrameSize() const { return MinStackFrameSize; }
|
|
|
|
int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
|
|
|
|
int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
|
|
|
|
bool argsOnStackHaveFixedSize() const { return true; }
|
2001-11-08 04:55:13 +00:00
|
|
|
|
2002-09-16 15:39:26 +00:00
|
|
|
// This method adjusts a stack offset to meet alignment rules of target.
|
|
|
|
// The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
|
|
|
|
virtual int adjustAlignment (int unalignedOffset,
|
|
|
|
bool growUp,
|
|
|
|
unsigned int align) const {
|
|
|
|
return unalignedOffset + (growUp? +1:-1)*((unalignedOffset-OFFSET) % align);
|
|
|
|
}
|
|
|
|
|
2001-11-08 04:55:13 +00:00
|
|
|
// These methods compute offsets using the frame contents for a
|
2002-04-27 06:56:12 +00:00
|
|
|
// particular function. The frame contents are obtained from the
|
|
|
|
// MachineCodeInfoForMethod object for the given function.
|
2001-11-08 04:55:13 +00:00
|
|
|
//
|
2002-10-28 00:28:31 +00:00
|
|
|
int getFirstIncomingArgOffset (MachineFunction& mcInfo,
|
2002-04-25 04:40:24 +00:00
|
|
|
bool& growUp) const
|
2001-11-08 04:55:13 +00:00
|
|
|
{
|
2002-04-25 04:40:24 +00:00
|
|
|
growUp = true; // arguments area grows upwards
|
2001-11-08 04:55:13 +00:00
|
|
|
return FirstIncomingArgOffsetFromFP;
|
|
|
|
}
|
2002-10-28 00:28:31 +00:00
|
|
|
int getFirstOutgoingArgOffset (MachineFunction& mcInfo,
|
2002-04-25 04:40:24 +00:00
|
|
|
bool& growUp) const
|
2001-11-08 04:55:13 +00:00
|
|
|
{
|
2002-04-25 04:40:24 +00:00
|
|
|
growUp = true; // arguments area grows upwards
|
2001-11-08 04:55:13 +00:00
|
|
|
return FirstOutgoingArgOffsetFromSP;
|
|
|
|
}
|
2002-10-28 00:28:31 +00:00
|
|
|
int getFirstOptionalOutgoingArgOffset(MachineFunction& mcInfo,
|
2002-04-25 04:40:24 +00:00
|
|
|
bool& growUp)const
|
2001-11-08 04:55:13 +00:00
|
|
|
{
|
2002-04-25 04:40:24 +00:00
|
|
|
growUp = true; // arguments area grows upwards
|
2001-11-08 04:55:13 +00:00
|
|
|
return FirstOptionalOutgoingArgOffsetFromSP;
|
|
|
|
}
|
|
|
|
|
2002-10-28 00:28:31 +00:00
|
|
|
int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
|
2002-04-25 04:40:24 +00:00
|
|
|
bool& growUp) const;
|
2002-10-28 00:28:31 +00:00
|
|
|
int getRegSpillAreaOffset (MachineFunction& mcInfo,
|
2002-04-25 04:40:24 +00:00
|
|
|
bool& growUp) const;
|
2002-10-28 00:28:31 +00:00
|
|
|
int getTmpAreaOffset (MachineFunction& mcInfo,
|
2002-04-25 04:40:24 +00:00
|
|
|
bool& growUp) const;
|
2002-10-28 00:28:31 +00:00
|
|
|
int getDynamicAreaOffset (MachineFunction& mcInfo,
|
2002-04-25 04:40:24 +00:00
|
|
|
bool& growUp) const;
|
2001-11-08 04:55:13 +00:00
|
|
|
|
|
|
|
//
|
|
|
|
// These methods specify the base register used for each stack area
|
|
|
|
// (generally FP or SP)
|
|
|
|
//
|
|
|
|
virtual int getIncomingArgBaseRegNum() const {
|
|
|
|
return (int) target.getRegInfo().getFramePointer();
|
|
|
|
}
|
|
|
|
virtual int getOutgoingArgBaseRegNum() const {
|
|
|
|
return (int) target.getRegInfo().getStackPointer();
|
|
|
|
}
|
|
|
|
virtual int getOptionalOutgoingArgBaseRegNum() const {
|
|
|
|
return (int) target.getRegInfo().getStackPointer();
|
|
|
|
}
|
|
|
|
virtual int getAutomaticVarBaseRegNum() const {
|
|
|
|
return (int) target.getRegInfo().getFramePointer();
|
|
|
|
}
|
|
|
|
virtual int getRegSpillAreaBaseRegNum() const {
|
|
|
|
return (int) target.getRegInfo().getFramePointer();
|
|
|
|
}
|
|
|
|
virtual int getDynamicAreaBaseRegNum() const {
|
|
|
|
return (int) target.getRegInfo().getStackPointer();
|
|
|
|
}
|
2002-12-28 20:20:24 +00:00
|
|
|
|
|
|
|
virtual int getIncomingArgOffset(MachineFunction& mcInfo,
|
|
|
|
unsigned argNum) const {
|
|
|
|
assert(argsOnStackHaveFixedSize());
|
|
|
|
|
|
|
|
unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
|
|
|
|
bool growUp; // do args grow up or down
|
|
|
|
int firstArg = getFirstIncomingArgOffset(mcInfo, growUp);
|
|
|
|
return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
|
|
|
|
}
|
|
|
|
|
|
|
|
virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
|
|
|
|
unsigned argNum) const {
|
|
|
|
assert(argsOnStackHaveFixedSize());
|
|
|
|
//assert(((int) argNum - this->getNumFixedOutgoingArgs())
|
|
|
|
// <= (int) mcInfo.getInfo()->getMaxOptionalNumArgs());
|
|
|
|
|
|
|
|
unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
|
|
|
|
bool growUp; // do args grow up or down
|
|
|
|
int firstArg = getFirstOutgoingArgOffset(mcInfo, growUp);
|
|
|
|
return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
|
|
|
|
}
|
2001-11-08 04:55:13 +00:00
|
|
|
|
|
|
|
private:
|
2002-09-16 15:39:26 +00:00
|
|
|
/*----------------------------------------------------------------------
|
|
|
|
This diagram shows the stack frame layout used by llc on Sparc V9.
|
|
|
|
Note that only the location of automatic variables, spill area,
|
|
|
|
temporary storage, and dynamically allocated stack area are chosen
|
|
|
|
by us. The rest conform to the Sparc V9 ABI.
|
|
|
|
All stack addresses are offset by OFFSET = 0x7ff (2047).
|
|
|
|
|
2002-12-28 20:20:24 +00:00
|
|
|
Alignment assumptions and other invariants:
|
2002-09-16 15:39:26 +00:00
|
|
|
(1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary
|
|
|
|
(2) Variables in automatic, spill, temporary, or dynamic regions
|
|
|
|
are aligned according to their size as in all memory accesses.
|
|
|
|
(3) Everything below the dynamically allocated stack area is only used
|
|
|
|
during a call to another function, so it is never needed when
|
|
|
|
the current function is active. This is why space can be allocated
|
|
|
|
dynamically by incrementing %sp any time within the function.
|
|
|
|
|
|
|
|
STACK FRAME LAYOUT:
|
|
|
|
|
|
|
|
...
|
|
|
|
%fp+OFFSET+176 Optional extra incoming arguments# 1..N
|
|
|
|
%fp+OFFSET+168 Incoming argument #6
|
|
|
|
... ...
|
|
|
|
%fp+OFFSET+128 Incoming argument #1
|
|
|
|
... ...
|
|
|
|
---%fp+OFFSET-0--------Bottom of caller's stack frame--------------------
|
|
|
|
%fp+OFFSET-8 Automatic variables <-- ****TOP OF STACK FRAME****
|
|
|
|
Spill area
|
|
|
|
Temporary storage
|
|
|
|
...
|
|
|
|
|
|
|
|
%sp+OFFSET+176+8N Bottom of dynamically allocated stack area
|
|
|
|
%sp+OFFSET+168+8N Optional extra outgoing argument# N
|
|
|
|
... ...
|
|
|
|
%sp+OFFSET+176 Optional extra outgoing argument# 1
|
|
|
|
%sp+OFFSET+168 Outgoing argument #6
|
|
|
|
... ...
|
|
|
|
%sp+OFFSET+128 Outgoing argument #1
|
|
|
|
%sp+OFFSET+120 Save area for %i7
|
|
|
|
... ...
|
|
|
|
%sp+OFFSET+0 Save area for %l0 <-- ****BOTTOM OF STACK FRAME****
|
|
|
|
|
|
|
|
*----------------------------------------------------------------------*/
|
|
|
|
|
2001-11-09 02:15:52 +00:00
|
|
|
// All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
|
|
|
|
static const int OFFSET = (int) 0x7ff;
|
2001-11-08 04:55:13 +00:00
|
|
|
static const int StackFrameSizeAlignment = 16;
|
2001-10-22 13:31:53 +00:00
|
|
|
static const int MinStackFrameSize = 176;
|
2001-11-08 04:55:13 +00:00
|
|
|
static const int NumFixedOutgoingArgs = 6;
|
|
|
|
static const int SizeOfEachArgOnStack = 8;
|
2001-11-09 02:15:52 +00:00
|
|
|
static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
|
|
|
|
static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
|
2002-09-16 15:39:26 +00:00
|
|
|
static const int StaticAreaOffsetFromFP = 0 + OFFSET;
|
2001-11-09 02:15:52 +00:00
|
|
|
static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
|
|
|
|
static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
|
2001-10-22 13:31:53 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
2001-11-09 02:15:52 +00:00
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
// class UltraSparcCacheInfo
|
|
|
|
//
|
|
|
|
// Purpose:
|
|
|
|
// Interface to cache parameters for the UltraSPARC.
|
|
|
|
// Just use defaults for now.
|
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
2002-12-29 02:50:33 +00:00
|
|
|
struct UltraSparcCacheInfo: public TargetCacheInfo {
|
|
|
|
UltraSparcCacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {}
|
2001-11-09 02:15:52 +00:00
|
|
|
};
|
|
|
|
|
2001-10-22 13:31:53 +00:00
|
|
|
|
2002-09-20 00:52:09 +00:00
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
// class UltraSparcOptInfo
|
|
|
|
//
|
|
|
|
// Purpose:
|
|
|
|
// Interface to machine-level optimization routines for the UltraSPARC.
|
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
2002-12-29 02:50:33 +00:00
|
|
|
struct UltraSparcOptInfo: public TargetOptInfo {
|
|
|
|
UltraSparcOptInfo(const TargetMachine &T) : TargetOptInfo(T) {}
|
2002-09-20 00:52:09 +00:00
|
|
|
|
|
|
|
virtual bool IsUselessCopy (const MachineInstr* MI) const;
|
|
|
|
};
|
|
|
|
|
2003-05-27 22:01:10 +00:00
|
|
|
/// createAddRegNumToValuesPass - this pass adds unsigned register numbers to
|
|
|
|
/// instructions, since that's not done by the Sparc InstSelector, but that's
|
|
|
|
/// how the target-independent register allocator in the JIT likes to see
|
|
|
|
/// instructions. This pass enables the usage of the JIT register allocator(s).
|
|
|
|
Pass *createAddRegNumToValuesPass();
|
|
|
|
|
2001-09-14 04:32:55 +00:00
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
// class UltraSparcMachine
|
|
|
|
//
|
|
|
|
// Purpose:
|
|
|
|
// Primary interface to machine description for the UltraSPARC.
|
|
|
|
// Primarily just initializes machine-dependent parameters in
|
|
|
|
// class TargetMachine, and creates machine-dependent subclasses
|
2001-09-18 13:04:24 +00:00
|
|
|
// for classes such as InstrInfo, SchedInfo and RegInfo.
|
2001-09-14 04:32:55 +00:00
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
|
|
|
class UltraSparc : public TargetMachine {
|
2001-09-18 13:04:24 +00:00
|
|
|
UltraSparcInstrInfo instrInfo;
|
|
|
|
UltraSparcSchedInfo schedInfo;
|
|
|
|
UltraSparcRegInfo regInfo;
|
2001-10-22 13:31:53 +00:00
|
|
|
UltraSparcFrameInfo frameInfo;
|
2001-11-09 02:15:52 +00:00
|
|
|
UltraSparcCacheInfo cacheInfo;
|
2002-09-20 00:52:09 +00:00
|
|
|
UltraSparcOptInfo optInfo;
|
2001-09-14 04:32:55 +00:00
|
|
|
public:
|
|
|
|
UltraSparc();
|
2002-09-20 00:52:09 +00:00
|
|
|
|
2003-01-14 22:00:31 +00:00
|
|
|
virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
|
2002-12-29 03:13:05 +00:00
|
|
|
virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
|
|
|
|
virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
|
2002-12-28 20:20:24 +00:00
|
|
|
virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
|
2002-12-29 02:50:33 +00:00
|
|
|
virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; }
|
|
|
|
virtual const TargetOptInfo &getOptInfo() const { return optInfo; }
|
2001-09-19 13:47:12 +00:00
|
|
|
|
2002-10-29 21:12:46 +00:00
|
|
|
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
|
2003-05-27 22:01:10 +00:00
|
|
|
virtual bool addPassesToJITCompile(PassManager &PM);
|
|
|
|
virtual bool addPassesToEmitMachineCode(PassManager &PM,
|
|
|
|
MachineCodeEmitter &MCE);
|
2002-10-28 01:03:43 +00:00
|
|
|
|
2002-10-29 22:01:44 +00:00
|
|
|
// getPrologEpilogInsertionPass - Inserts prolog/epilog code.
|
|
|
|
Pass* getPrologEpilogInsertionPass();
|
2002-02-03 07:51:17 +00:00
|
|
|
|
2002-09-16 15:39:26 +00:00
|
|
|
// getFunctionAsmPrinterPass - Writes out machine code for a single function
|
2002-10-29 22:01:44 +00:00
|
|
|
Pass* getFunctionAsmPrinterPass(std::ostream &Out);
|
2002-09-16 15:39:26 +00:00
|
|
|
|
|
|
|
// getModuleAsmPrinterPass - Writes generated machine code to assembly file.
|
2002-10-29 22:01:44 +00:00
|
|
|
Pass* getModuleAsmPrinterPass(std::ostream &Out);
|
2002-09-16 15:39:26 +00:00
|
|
|
|
|
|
|
// getEmitBytecodeToAsmPass - Emits final LLVM bytecode to assembly file.
|
2002-10-29 22:01:44 +00:00
|
|
|
Pass* getEmitBytecodeToAsmPass(std::ostream &Out);
|
2002-02-03 07:51:17 +00:00
|
|
|
};
|
2001-09-14 04:32:55 +00:00
|
|
|
|
2003-01-15 21:36:50 +00:00
|
|
|
int64_t GetConstantValueAsSignedInt(const Value *V, bool &isValidConstant);
|
|
|
|
|
2003-06-16 15:31:09 +00:00
|
|
|
Pass *getFunctionInfo(std::ostream &out);
|
|
|
|
|
2001-09-14 03:56:45 +00:00
|
|
|
#endif
|