2004-08-16 01:09:52 +00:00
|
|
|
//===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
|
2005-04-22 00:00:37 +00:00
|
|
|
//
|
2004-08-16 01:09:52 +00:00
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-29 20:37:13 +00:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2005-04-22 00:00:37 +00:00
|
|
|
//
|
2004-08-16 01:09:52 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This file defines structures to encapsulate information gleaned from the
|
|
|
|
// target register and register class definitions.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#ifndef CODEGEN_REGISTERS_H
|
|
|
|
#define CODEGEN_REGISTERS_H
|
|
|
|
|
2011-06-15 05:09:20 +00:00
|
|
|
#include "SetTheory.h"
|
2011-06-15 04:50:36 +00:00
|
|
|
#include "llvm/ADT/ArrayRef.h"
|
2011-09-30 00:10:40 +00:00
|
|
|
#include "llvm/ADT/BitVector.h"
|
2010-05-24 21:46:58 +00:00
|
|
|
#include "llvm/ADT/DenseMap.h"
|
2011-06-12 03:05:52 +00:00
|
|
|
#include "llvm/ADT/SetVector.h"
|
2012-12-04 10:37:14 +00:00
|
|
|
#include "llvm/CodeGen/ValueTypes.h"
|
2012-02-05 07:21:30 +00:00
|
|
|
#include "llvm/Support/ErrorHandling.h"
|
2012-12-04 10:37:14 +00:00
|
|
|
#include "llvm/TableGen/Record.h"
|
2011-06-11 00:28:06 +00:00
|
|
|
#include <cstdlib>
|
|
|
|
#include <map>
|
2010-08-25 00:41:18 +00:00
|
|
|
#include <set>
|
2012-12-04 10:37:14 +00:00
|
|
|
#include <string>
|
2011-06-11 00:28:06 +00:00
|
|
|
#include <vector>
|
2004-08-16 01:09:52 +00:00
|
|
|
|
|
|
|
namespace llvm {
|
2011-06-11 00:28:06 +00:00
|
|
|
class CodeGenRegBank;
|
2004-08-16 01:09:52 +00:00
|
|
|
|
2012-01-31 20:57:55 +00:00
|
|
|
/// CodeGenSubRegIndex - Represents a sub-register index.
|
|
|
|
class CodeGenSubRegIndex {
|
|
|
|
Record *const TheDef;
|
2012-08-15 18:00:55 +00:00
|
|
|
std::string Name;
|
|
|
|
std::string Namespace;
|
2013-05-31 17:08:36 +00:00
|
|
|
uint16_t Size;
|
|
|
|
uint16_t Offset;
|
2012-01-31 20:57:55 +00:00
|
|
|
|
|
|
|
public:
|
2012-05-14 15:10:07 +00:00
|
|
|
const unsigned EnumValue;
|
2012-09-11 16:34:08 +00:00
|
|
|
unsigned LaneMask;
|
2012-05-14 15:10:07 +00:00
|
|
|
|
2013-05-16 18:03:08 +00:00
|
|
|
// Are all super-registers containing this SubRegIndex covered by their
|
|
|
|
// sub-registers?
|
|
|
|
bool AllSuperRegsCovered;
|
|
|
|
|
2012-01-31 20:57:55 +00:00
|
|
|
CodeGenSubRegIndex(Record *R, unsigned Enum);
|
2012-08-15 18:00:55 +00:00
|
|
|
CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
|
2012-01-31 20:57:55 +00:00
|
|
|
|
2012-08-15 18:00:55 +00:00
|
|
|
const std::string &getName() const { return Name; }
|
|
|
|
const std::string &getNamespace() const { return Namespace; }
|
2012-01-31 20:57:55 +00:00
|
|
|
std::string getQualifiedName() const;
|
2013-05-31 17:08:36 +00:00
|
|
|
uint16_t getSize() const { return Size; }
|
|
|
|
uint16_t getOffset() const { return Offset; }
|
2012-01-31 20:57:55 +00:00
|
|
|
|
|
|
|
// Order CodeGenSubRegIndex pointers by EnumValue.
|
|
|
|
struct Less {
|
|
|
|
bool operator()(const CodeGenSubRegIndex *A,
|
|
|
|
const CodeGenSubRegIndex *B) const {
|
|
|
|
assert(A && B);
|
|
|
|
return A->EnumValue < B->EnumValue;
|
|
|
|
}
|
|
|
|
};
|
2012-01-31 21:44:11 +00:00
|
|
|
|
|
|
|
// Map of composite subreg indices.
|
|
|
|
typedef std::map<CodeGenSubRegIndex*, CodeGenSubRegIndex*, Less> CompMap;
|
|
|
|
|
|
|
|
// Returns the subreg index that results from composing this with Idx.
|
|
|
|
// Returns NULL if this and Idx don't compose.
|
|
|
|
CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
|
|
|
|
CompMap::const_iterator I = Composed.find(Idx);
|
|
|
|
return I == Composed.end() ? 0 : I->second;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Add a composite subreg index: this+A = B.
|
|
|
|
// Return a conflicting composite, or NULL
|
|
|
|
CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
|
|
|
|
CodeGenSubRegIndex *B) {
|
Compute secondary sub-registers.
The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:
Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3]
But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.
This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.
This will eventually enable the coalescer to handle copies of skewed
sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 23:27:10 +00:00
|
|
|
assert(A && B);
|
2012-01-31 21:44:11 +00:00
|
|
|
std::pair<CompMap::iterator, bool> Ins =
|
|
|
|
Composed.insert(std::make_pair(A, B));
|
2013-05-31 17:08:36 +00:00
|
|
|
// Synthetic subreg indices that aren't contiguous (for instance ARM
|
|
|
|
// register tuples) don't have a bit range, so it's OK to let
|
|
|
|
// B->Offset == -1. For the other cases, accumulate the offset and set
|
|
|
|
// the size here. Only do so if there is no offset yet though.
|
|
|
|
if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
|
|
|
|
(B->Offset == (uint16_t)-1)) {
|
|
|
|
B->Offset = Offset + A->Offset;
|
|
|
|
B->Size = A->Size;
|
|
|
|
}
|
2012-01-31 21:44:11 +00:00
|
|
|
return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second;
|
|
|
|
}
|
|
|
|
|
2012-02-01 23:16:41 +00:00
|
|
|
// Update the composite maps of components specified in 'ComposedOf'.
|
|
|
|
void updateComponents(CodeGenRegBank&);
|
|
|
|
|
2012-01-31 21:44:11 +00:00
|
|
|
// Return the map of composites.
|
|
|
|
const CompMap &getComposites() const { return Composed; }
|
|
|
|
|
2012-09-11 16:34:08 +00:00
|
|
|
// Compute LaneMask from Composed. Return LaneMask.
|
|
|
|
unsigned computeLaneMask();
|
|
|
|
|
2012-01-31 21:44:11 +00:00
|
|
|
private:
|
|
|
|
CompMap Composed;
|
2012-01-31 20:57:55 +00:00
|
|
|
};
|
|
|
|
|
2004-08-16 01:09:52 +00:00
|
|
|
/// CodeGenRegister - Represents a register definition.
|
|
|
|
struct CodeGenRegister {
|
|
|
|
Record *TheDef;
|
2011-03-11 01:33:54 +00:00
|
|
|
unsigned EnumValue;
|
2011-04-20 18:19:48 +00:00
|
|
|
unsigned CostPerUse;
|
2012-01-18 00:16:39 +00:00
|
|
|
bool CoveredBySubRegs;
|
2011-06-11 00:28:06 +00:00
|
|
|
|
|
|
|
// Map SubRegIndex -> Register.
|
2012-01-31 20:57:55 +00:00
|
|
|
typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*,
|
|
|
|
CodeGenSubRegIndex::Less> SubRegMap;
|
2011-06-11 00:28:06 +00:00
|
|
|
|
|
|
|
CodeGenRegister(Record *R, unsigned Enum);
|
|
|
|
|
|
|
|
const std::string &getName() const;
|
|
|
|
|
2012-05-10 17:46:18 +00:00
|
|
|
// Extract more information from TheDef. This is used to build an object
|
|
|
|
// graph after all CodeGenRegister objects have been created.
|
|
|
|
void buildObjectGraph(CodeGenRegBank&);
|
|
|
|
|
2012-05-09 22:09:17 +00:00
|
|
|
// Lazily compute a map of all sub-registers.
|
2011-06-11 00:28:06 +00:00
|
|
|
// This includes unique entries for all sub-sub-registers.
|
2012-05-09 22:09:17 +00:00
|
|
|
const SubRegMap &computeSubRegs(CodeGenRegBank&);
|
2011-06-11 00:28:06 +00:00
|
|
|
|
Compute secondary sub-registers.
The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:
Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3]
But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.
This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.
This will eventually enable the coalescer to handle copies of skewed
sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 23:27:10 +00:00
|
|
|
// Compute extra sub-registers by combining the existing sub-registers.
|
|
|
|
void computeSecondarySubRegs(CodeGenRegBank&);
|
|
|
|
|
2012-05-11 19:01:01 +00:00
|
|
|
// Add this as a super-register to all sub-registers after the sub-register
|
|
|
|
// graph has been built.
|
2012-05-14 15:10:07 +00:00
|
|
|
void computeSuperRegs(CodeGenRegBank&);
|
2012-05-11 19:01:01 +00:00
|
|
|
|
2011-06-11 00:28:06 +00:00
|
|
|
const SubRegMap &getSubRegs() const {
|
|
|
|
assert(SubRegsComplete && "Must precompute sub-registers");
|
|
|
|
return SubRegs;
|
|
|
|
}
|
|
|
|
|
2011-06-12 03:05:52 +00:00
|
|
|
// Add sub-registers to OSet following a pre-order defined by the .td file.
|
2012-03-29 18:03:59 +00:00
|
|
|
void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
|
2012-01-31 20:57:55 +00:00
|
|
|
CodeGenRegBank&) const;
|
2011-06-12 03:05:52 +00:00
|
|
|
|
2012-05-09 22:15:00 +00:00
|
|
|
// Return the sub-register index naming Reg as a sub-register of this
|
|
|
|
// register. Returns NULL if Reg is not a sub-register.
|
|
|
|
CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
|
|
|
|
return SubReg2Idx.lookup(Reg);
|
|
|
|
}
|
|
|
|
|
2012-03-29 18:03:59 +00:00
|
|
|
typedef std::vector<const CodeGenRegister*> SuperRegList;
|
2011-06-12 03:05:52 +00:00
|
|
|
|
Compute secondary sub-registers.
The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:
Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3]
But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.
This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.
This will eventually enable the coalescer to handle copies of skewed
sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 23:27:10 +00:00
|
|
|
// Get the list of super-registers in topological order, small to large.
|
|
|
|
// This is valid after computeSubRegs visits all registers during RegBank
|
|
|
|
// construction.
|
2011-06-12 03:05:52 +00:00
|
|
|
const SuperRegList &getSuperRegs() const {
|
|
|
|
assert(SubRegsComplete && "Must precompute sub-registers");
|
|
|
|
return SuperRegs;
|
|
|
|
}
|
|
|
|
|
2012-05-14 15:12:37 +00:00
|
|
|
// Get the list of ad hoc aliases. The graph is symmetric, so the list
|
|
|
|
// contains all registers in 'Aliases', and all registers that mention this
|
|
|
|
// register in 'Aliases'.
|
|
|
|
ArrayRef<CodeGenRegister*> getExplicitAliases() const {
|
|
|
|
return ExplicitAliases;
|
|
|
|
}
|
|
|
|
|
2012-05-14 15:10:07 +00:00
|
|
|
// Get the topological signature of this register. This is a small integer
|
|
|
|
// less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
|
|
|
|
// identical sub-register structure. That is, they support the same set of
|
|
|
|
// sub-register indices mapping to the same kind of sub-registers
|
|
|
|
// (TopoSig-wise).
|
|
|
|
unsigned getTopoSig() const {
|
|
|
|
assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
|
|
|
|
return TopoSig;
|
|
|
|
}
|
|
|
|
|
2012-03-31 01:35:59 +00:00
|
|
|
// List of register units in ascending order.
|
|
|
|
typedef SmallVector<unsigned, 16> RegUnitList;
|
|
|
|
|
2012-05-29 23:40:00 +00:00
|
|
|
// How many entries in RegUnitList are native?
|
|
|
|
unsigned NumNativeRegUnits;
|
|
|
|
|
2012-03-31 01:35:59 +00:00
|
|
|
// Get the list of register units.
|
2012-05-29 23:40:00 +00:00
|
|
|
// This is only valid after computeSubRegs() completes.
|
2012-03-31 01:35:59 +00:00
|
|
|
const RegUnitList &getRegUnits() const { return RegUnits; }
|
|
|
|
|
2012-05-29 23:40:00 +00:00
|
|
|
// Get the native register units. This is a prefix of getRegUnits().
|
|
|
|
ArrayRef<unsigned> getNativeRegUnits() const {
|
|
|
|
return makeArrayRef(RegUnits).slice(0, NumNativeRegUnits);
|
|
|
|
}
|
|
|
|
|
2012-04-10 02:25:21 +00:00
|
|
|
// Inherit register units from subregisters.
|
|
|
|
// Return true if the RegUnits changed.
|
|
|
|
bool inheritRegUnits(CodeGenRegBank &RegBank);
|
|
|
|
|
|
|
|
// Adopt a register unit for pressure tracking.
|
2012-09-27 10:14:43 +00:00
|
|
|
// A unit is adopted iff its unit number is >= NumNativeRegUnits.
|
2012-04-10 02:25:21 +00:00
|
|
|
void adoptRegUnit(unsigned RUID) { RegUnits.push_back(RUID); }
|
|
|
|
|
|
|
|
// Get the sum of this register's register unit weights.
|
|
|
|
unsigned getWeight(const CodeGenRegBank &RegBank) const;
|
|
|
|
|
2011-06-12 03:05:52 +00:00
|
|
|
// Order CodeGenRegister pointers by EnumValue.
|
|
|
|
struct Less {
|
2011-06-15 04:50:36 +00:00
|
|
|
bool operator()(const CodeGenRegister *A,
|
|
|
|
const CodeGenRegister *B) const {
|
2011-10-04 15:28:49 +00:00
|
|
|
assert(A && B);
|
2011-06-12 03:05:52 +00:00
|
|
|
return A->EnumValue < B->EnumValue;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
// Canonically ordered set.
|
2011-06-15 04:50:36 +00:00
|
|
|
typedef std::set<const CodeGenRegister*, Less> Set;
|
2011-06-12 03:05:52 +00:00
|
|
|
|
2011-06-11 00:28:06 +00:00
|
|
|
private:
|
|
|
|
bool SubRegsComplete;
|
2012-05-11 19:01:01 +00:00
|
|
|
bool SuperRegsComplete;
|
2012-05-14 15:10:07 +00:00
|
|
|
unsigned TopoSig;
|
2012-05-10 17:46:18 +00:00
|
|
|
|
|
|
|
// The sub-registers explicit in the .td file form a tree.
|
|
|
|
SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices;
|
|
|
|
SmallVector<CodeGenRegister*, 8> ExplicitSubRegs;
|
|
|
|
|
2012-05-14 15:12:37 +00:00
|
|
|
// Explicit ad hoc aliases, symmetrized to form an undirected graph.
|
|
|
|
SmallVector<CodeGenRegister*, 8> ExplicitAliases;
|
|
|
|
|
Compute secondary sub-registers.
The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:
Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3]
But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.
This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.
This will eventually enable the coalescer to handle copies of skewed
sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 23:27:10 +00:00
|
|
|
// Super-registers where this is the first explicit sub-register.
|
|
|
|
SuperRegList LeadingSuperRegs;
|
|
|
|
|
2011-06-11 00:28:06 +00:00
|
|
|
SubRegMap SubRegs;
|
2011-06-12 03:05:52 +00:00
|
|
|
SuperRegList SuperRegs;
|
2012-05-09 22:15:00 +00:00
|
|
|
DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
|
2012-03-31 01:35:59 +00:00
|
|
|
RegUnitList RegUnits;
|
2004-08-16 01:09:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
2011-06-15 04:50:36 +00:00
|
|
|
class CodeGenRegisterClass {
|
|
|
|
CodeGenRegister::Set Members;
|
2011-10-04 15:28:44 +00:00
|
|
|
// Allocation orders. Order[0] always contains all registers in Members.
|
|
|
|
std::vector<SmallVector<Record*, 16> > Orders;
|
2011-09-30 00:10:40 +00:00
|
|
|
// Bit mask of sub-classes including this, indexed by their EnumValue.
|
|
|
|
BitVector SubClasses;
|
2011-09-30 22:18:45 +00:00
|
|
|
// List of super-classes, topologocally ordered to have the larger classes
|
|
|
|
// first. This is the same as sorting by EnumValue.
|
|
|
|
SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
|
2004-08-21 04:05:00 +00:00
|
|
|
Record *TheDef;
|
2011-10-04 15:28:08 +00:00
|
|
|
std::string Name;
|
2011-10-04 15:28:49 +00:00
|
|
|
|
|
|
|
// For a synthesized class, inherit missing properties from the nearest
|
|
|
|
// super-class.
|
|
|
|
void inheritProperties(CodeGenRegBank&);
|
|
|
|
|
2011-12-19 16:53:34 +00:00
|
|
|
// Map SubRegIndex -> sub-class. This is the largest sub-class where all
|
|
|
|
// registers have a SubRegIndex sub-register.
|
2012-01-31 20:57:55 +00:00
|
|
|
DenseMap<CodeGenSubRegIndex*, CodeGenRegisterClass*> SubClassWithSubReg;
|
2011-10-05 00:35:49 +00:00
|
|
|
|
2011-12-19 16:53:34 +00:00
|
|
|
// Map SubRegIndex -> set of super-reg classes. This is all register
|
|
|
|
// classes SuperRC such that:
|
|
|
|
//
|
|
|
|
// R:SubRegIndex in this RC for all R in SuperRC.
|
|
|
|
//
|
2012-01-31 20:57:55 +00:00
|
|
|
DenseMap<CodeGenSubRegIndex*,
|
|
|
|
SmallPtrSet<CodeGenRegisterClass*, 8> > SuperRegClasses;
|
2012-04-10 02:25:24 +00:00
|
|
|
|
2012-05-14 15:10:07 +00:00
|
|
|
// Bit vector of TopoSigs for the registers in this class. This will be
|
|
|
|
// very sparse on regular architectures.
|
|
|
|
BitVector TopoSigs;
|
|
|
|
|
2011-10-04 15:28:08 +00:00
|
|
|
public:
|
2011-09-30 00:10:36 +00:00
|
|
|
unsigned EnumValue;
|
2005-08-19 18:45:20 +00:00
|
|
|
std::string Namespace;
|
2013-03-17 17:26:09 +00:00
|
|
|
SmallVector<MVT::SimpleValueType, 4> VTs;
|
2004-08-21 04:05:00 +00:00
|
|
|
unsigned SpillSize;
|
|
|
|
unsigned SpillAlignment;
|
2007-09-19 01:35:01 +00:00
|
|
|
int CopyCost;
|
2011-06-02 23:07:20 +00:00
|
|
|
bool Allocatable;
|
2011-06-18 03:08:20 +00:00
|
|
|
std::string AltOrderSelect;
|
2004-08-21 04:05:00 +00:00
|
|
|
|
2011-10-04 15:28:08 +00:00
|
|
|
// Return the Record that defined this class, or NULL if the class was
|
|
|
|
// created by TableGen.
|
|
|
|
Record *getDef() const { return TheDef; }
|
|
|
|
|
|
|
|
const std::string &getName() const { return Name; }
|
|
|
|
std::string getQualifiedName() const;
|
2013-03-17 17:26:09 +00:00
|
|
|
ArrayRef<MVT::SimpleValueType> getValueTypes() const {return VTs;}
|
2005-12-05 02:35:08 +00:00
|
|
|
unsigned getNumValueTypes() const { return VTs.size(); }
|
2011-03-11 01:19:05 +00:00
|
|
|
|
2009-08-11 20:47:22 +00:00
|
|
|
MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
|
2005-12-01 04:51:06 +00:00
|
|
|
if (VTNum < VTs.size())
|
|
|
|
return VTs[VTNum];
|
2012-02-05 07:21:30 +00:00
|
|
|
llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
|
2005-12-01 04:51:06 +00:00
|
|
|
}
|
2011-03-11 01:19:05 +00:00
|
|
|
|
2011-06-15 04:50:36 +00:00
|
|
|
// Return true if this this class contains the register.
|
|
|
|
bool contains(const CodeGenRegister*) const;
|
2011-03-11 01:19:05 +00:00
|
|
|
|
2011-06-15 04:50:36 +00:00
|
|
|
// Returns true if RC is a subclass.
|
2010-08-25 00:41:18 +00:00
|
|
|
// RC is a sub-class of this class if it is a valid replacement for any
|
2011-03-11 01:19:05 +00:00
|
|
|
// instruction operand where a register of this classis required. It must
|
2010-08-25 00:41:18 +00:00
|
|
|
// satisfy these conditions:
|
|
|
|
//
|
|
|
|
// 1. All RC registers are also in this.
|
|
|
|
// 2. The RC spill size must not be smaller than our spill size.
|
|
|
|
// 3. RC spill alignment must be compatible with ours.
|
|
|
|
//
|
2011-09-30 23:47:05 +00:00
|
|
|
bool hasSubClass(const CodeGenRegisterClass *RC) const {
|
|
|
|
return SubClasses.test(RC->EnumValue);
|
|
|
|
}
|
2010-08-25 00:41:18 +00:00
|
|
|
|
2011-10-05 00:35:49 +00:00
|
|
|
// getSubClassWithSubReg - Returns the largest sub-class where all
|
|
|
|
// registers have a SubIdx sub-register.
|
2012-01-31 20:57:55 +00:00
|
|
|
CodeGenRegisterClass*
|
|
|
|
getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
|
2011-10-05 00:35:49 +00:00
|
|
|
return SubClassWithSubReg.lookup(SubIdx);
|
|
|
|
}
|
|
|
|
|
2012-01-31 20:57:55 +00:00
|
|
|
void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx,
|
|
|
|
CodeGenRegisterClass *SubRC) {
|
2011-10-05 00:35:49 +00:00
|
|
|
SubClassWithSubReg[SubIdx] = SubRC;
|
|
|
|
}
|
|
|
|
|
2011-12-19 16:53:34 +00:00
|
|
|
// getSuperRegClasses - Returns a bit vector of all register classes
|
|
|
|
// containing only SubIdx super-registers of this class.
|
2012-01-31 20:57:55 +00:00
|
|
|
void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
|
2011-12-19 16:53:34 +00:00
|
|
|
|
|
|
|
// addSuperRegClass - Add a class containing only SudIdx super-registers.
|
2012-01-31 20:57:55 +00:00
|
|
|
void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
|
|
|
|
CodeGenRegisterClass *SuperRC) {
|
2011-12-19 16:53:34 +00:00
|
|
|
SuperRegClasses[SubIdx].insert(SuperRC);
|
|
|
|
}
|
|
|
|
|
2011-09-30 22:18:45 +00:00
|
|
|
// getSubClasses - Returns a constant BitVector of subclasses indexed by
|
|
|
|
// EnumValue.
|
|
|
|
// The SubClasses vector includs an entry for this class.
|
2011-10-11 19:53:40 +00:00
|
|
|
const BitVector &getSubClasses() const { return SubClasses; }
|
2011-09-30 22:18:45 +00:00
|
|
|
|
|
|
|
// getSuperClasses - Returns a list of super classes ordered by EnumValue.
|
|
|
|
// The array does not include an entry for this class.
|
|
|
|
ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
|
|
|
|
return SuperClasses;
|
|
|
|
}
|
|
|
|
|
2011-06-15 04:50:36 +00:00
|
|
|
// Returns an ordered list of class members.
|
|
|
|
// The order of registers is the same as in the .td file.
|
2011-06-18 00:50:49 +00:00
|
|
|
// No = 0 is the default allocation order, No = 1 is the first alternative.
|
|
|
|
ArrayRef<Record*> getOrder(unsigned No = 0) const {
|
2011-10-04 15:28:44 +00:00
|
|
|
return Orders[No];
|
2010-08-25 00:41:18 +00:00
|
|
|
}
|
2005-12-01 04:51:06 +00:00
|
|
|
|
2011-06-18 00:50:49 +00:00
|
|
|
// Return the total number of allocation orders available.
|
2011-10-04 15:28:44 +00:00
|
|
|
unsigned getNumOrders() const { return Orders.size(); }
|
2011-06-18 00:50:49 +00:00
|
|
|
|
2011-09-30 23:47:05 +00:00
|
|
|
// Get the set of registers. This set contains the same registers as
|
|
|
|
// getOrder(0).
|
|
|
|
const CodeGenRegister::Set &getMembers() const { return Members; }
|
|
|
|
|
2012-05-14 15:10:07 +00:00
|
|
|
// Get a bit vector of TopoSigs present in this register class.
|
|
|
|
const BitVector &getTopoSigs() const { return TopoSigs; }
|
|
|
|
|
2012-04-11 18:16:28 +00:00
|
|
|
// Populate a unique sorted list of units from a register set.
|
|
|
|
void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
|
|
|
|
|
2011-06-15 04:50:36 +00:00
|
|
|
CodeGenRegisterClass(CodeGenRegBank&, Record *R);
|
2011-09-30 00:10:40 +00:00
|
|
|
|
2011-10-04 15:28:49 +00:00
|
|
|
// A key representing the parts of a register class used for forming
|
|
|
|
// sub-classes. Note the ordering provided by this key is not the same as
|
|
|
|
// the topological order used for the EnumValues.
|
|
|
|
struct Key {
|
|
|
|
const CodeGenRegister::Set *Members;
|
|
|
|
unsigned SpillSize;
|
|
|
|
unsigned SpillAlignment;
|
|
|
|
|
|
|
|
Key(const Key &O)
|
|
|
|
: Members(O.Members),
|
|
|
|
SpillSize(O.SpillSize),
|
|
|
|
SpillAlignment(O.SpillAlignment) {}
|
|
|
|
|
|
|
|
Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0)
|
|
|
|
: Members(M), SpillSize(S), SpillAlignment(A) {}
|
|
|
|
|
|
|
|
Key(const CodeGenRegisterClass &RC)
|
|
|
|
: Members(&RC.getMembers()),
|
|
|
|
SpillSize(RC.SpillSize),
|
|
|
|
SpillAlignment(RC.SpillAlignment) {}
|
|
|
|
|
|
|
|
// Lexicographical order of (Members, SpillSize, SpillAlignment).
|
|
|
|
bool operator<(const Key&) const;
|
|
|
|
};
|
|
|
|
|
|
|
|
// Create a non-user defined register class.
|
2012-05-22 18:20:28 +00:00
|
|
|
CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
|
2011-10-04 15:28:49 +00:00
|
|
|
|
2011-09-30 00:10:40 +00:00
|
|
|
// Called by CodeGenRegBank::CodeGenRegBank().
|
2011-10-04 15:28:49 +00:00
|
|
|
static void computeSubClasses(CodeGenRegBank&);
|
2004-08-16 01:09:52 +00:00
|
|
|
};
|
2011-06-10 18:40:00 +00:00
|
|
|
|
2012-05-15 00:50:23 +00:00
|
|
|
// Register units are used to model interference and register pressure.
|
|
|
|
// Every register is assigned one or more register units such that two
|
|
|
|
// registers overlap if and only if they have a register unit in common.
|
|
|
|
//
|
|
|
|
// Normally, one register unit is created per leaf register. Non-leaf
|
|
|
|
// registers inherit the units of their sub-registers.
|
|
|
|
struct RegUnit {
|
|
|
|
// Weight assigned to this RegUnit for estimating register pressure.
|
|
|
|
// This is useful when equalizing weights in register classes with mixed
|
|
|
|
// register topologies.
|
|
|
|
unsigned Weight;
|
|
|
|
|
|
|
|
// Each native RegUnit corresponds to one or two root registers. The full
|
|
|
|
// set of registers containing this unit can be computed as the union of
|
|
|
|
// these two registers and their super-registers.
|
|
|
|
const CodeGenRegister *Roots[2];
|
|
|
|
|
2012-12-05 06:47:12 +00:00
|
|
|
// Index into RegClassUnitSets where we can find the list of UnitSets that
|
|
|
|
// contain this unit.
|
|
|
|
unsigned RegClassUnitSetsIdx;
|
|
|
|
|
|
|
|
RegUnit() : Weight(0), RegClassUnitSetsIdx(0) { Roots[0] = Roots[1] = 0; }
|
2012-05-15 00:50:23 +00:00
|
|
|
|
|
|
|
ArrayRef<const CodeGenRegister*> getRoots() const {
|
|
|
|
assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
|
|
|
|
return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]);
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2012-04-10 02:25:24 +00:00
|
|
|
// Each RegUnitSet is a sorted vector with a name.
|
|
|
|
struct RegUnitSet {
|
|
|
|
typedef std::vector<unsigned>::const_iterator iterator;
|
|
|
|
|
|
|
|
std::string Name;
|
|
|
|
std::vector<unsigned> Units;
|
|
|
|
};
|
|
|
|
|
2012-05-14 15:10:07 +00:00
|
|
|
// Base vector for identifying TopoSigs. The contents uniquely identify a
|
|
|
|
// TopoSig, only computeSuperRegs needs to know how.
|
|
|
|
typedef SmallVector<unsigned, 16> TopoSigId;
|
|
|
|
|
2011-06-10 18:40:00 +00:00
|
|
|
// CodeGenRegBank - Represent a target's registers and the relations between
|
|
|
|
// them.
|
|
|
|
class CodeGenRegBank {
|
2011-06-15 05:09:20 +00:00
|
|
|
SetTheory Sets;
|
|
|
|
|
2012-01-31 20:57:55 +00:00
|
|
|
// SubRegIndices.
|
|
|
|
std::vector<CodeGenSubRegIndex*> SubRegIndices;
|
|
|
|
DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
|
2012-08-15 18:00:55 +00:00
|
|
|
|
|
|
|
CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
|
2012-01-31 20:57:55 +00:00
|
|
|
|
Compute secondary sub-registers.
The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:
Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3]
But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.
This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.
This will eventually enable the coalescer to handle copies of skewed
sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 23:27:10 +00:00
|
|
|
typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>,
|
|
|
|
CodeGenSubRegIndex*> ConcatIdxMap;
|
|
|
|
ConcatIdxMap ConcatIdx;
|
|
|
|
|
2012-01-31 20:57:55 +00:00
|
|
|
// Registers.
|
2011-06-18 04:26:06 +00:00
|
|
|
std::vector<CodeGenRegister*> Registers;
|
2012-09-11 23:32:17 +00:00
|
|
|
StringMap<CodeGenRegister*> RegistersByName;
|
2011-06-11 00:28:06 +00:00
|
|
|
DenseMap<Record*, CodeGenRegister*> Def2Reg;
|
2012-04-10 02:25:21 +00:00
|
|
|
unsigned NumNativeRegUnits;
|
|
|
|
|
2012-05-14 15:10:07 +00:00
|
|
|
std::map<TopoSigId, unsigned> TopoSigs;
|
|
|
|
|
2012-05-15 00:50:23 +00:00
|
|
|
// Includes native (0..NumNativeRegUnits-1) and adopted register units.
|
|
|
|
SmallVector<RegUnit, 8> RegUnits;
|
2011-06-11 00:28:06 +00:00
|
|
|
|
2011-10-04 15:28:49 +00:00
|
|
|
// Register classes.
|
2011-09-29 22:28:37 +00:00
|
|
|
std::vector<CodeGenRegisterClass*> RegClasses;
|
2011-06-15 00:20:40 +00:00
|
|
|
DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
|
2011-10-04 15:28:49 +00:00
|
|
|
typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
|
|
|
|
RCKeyMap Key2RC;
|
|
|
|
|
2012-04-10 02:25:24 +00:00
|
|
|
// Remember each unique set of register units. Initially, this contains a
|
|
|
|
// unique set for each register class. Simliar sets are coalesced with
|
|
|
|
// pruneUnitSets and new supersets are inferred during computeRegUnitSets.
|
|
|
|
std::vector<RegUnitSet> RegUnitSets;
|
|
|
|
|
|
|
|
// Map RegisterClass index to the index of the RegUnitSet that contains the
|
|
|
|
// class's units and any inferred RegUnit supersets.
|
2012-12-05 06:47:12 +00:00
|
|
|
//
|
|
|
|
// NOTE: This could grow beyond the number of register classes when we map
|
|
|
|
// register units to lists of unit sets. If the list of unit sets does not
|
|
|
|
// already exist for a register class, we create a new entry in this vector.
|
2012-04-10 02:25:24 +00:00
|
|
|
std::vector<std::vector<unsigned> > RegClassUnitSets;
|
|
|
|
|
2011-10-04 15:28:49 +00:00
|
|
|
// Add RC to *2RC maps.
|
|
|
|
void addToMaps(CodeGenRegisterClass*);
|
|
|
|
|
2011-12-12 16:16:24 +00:00
|
|
|
// Create a synthetic sub-class if it is missing.
|
|
|
|
CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
|
|
|
|
const CodeGenRegister::Set *Membs,
|
|
|
|
StringRef Name);
|
|
|
|
|
2011-10-04 15:28:49 +00:00
|
|
|
// Infer missing register classes.
|
|
|
|
void computeInferredRegisterClasses();
|
2011-12-15 16:48:55 +00:00
|
|
|
void inferCommonSubClass(CodeGenRegisterClass *RC);
|
2011-12-16 00:12:05 +00:00
|
|
|
void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
|
2011-12-19 16:53:28 +00:00
|
|
|
void inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
|
|
|
|
unsigned FirstSubRegRC = 0);
|
2011-06-15 00:20:40 +00:00
|
|
|
|
2012-04-10 02:25:24 +00:00
|
|
|
// Iteratively prune unit sets.
|
|
|
|
void pruneUnitSets();
|
|
|
|
|
2012-04-10 02:25:21 +00:00
|
|
|
// Compute a weight for each register unit created during getSubRegs.
|
|
|
|
void computeRegUnitWeights();
|
|
|
|
|
2012-04-10 02:25:24 +00:00
|
|
|
// Create a RegUnitSet for each RegClass and infer superclasses.
|
|
|
|
void computeRegUnitSets();
|
|
|
|
|
2011-06-11 00:28:06 +00:00
|
|
|
// Populate the Composite map from sub-register relationships.
|
|
|
|
void computeComposites();
|
2011-06-10 18:40:00 +00:00
|
|
|
|
2012-09-11 16:34:08 +00:00
|
|
|
// Compute a lane mask for each sub-register index.
|
|
|
|
void computeSubRegIndexLaneMasks();
|
|
|
|
|
2011-06-10 18:40:00 +00:00
|
|
|
public:
|
|
|
|
CodeGenRegBank(RecordKeeper&);
|
|
|
|
|
2011-06-15 05:09:20 +00:00
|
|
|
SetTheory &getSets() { return Sets; }
|
|
|
|
|
2011-06-11 00:28:06 +00:00
|
|
|
// Sub-register indices. The first NumNamedIndices are defined by the user
|
|
|
|
// in the .td files. The rest are synthesized such that all sub-registers
|
|
|
|
// have a unique name.
|
2012-01-31 20:57:55 +00:00
|
|
|
ArrayRef<CodeGenSubRegIndex*> getSubRegIndices() { return SubRegIndices; }
|
2011-06-10 18:40:00 +00:00
|
|
|
|
2012-01-31 20:57:55 +00:00
|
|
|
// Find a SubRegIndex form its Record def.
|
|
|
|
CodeGenSubRegIndex *getSubRegIdx(Record*);
|
2011-06-10 18:40:00 +00:00
|
|
|
|
2011-06-11 00:28:06 +00:00
|
|
|
// Find or create a sub-register index representing the A+B composition.
|
2012-01-31 20:57:55 +00:00
|
|
|
CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
|
2012-01-31 21:44:11 +00:00
|
|
|
CodeGenSubRegIndex *B);
|
2011-06-11 00:28:06 +00:00
|
|
|
|
Compute secondary sub-registers.
The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:
Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3]
But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.
This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.
This will eventually enable the coalescer to handle copies of skewed
sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 23:27:10 +00:00
|
|
|
// Find or create a sub-register index representing the concatenation of
|
|
|
|
// non-overlapping sibling indices.
|
|
|
|
CodeGenSubRegIndex *
|
|
|
|
getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8>&);
|
|
|
|
|
|
|
|
void
|
|
|
|
addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8> &Parts,
|
|
|
|
CodeGenSubRegIndex *Idx) {
|
|
|
|
ConcatIdx.insert(std::make_pair(Parts, Idx));
|
|
|
|
}
|
|
|
|
|
2011-06-18 04:26:06 +00:00
|
|
|
const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
|
2012-09-11 23:32:17 +00:00
|
|
|
const StringMap<CodeGenRegister*> &getRegistersByName() {
|
|
|
|
return RegistersByName;
|
|
|
|
}
|
2011-06-11 00:28:06 +00:00
|
|
|
|
|
|
|
// Find a register from its Record def.
|
|
|
|
CodeGenRegister *getReg(Record*);
|
|
|
|
|
2012-04-10 02:25:21 +00:00
|
|
|
// Get a Register's index into the Registers array.
|
|
|
|
unsigned getRegIndex(const CodeGenRegister *Reg) const {
|
|
|
|
return Reg->EnumValue - 1;
|
|
|
|
}
|
|
|
|
|
2012-05-14 15:10:07 +00:00
|
|
|
// Return the number of allocated TopoSigs. The first TopoSig representing
|
|
|
|
// leaf registers is allocated number 0.
|
|
|
|
unsigned getNumTopoSigs() const {
|
|
|
|
return TopoSigs.size();
|
|
|
|
}
|
|
|
|
|
|
|
|
// Find or create a TopoSig for the given TopoSigId.
|
|
|
|
// This function is only for use by CodeGenRegister::computeSuperRegs().
|
|
|
|
// Others should simply use Reg->getTopoSig().
|
|
|
|
unsigned getTopoSig(const TopoSigId &Id) {
|
|
|
|
return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
|
|
|
|
}
|
|
|
|
|
2012-05-15 00:50:23 +00:00
|
|
|
// Create a native register unit that is associated with one or two root
|
|
|
|
// registers.
|
|
|
|
unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = 0) {
|
|
|
|
RegUnits.resize(RegUnits.size() + 1);
|
|
|
|
RegUnits.back().Roots[0] = R0;
|
|
|
|
RegUnits.back().Roots[1] = R1;
|
|
|
|
return RegUnits.size() - 1;
|
|
|
|
}
|
|
|
|
|
2012-04-10 02:25:21 +00:00
|
|
|
// Create a new non-native register unit that can be adopted by a register
|
|
|
|
// to increase its pressure. Note that NumNativeRegUnits is not increased.
|
|
|
|
unsigned newRegUnit(unsigned Weight) {
|
2012-05-15 00:50:23 +00:00
|
|
|
RegUnits.resize(RegUnits.size() + 1);
|
|
|
|
RegUnits.back().Weight = Weight;
|
|
|
|
return RegUnits.size() - 1;
|
2012-04-10 02:25:21 +00:00
|
|
|
}
|
|
|
|
|
2012-04-10 02:25:24 +00:00
|
|
|
// Native units are the singular unit of a leaf register. Register aliasing
|
|
|
|
// is completely characterized by native units. Adopted units exist to give
|
|
|
|
// register additional weight but don't affect aliasing.
|
2012-04-10 02:25:21 +00:00
|
|
|
bool isNativeUnit(unsigned RUID) {
|
|
|
|
return RUID < NumNativeRegUnits;
|
|
|
|
}
|
2012-03-31 01:35:59 +00:00
|
|
|
|
2012-05-29 23:40:00 +00:00
|
|
|
unsigned getNumNativeRegUnits() const {
|
|
|
|
return NumNativeRegUnits;
|
2012-05-30 09:13:49 +00:00
|
|
|
}
|
2012-05-29 23:40:00 +00:00
|
|
|
|
2012-05-15 00:50:23 +00:00
|
|
|
RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
|
|
|
|
const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
|
|
|
|
|
2011-09-29 22:28:37 +00:00
|
|
|
ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
|
2011-06-15 00:20:40 +00:00
|
|
|
return RegClasses;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Find a register class from its def.
|
|
|
|
CodeGenRegisterClass *getRegClass(Record*);
|
|
|
|
|
|
|
|
/// getRegisterClassForRegister - Find the register class that contains the
|
|
|
|
/// specified physical register. If the register is not in a register
|
|
|
|
/// class, return null. If the register is in multiple classes, and the
|
|
|
|
/// classes have a superset-subset relationship and the same set of types,
|
|
|
|
/// return the superclass. Otherwise return null.
|
|
|
|
const CodeGenRegisterClass* getRegClassForRegister(Record *R);
|
|
|
|
|
2012-04-11 18:16:28 +00:00
|
|
|
// Get the sum of unit weights.
|
|
|
|
unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
|
|
|
|
unsigned Weight = 0;
|
|
|
|
for (std::vector<unsigned>::const_iterator
|
|
|
|
I = Units.begin(), E = Units.end(); I != E; ++I)
|
2012-05-15 00:50:23 +00:00
|
|
|
Weight += getRegUnit(*I).Weight;
|
2012-04-11 18:16:28 +00:00
|
|
|
return Weight;
|
|
|
|
}
|
|
|
|
|
2012-04-10 02:25:24 +00:00
|
|
|
// Increase a RegUnitWeight.
|
2012-04-10 02:25:21 +00:00
|
|
|
void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
|
2012-05-15 00:50:23 +00:00
|
|
|
getRegUnit(RUID).Weight += Inc;
|
2012-04-10 02:25:21 +00:00
|
|
|
}
|
|
|
|
|
2012-04-10 02:25:24 +00:00
|
|
|
// Get the number of register pressure dimensions.
|
|
|
|
unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
|
|
|
|
|
|
|
|
// Get a set of register unit IDs for a given dimension of pressure.
|
|
|
|
RegUnitSet getRegPressureSet(unsigned Idx) const {
|
|
|
|
return RegUnitSets[Idx];
|
|
|
|
}
|
|
|
|
|
2012-12-05 06:47:12 +00:00
|
|
|
// The number of pressure set lists may be larget than the number of
|
|
|
|
// register classes if some register units appeared in a list of sets that
|
|
|
|
// did not correspond to an existing register class.
|
|
|
|
unsigned getNumRegClassPressureSetLists() const {
|
|
|
|
return RegClassUnitSets.size();
|
|
|
|
}
|
|
|
|
|
2012-04-10 02:25:24 +00:00
|
|
|
// Get a list of pressure set IDs for a register class. Liveness of a
|
|
|
|
// register in this class impacts each pressure set in this list by the
|
|
|
|
// weight of the register. An exact solution requires all registers in a
|
|
|
|
// class to have the same class, but it is not strictly guaranteed.
|
|
|
|
ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
|
|
|
|
return RegClassUnitSets[RCIdx];
|
|
|
|
}
|
|
|
|
|
2011-06-11 00:28:06 +00:00
|
|
|
// Computed derived records such as missing sub-register indices.
|
|
|
|
void computeDerivedInfo();
|
2011-06-12 03:05:52 +00:00
|
|
|
|
2012-01-17 22:46:58 +00:00
|
|
|
// Compute the set of registers completely covered by the registers in Regs.
|
|
|
|
// The returned BitVector will have a bit set for each register in Regs,
|
|
|
|
// all sub-registers, and all super-registers that are covered by the
|
|
|
|
// registers in Regs.
|
|
|
|
//
|
|
|
|
// This is used to compute the mask of call-preserved registers from a list
|
|
|
|
// of callee-saves.
|
|
|
|
BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
|
2013-05-16 18:03:08 +00:00
|
|
|
|
|
|
|
// Bit mask of lanes that cover their registers. A sub-register index whose
|
|
|
|
// LaneMask is contained in CoveringLanes will be completely covered by
|
|
|
|
// another sub-register with the same or larger lane mask.
|
|
|
|
unsigned CoveringLanes;
|
2011-06-10 18:40:00 +00:00
|
|
|
};
|
2004-08-16 01:09:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|