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llvm-6502/lib/Target/X86/X86InstrInfo.def

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Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 22:55:53 +00:00
//===-- X86InstructionInfo.def - X86 Instruction Information ----*- C++ -*-===//
//
// This file describes all of the instructions that the X86 backend uses. It
// relys on an external 'I' macro being defined that takes the arguments
// specified below, and is used to make all of the information relevant to an
// instruction be in one place.
//
Set the destination register field based on the target specific flags git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4442 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-30 01:15:31 +00:00
// Note that X86 Instructions always have the destination register listed as
// operand 0, unless it does not produce a value (in which case the TSFlags will
// include X86II::Void).
//
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 22:55:53 +00:00
//===----------------------------------------------------------------------===//
// NOTE: No include guards desired
#ifndef I
#errror "Must define I macro before including X86/X86InstructionInfo.def!"
#endif
* Move information about Implicit Defs/Uses into X86InstrInfo.def. * Expose information about implicit defs/uses of register through the MachineInstrInfo.h file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4877 91177308-0d34-0410-b5e6-96231b3b80d8
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// Macro to handle the implicit register uses lists...
#ifndef IMPREGSLIST
#define IMPREGSLIST(NAME, ...)
#endif
// Implicit register usage info: O_ is for one register, T_ is for two registers
Target/X86/Printer.cpp: Add sizePtr function, and use it instead of " <SIZE> PTR " string when emitting assembly. Target/X86/X86InstrInfo.def: Tidy up a bit: Squashed everything down to 118 chars wide, wrapping lines so that comment is at the same point on each line. Rename "NoImpRegs" as "NoIR". (most instructions have NoImpRegs twice on a line, so this saves 10 columns). Also, annotate various instructions with flags for size of memory operand. (MemArg16, MemArg32, MemArg64, etc.) Target/X86/X86InstrInfo.h: Define flags for size of memory operand. (MemArg16, MemArg32, MemArg64, etc.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4932 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-05 08:30:40 +00:00
// NoIR means the instruction does not use implicit registers, in this form.
Add reg clobber list for direct calls Represent empty use/def list as a null pointer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5101 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-18 01:05:31 +00:00
#define NoIR 0
Target/X86/Printer.cpp: Add sizePtr function, and use it instead of " <SIZE> PTR " string when emitting assembly. Target/X86/X86InstrInfo.def: Tidy up a bit: Squashed everything down to 118 chars wide, wrapping lines so that comment is at the same point on each line. Rename "NoImpRegs" as "NoIR". (most instructions have NoImpRegs twice on a line, so this saves 10 columns). Also, annotate various instructions with flags for size of memory operand. (MemArg16, MemArg32, MemArg64, etc.) Target/X86/X86InstrInfo.h: Define flags for size of memory operand. (MemArg16, MemArg32, MemArg64, etc.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4932 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-05 08:30:40 +00:00
IMPREGSLIST(O_AL , X86::AL , 0)
IMPREGSLIST(O_AH , X86::AH , 0)
IMPREGSLIST(O_CL , X86::CL , 0)
IMPREGSLIST(O_AX , X86::AX , 0)
IMPREGSLIST(O_DX , X86::DX , 0)
IMPREGSLIST(O_EAX, X86::EAX, 0)
IMPREGSLIST(O_EDX, X86::EDX, 0)
IMPREGSLIST(O_EBP, X86::EBP, 0)
IMPREGSLIST(T_AXDX , X86::AX , X86::DX , 0)
IMPREGSLIST(T_EAXEDX, X86::EAX, X86::EDX, 0)
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
IMPREGSLIST(C_CLOBBER, X86::EAX, X86::ECX, X86::EDX,
X86::FP0, X86::FP1, X86::FP2, X86::FP3,
X86::FP4, X86::FP5, X86::FP6, 0) // Callee clobber regs
// Floating point registers...
IMPREGSLIST(O_ST0, X86::ST0, 0)
//IMPREGSLIST(O_TOP, X86::TOP, 0)
* Move information about Implicit Defs/Uses into X86InstrInfo.def. * Expose information about implicit defs/uses of register through the MachineInstrInfo.h file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4877 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-03 05:42:53 +00:00
#undef IMPREGSLIST
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 22:55:53 +00:00
// Arguments to be passed into the I macro
// #1: Enum name - This ends up being the opcode symbol in the X86 namespace
RECAPITALIZE all the names of pseudo-instructions, and add a comment explaining the convention. :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6791 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:41:13 +00:00
// #2: Opcode name, as used by the Intel assembler. This should be in
// ALL CAPS for pseudo-instructions (which the assembler should never
// see), or all lowercase for real instructions (which the assembler
// should see).
Start to add more information to instr.def git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4741 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-18 05:37:11 +00:00
// #3: The base opcode for the instruction
// #4: Instruction Flags - This should be a field or'd together that contains
Rename MachineInstrInfo -> TargetInstrInfo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5272 91177308-0d34-0410-b5e6-96231b3b80d8
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// constants from the TargetInstrInfo.h file.
Start to add more information to instr.def git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4741 91177308-0d34-0410-b5e6-96231b3b80d8
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// #5: Target Specific Flags - Another bitfield containing X86 specific flags
Add flag to specify when no value is produced by an instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4441 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-30 01:09:34 +00:00
// that we are interested in for each instruction. These should be flags
// defined in X86InstrInfo.h in the X86II namespace.
* Move information about Implicit Defs/Uses into X86InstrInfo.def. * Expose information about implicit defs/uses of register through the MachineInstrInfo.h file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4877 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-03 05:42:53 +00:00
// #6: Name of the implicit register uses list
// #7: Name of the implicit register definitions list
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 22:55:53 +00:00
//
Set the void flag on instructions that should get it git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4738 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-18 01:34:36 +00:00
// The first instruction must always be the PHI instruction:
RECAPITALIZE all the names of pseudo-instructions, and add a comment explaining the convention. :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6791 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:41:13 +00:00
I(PHI , "PHI", 0, 0, X86II::Pseudo , NoIR, NoIR)
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 22:55:53 +00:00
Set the void flag on instructions that should get it git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4738 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-18 01:34:36 +00:00
// The second instruction must always be the noop instruction:
* Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5183 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:29:14 +00:00
I(NOOP , "nop", 0x90, 0, X86II::RawFrm | X86II::Void, NoIR, NoIR) // nop
// This "instruction" is really an annotation which indicates that a specified
// amount of stack space is needed for an outgoing function call. This
// instruction is found before any of the stores to the argument slots, which
// use direct ESP references. If the frame pointer is eliminated, this
// instruction turns into a noop, but if the frame pointer is retained, this
// turns into a 'sub ESP, <amount>'.
//
RECAPITALIZE all the names of pseudo-instructions, and add a comment explaining the convention. :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6791 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:41:13 +00:00
I(ADJCALLSTACKDOWN, "ADJCALLSTACKDOWN", 0, 0, X86II::Pseudo, NoIR, NoIR)
* Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5183 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:29:14 +00:00
// This instruction is used to mark readjustment of the stack after a function
// call. If the frame pointer is retained, this becomes a 'add ESP, <amount>'
// instruction after the call.
RECAPITALIZE all the names of pseudo-instructions, and add a comment explaining the convention. :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6791 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:41:13 +00:00
I(ADJCALLSTACKUP , "ADJCALLSTACKUP" , 0, 0, X86II::Pseudo, NoIR, NoIR)
Add two new pseudo instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6008 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-06 21:31:31 +00:00
// This pseudo-instruction is used to record implicit uses of physical registers
// at the end of the function. This ensures that bad things aren't done to
// registes that are live on exit from the function (for example, EAX).
//
RECAPITALIZE all the names of pseudo-instructions, and add a comment explaining the convention. :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6791 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:41:13 +00:00
I(IMPLICIT_USE, "IMPLICIT_USE", 0, 0, X86II::Pseudo, NoIR, NoIR)
Add two new pseudo instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6008 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-06 21:31:31 +00:00
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 22:55:53 +00:00
Implement unconditional branching support git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4498 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-02 19:27:56 +00:00
// Flow control instructions
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(RET , "ret", 0xC3, M_RET_FLAG | M_TERMINATOR_FLAG, X86II::RawFrm | X86II::Void, NoIR, NoIR) // ret
Add more flavors of branch instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5323 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-16 16:42:45 +00:00
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(JMP , "jmp", 0xE9, M_BRANCH_FLAG | M_TERMINATOR_FLAG, X86II::RawFrm | X86II::Void, NoIR, NoIR) // jmp foo
Add more flavors of branch instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5323 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-16 16:42:45 +00:00
I(JB , "jb" , 0x82, M_BRANCH_FLAG | M_TERMINATOR_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // jne foo
I(JAE , "jae", 0x83, M_BRANCH_FLAG | M_TERMINATOR_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // jne foo
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(JE , "je", 0x84, M_BRANCH_FLAG | M_TERMINATOR_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // je foo
Add more flavors of branch instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5323 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-16 16:42:45 +00:00
I(JNE , "jne", 0x85, M_BRANCH_FLAG | M_TERMINATOR_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // jne foo
I(JBE , "jbe", 0x86, M_BRANCH_FLAG | M_TERMINATOR_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // jne foo
I(JA , "ja" , 0x87, M_BRANCH_FLAG | M_TERMINATOR_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // jne foo
I(JL , "jl" , 0x8C, M_BRANCH_FLAG | M_TERMINATOR_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // jne foo
I(JGE , "jge", 0x8D, M_BRANCH_FLAG | M_TERMINATOR_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // jne foo
I(JLE , "jle", 0x8E, M_BRANCH_FLAG | M_TERMINATOR_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // jne foo
I(JG , "jg" , 0x8F, M_BRANCH_FLAG | M_TERMINATOR_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // jne foo
* Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5183 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:29:14 +00:00
I(CALLpcrel32 , "call", 0xE8, M_CALL_FLAG, X86II::Void | X86II::RawFrm, NoIR, C_CLOBBER) // call pc+42
I(CALLr32 , "call", 0xFF, M_CALL_FLAG, X86II::Void | X86II::MRMS2r | X86II::Arg32,
NoIR, C_CLOBBER) // call [r32]
I(CALLm32 , "call", 0xFF, M_CALL_FLAG, X86II::Void | X86II::MRMS2m | X86II::Arg32,
NoIR, C_CLOBBER) // call [m32]
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 22:55:53 +00:00
Add load/store instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4711 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-17 20:33:12 +00:00
// Misc instructions
* Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5183 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:29:14 +00:00
I(LEAVE , "leave", 0xC9, 0, X86II::RawFrm , O_EBP, O_EBP) // leave
I(BSWAPr32 , "bswap", 0xC8, M_2_ADDR_FLAG, X86II::AddRegFrm | X86II::Arg32 | X86II::TB , NoIR, NoIR) // R32 = bswap R32
I(XCHGrr8 , "xchg" , 0x86, 0, X86II::MRMDestReg | X86II::Arg8 , NoIR, NoIR) // xchg(R8, R8)
* Use new pseudo instr form for instructions * Mark CALLpcrel as a RawFrm instruction as required * Eliminate invalid BSWAP16 instruction * Add xchg instructions * Add initial support for FP instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5153 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-25 05:11:46 +00:00
I(XCHGrr16 , "xchg" , 0x87, 0, X86II::MRMDestReg | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // xchg(R16, R16)
* Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5183 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:29:14 +00:00
I(XCHGrr32 , "xchg" , 0x87, 0, X86II::MRMDestReg | X86II::Arg32 , NoIR, NoIR) // xchg(R32, R32)
I(LEAr16 , "lea" , 0x8D, 0, X86II::MRMSrcMem | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // R16 = lea [mem]
I(LEAr32 , "lea" , 0x8D, 0, X86II::MRMSrcMem | X86II::Arg32 , NoIR, NoIR) // R32 = lea [mem]
Add load/store instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4711 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-17 20:33:12 +00:00
Add instruction definitions for mov r, imm instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4296 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-27 21:16:44 +00:00
// Move instructions
* Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5183 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:29:14 +00:00
I(MOVrr8 , "mov", 0x88, 0, X86II::MRMDestReg, NoIR, NoIR) // R8 = R8
I(MOVrr16 , "mov", 0x89, 0, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 = R16
I(MOVrr32 , "mov", 0x89, 0, X86II::MRMDestReg, NoIR, NoIR) // R32 = R32
I(MOVir8 , "mov", 0xB0, 0, X86II::AddRegFrm | X86II::Arg8, NoIR, NoIR) // R8 = imm8
I(MOVir16 , "mov", 0xB8, 0, X86II::AddRegFrm | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // R16 = imm16
I(MOVir32 , "mov", 0xB8, 0, X86II::AddRegFrm | X86II::Arg32, NoIR, NoIR) // R32 = imm32
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(MOVim8 , "mov", 0xC6, 0, X86II::MRMS0m | X86II::Arg8, NoIR, NoIR) // [mem] = imm8
I(MOVim16 , "mov", 0xC7, 0, X86II::MRMS0m | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // [mem] = imm16
I(MOVim32 , "mov", 0xC7, 0, X86II::MRMS0m | X86II::Arg32, NoIR, NoIR) // [mem] = imm32
* Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5183 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:29:14 +00:00
I(MOVmr8 , "mov", 0x8A, 0, X86II::MRMSrcMem | X86II::Arg8, NoIR, NoIR) // R8 = [mem]
I(MOVmr16 , "mov", 0x8B, 0, X86II::MRMSrcMem | X86II::OpSize |
X86II::Arg16, NoIR, NoIR) // R16 = [mem]
I(MOVmr32 , "mov", 0x8B, 0, X86II::MRMSrcMem | X86II::Arg32, NoIR, NoIR)// R32 = [mem]
I(MOVrm8 , "mov", 0x88, 0, X86II::MRMDestMem | X86II::Void |
X86II::Arg8, NoIR, NoIR) // [mem] = R8
I(MOVrm16 , "mov", 0x89, 0, X86II::MRMDestMem | X86II::Void |
X86II::OpSize | X86II::Arg16, NoIR, NoIR) // [mem] = R16
I(MOVrm32 , "mov", 0x89, 0, X86II::MRMDestMem | X86II::Void |
X86II::Arg32, NoIR, NoIR) // [mem] = R32
Add instruction definitions for mov r, imm instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4296 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-27 21:16:44 +00:00
// Arithmetic instructions
* Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5183 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:29:14 +00:00
I(ADDrr8 , "add", 0x00, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 += R8
I(ADDrr16 , "add", 0x01, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 += R16
Add instructions for (add|sub|and|or|xor)ri(8|16|32) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6625 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-05 18:25:08 +00:00
I(ADDrr32 , "add", 0x01, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::Arg32, NoIR, NoIR) // R32 += R32
I(ADDri8 , "add", 0x80, M_2_ADDR_FLAG, X86II::MRMS0r | X86II::Arg8, NoIR, NoIR) // R8 += imm8
I(ADDri16 , "add", 0x81, M_2_ADDR_FLAG, X86II::MRMS0r | X86II::OpSize | X86II::Arg16, NoIR, NoIR) // R16 += imm16
I(ADDri32 , "add", 0x81, M_2_ADDR_FLAG, X86II::MRMS0r | X86II::Arg32, NoIR, NoIR) // R32 += imm32
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(ADCrr32 , "adc", 0x11, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::Arg32, NoIR, NoIR) // R32 += R32 + Carry
* Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5183 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:29:14 +00:00
I(SUBrr8 , "sub", 0x28, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 -= R8
I(SUBrr16 , "sub", 0x29, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 -= R16
I(SUBrr32 , "sub", 0x29, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 -= R32
Add instructions for (add|sub|and|or|xor)ri(8|16|32) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6625 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-05 18:25:08 +00:00
I(SUBri8 , "sub", 0x80, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg8 , NoIR, NoIR) // R8 -= imm8
I(SUBri16 , "sub", 0x81, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::OpSize | X86II::Arg16, NoIR, NoIR) // R16 -= imm16
* Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5183 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:29:14 +00:00
I(SUBri32 , "sub", 0x81, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg32, NoIR, NoIR) // R32 -= imm32
Add instructions for (add|sub|and|or|xor)ri(8|16|32) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6625 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-05 18:25:08 +00:00
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(SBBrr32 , "sbb", 0x19, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::Arg32, NoIR, NoIR) // R32 -= R32 + Carry
Add instructions for (add|sub|and|or|xor)ri(8|16|32) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6625 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-05 18:25:08 +00:00
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(MULr8 , "mul", 0xF6, 0, X86II::MRMS4r | X86II::Void, O_AL, O_AX) // AX = AL*R8
I(MULr16 , "mul", 0xF7, 0, X86II::MRMS4r | X86II::Void | // DX:AX= AX*R16
Add IMULr16 & IMULr32 instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6829 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-21 17:13:35 +00:00
X86II::OpSize, O_AX, T_AXDX)
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(MULr32 , "mul", 0xF7, 0, X86II::MRMS4r | X86II::Void, O_EAX, T_EAXEDX) // ED:EA= EA*R32
Implement multiply operator git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4506 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-02 20:28:58 +00:00
Add IMULr16 & IMULr32 instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6829 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-21 17:13:35 +00:00
I(IMULr16 , "imul", 0xAF, M_2_ADDR_FLAG, X86II::MRMSrcReg | X86II::TB | // R16 *= R16
X86II::OpSize, NoIR, NoIR)
I(IMULr32 , "imul", 0xAF, M_2_ADDR_FLAG, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 *= R32
Implement signed and unsigned division and remainder git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4508 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-02 20:54:46 +00:00
// unsigned division/remainder
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(DIVr8 , "div", 0xF6, 0, X86II::MRMS6r | X86II::Void, O_AX, O_AX) // AX/r8= AL&AH
I(DIVr16 , "div", 0xF7, 0, X86II::MRMS6r | X86II::Void | // ED:EA/r16=AX&DX
Add IMULr16 & IMULr32 instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6829 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-21 17:13:35 +00:00
X86II::OpSize, T_AXDX, T_AXDX)
I(DIVr32 , "div", 0xF7, 0, X86II::MRMS6r | X86II::Void, T_EAXEDX,T_EAXEDX)// ED:EA/r32=EA&ED
Implement signed and unsigned division and remainder git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4508 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-02 20:54:46 +00:00
// signed division/remainder
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(IDIVr8 , "idiv", 0xF6, 0, X86II::MRMS7r | X86II::Void, O_AX, O_AX) // AX/r8= AL&AH
I(IDIVr16 , "idiv", 0xF7, 0, X86II::MRMS7r | X86II::Void | // DA/r16=AX&DX
Add IMULr16 & IMULr32 instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6829 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-21 17:13:35 +00:00
X86II::OpSize, T_AXDX, T_AXDX)
I(IDIVr32 , "idiv", 0xF7, 0, X86II::MRMS7r | X86II::Void, T_EAXEDX,T_EAXEDX)// DA/r32=EAX&DX
Implement signed and unsigned division and remainder git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4508 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-02 20:54:46 +00:00
shuffle code around a bit, implement and, or, xor git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4502 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-02 20:04:26 +00:00
// Logical operators
* Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5183 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:29:14 +00:00
I(ANDrr8 , "and", 0x20, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 &= R8
I(ANDrr16 , "and", 0x21, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 &= R16
I(ANDrr32 , "and", 0x21, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 &= R32
Add instructions for (add|sub|and|or|xor)ri(8|16|32) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6625 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-05 18:25:08 +00:00
I(ANDri8 , "and", 0x80, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg8 , NoIR, NoIR) // R8 &= imm8
I(ANDri16 , "and", 0x81, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // R16 &= imm16
* Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5183 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:29:14 +00:00
I(ANDri32 , "and", 0x81, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg32, NoIR, NoIR) // R32 &= imm32
Add instructions for (add|sub|and|or|xor)ri(8|16|32) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6625 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-05 18:25:08 +00:00
* Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5183 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:29:14 +00:00
I(ORrr8 , "or", 0x08, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 |= R8
I(ORrr16 , "or", 0x09, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 |= R16
I(ORrr32 , "or", 0x09, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 |= R32
Add instructions for (add|sub|and|or|xor)ri(8|16|32) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6625 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-05 18:25:08 +00:00
I(ORri8 , "or", 0x80, M_2_ADDR_FLAG, X86II::MRMS1r | X86II::Arg8 , NoIR, NoIR) // R8 |= imm8
I(ORri16 , "or", 0x81, M_2_ADDR_FLAG, X86II::MRMS1r | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // R16 |= imm16
I(ORri32 , "or", 0x81, M_2_ADDR_FLAG, X86II::MRMS1r | X86II::Arg32, NoIR, NoIR) // R32 |= imm32
* Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5183 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:29:14 +00:00
I(XORrr8 , "xor", 0x30, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 ^= R8
I(XORrr16 , "xor", 0x31, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 ^= R16
I(XORrr32 , "xor", 0x31, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 ^= R32
Add instructions for (add|sub|and|or|xor)ri(8|16|32) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6625 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-05 18:25:08 +00:00
I(XORri8 , "xor", 0x80, M_2_ADDR_FLAG, X86II::MRMS6r | X86II::Arg8 , NoIR, NoIR) // R8 ^= imm8
I(XORri16 , "xor", 0x81, M_2_ADDR_FLAG, X86II::MRMS6r | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // R16 ^= imm16
I(XORri32 , "xor", 0x81, M_2_ADDR_FLAG, X86II::MRMS6r | X86II::Arg32, NoIR, NoIR) // R32 ^= imm32
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 22:55:53 +00:00
Add definitions for TEST instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6498 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-01 01:56:39 +00:00
// test instructions are just like and, except they don't generate a result (but
// they do set flags).
I(TESTri8 , "test", 0xF6, 0, X86II::MRMS0r | X86II::Arg8, NoIR, NoIR) // flags = R8 & imm8
I(TESTri16 , "test", 0xF7, 0, X86II::MRMS0r | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // flags = R16 & imm16
I(TESTri32 , "test", 0xF7, 0, X86II::MRMS0r | X86II::Arg32, NoIR, NoIR) // flags = R32 & imm32
Add RR forms of test instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6509 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-01 03:37:46 +00:00
I(TESTrr8 , "test", 0x84, 0, X86II::MRMDestReg | X86II::Arg8, NoIR, NoIR) // flags = R8 & R8
I(TESTrr16 , "test", 0x85, 0, X86II::MRMDestReg | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // flags = R16 & R16
I(TESTrr32 , "test", 0x85, 0, X86II::MRMDestReg | X86II::Arg32, NoIR, NoIR) // flags = R32 & R32
Add definitions for TEST instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6498 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-01 01:56:39 +00:00
InstSelectSimple.cpp: Include llvm/iOther.h for ShiftInst. Add ISel::visitShiftInst() to instruction select shift instructions. Add a comment in visitAdd about how to do 64 bit adds. X86InstrInfo.def: Add register-to-register move opcodes and shift opcodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4477 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-31 23:03:59 +00:00
// Shift instructions
Nice tasty llc fixes. These should fix LLC for x86 for everything in SingleSource except oopack and Oscar. (Sorry, Oscar.) include/llvm/Target/TargetInstrInfo.h: Remove virtual print method. Add accessors for ImplicitUses/Defs. lib/Target/TargetInstrInfo.cpp: Remove virtual print method. If you really wanted this, just use MI->print(O, TM); instead... lib/Target/X86: FloatingPoint.cpp: ...like this. X86InstrInfo.h: Remove virtual print method. Define the PrintImplUses target-specific flag bit. X86InstrInfo.def: Add the PrintImplUses flag to all the instructions which implicitly use CL, because the assembler needs to see the CL in order to generate the right instruction. Printer.cpp: Ditch fnIndex at Chris's request. Now we use CurrentFnName to name constants in the constant pool for each function instead. This avoids keeping state between runOnMachineFunction() invocations, which is a no-no. Having MangledGlobals be global is a bogon I'd like to get rid of too, but making it a static member of Printer causes link errors (why???). Make NumberForBB into a member of Printer instead of a global, too. Make printOp and printMemReference into methods of Printer. X86InstrInfo::print is now Printer::printMachineInstruction, because TargetInstrInfo::print is history. (Because of this, we have to qualify the names of some TargetInstrInfo methods we call.) Print out the ImplicitUses field of any instruction we print that has the PrintImplUses bit set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6924 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-27 00:00:48 +00:00
I(SHLrr8 , "shl", 0xD2, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::PrintImplUses, O_CL, NoIR) // R8 <<= cl
I(SHLrr16 , "shl", 0xD3, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::OpSize | X86II::PrintImplUses, O_CL, NoIR) // R16 <<= cl
I(SHLrr32 , "shl", 0xD3, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::PrintImplUses, O_CL, NoIR) // R32 <<= cl
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(SHLir8 , "shl", 0xC0, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg8, NoIR, NoIR) // R8 <<= imm8
I(SHLir16 , "shl", 0xC1, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg8 | X86II::OpSize, NoIR, NoIR) // R16 <<= imm8
I(SHLir32 , "shl", 0xC1, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg8, NoIR, NoIR) // R32 <<= imm8
Nice tasty llc fixes. These should fix LLC for x86 for everything in SingleSource except oopack and Oscar. (Sorry, Oscar.) include/llvm/Target/TargetInstrInfo.h: Remove virtual print method. Add accessors for ImplicitUses/Defs. lib/Target/TargetInstrInfo.cpp: Remove virtual print method. If you really wanted this, just use MI->print(O, TM); instead... lib/Target/X86: FloatingPoint.cpp: ...like this. X86InstrInfo.h: Remove virtual print method. Define the PrintImplUses target-specific flag bit. X86InstrInfo.def: Add the PrintImplUses flag to all the instructions which implicitly use CL, because the assembler needs to see the CL in order to generate the right instruction. Printer.cpp: Ditch fnIndex at Chris's request. Now we use CurrentFnName to name constants in the constant pool for each function instead. This avoids keeping state between runOnMachineFunction() invocations, which is a no-no. Having MangledGlobals be global is a bogon I'd like to get rid of too, but making it a static member of Printer causes link errors (why???). Make NumberForBB into a member of Printer instead of a global, too. Make printOp and printMemReference into methods of Printer. X86InstrInfo::print is now Printer::printMachineInstruction, because TargetInstrInfo::print is history. (Because of this, we have to qualify the names of some TargetInstrInfo methods we call.) Print out the ImplicitUses field of any instruction we print that has the PrintImplUses bit set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6924 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-27 00:00:48 +00:00
I(SHRrr8 , "shr", 0xD2, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::PrintImplUses, O_CL, NoIR) // R8 >>>= cl
I(SHRrr16 , "shr", 0xD3, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::OpSize | X86II::PrintImplUses, O_CL, NoIR) // R16 >>>= cl
I(SHRrr32 , "shr", 0xD3, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::PrintImplUses, O_CL, NoIR) // R32 >>>= cl
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(SHRir8 , "shr", 0xC0, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg8, NoIR, NoIR) // R8 >>>= imm8
I(SHRir16 , "shr", 0xC1, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg8 | X86II::OpSize, NoIR, NoIR) // R16 >>>= imm8
I(SHRir32 , "shr", 0xC1, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg8, NoIR, NoIR) // R32 >>>= imm8
Nice tasty llc fixes. These should fix LLC for x86 for everything in SingleSource except oopack and Oscar. (Sorry, Oscar.) include/llvm/Target/TargetInstrInfo.h: Remove virtual print method. Add accessors for ImplicitUses/Defs. lib/Target/TargetInstrInfo.cpp: Remove virtual print method. If you really wanted this, just use MI->print(O, TM); instead... lib/Target/X86: FloatingPoint.cpp: ...like this. X86InstrInfo.h: Remove virtual print method. Define the PrintImplUses target-specific flag bit. X86InstrInfo.def: Add the PrintImplUses flag to all the instructions which implicitly use CL, because the assembler needs to see the CL in order to generate the right instruction. Printer.cpp: Ditch fnIndex at Chris's request. Now we use CurrentFnName to name constants in the constant pool for each function instead. This avoids keeping state between runOnMachineFunction() invocations, which is a no-no. Having MangledGlobals be global is a bogon I'd like to get rid of too, but making it a static member of Printer causes link errors (why???). Make NumberForBB into a member of Printer instead of a global, too. Make printOp and printMemReference into methods of Printer. X86InstrInfo::print is now Printer::printMachineInstruction, because TargetInstrInfo::print is history. (Because of this, we have to qualify the names of some TargetInstrInfo methods we call.) Print out the ImplicitUses field of any instruction we print that has the PrintImplUses bit set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6924 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-27 00:00:48 +00:00
I(SARrr8 , "sar", 0xD2, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::PrintImplUses, O_CL, NoIR) // R8 >>= cl
I(SARrr16 , "sar", 0xD3, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::OpSize | X86II::PrintImplUses, O_CL, NoIR) // R16 >>= cl
I(SARrr32 , "sar", 0xD3, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::PrintImplUses, O_CL, NoIR) // R32 >>= cl
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(SARir8 , "sar", 0xC0, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::Arg8, NoIR, NoIR) // R8 >>= imm8
I(SARir16 , "sar", 0xC1, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::Arg8 | X86II::OpSize, NoIR, NoIR) // R16 >>= imm8
I(SARir32 , "sar", 0xC1, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::Arg8, NoIR, NoIR) // R32 >>= imm8
I(SHLDir32 , "shld", 0xA4, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::TB | X86II::Arg8, NoIR, NoIR) // R32 >>= R32,R32 imm8
Nice tasty llc fixes. These should fix LLC for x86 for everything in SingleSource except oopack and Oscar. (Sorry, Oscar.) include/llvm/Target/TargetInstrInfo.h: Remove virtual print method. Add accessors for ImplicitUses/Defs. lib/Target/TargetInstrInfo.cpp: Remove virtual print method. If you really wanted this, just use MI->print(O, TM); instead... lib/Target/X86: FloatingPoint.cpp: ...like this. X86InstrInfo.h: Remove virtual print method. Define the PrintImplUses target-specific flag bit. X86InstrInfo.def: Add the PrintImplUses flag to all the instructions which implicitly use CL, because the assembler needs to see the CL in order to generate the right instruction. Printer.cpp: Ditch fnIndex at Chris's request. Now we use CurrentFnName to name constants in the constant pool for each function instead. This avoids keeping state between runOnMachineFunction() invocations, which is a no-no. Having MangledGlobals be global is a bogon I'd like to get rid of too, but making it a static member of Printer causes link errors (why???). Make NumberForBB into a member of Printer instead of a global, too. Make printOp and printMemReference into methods of Printer. X86InstrInfo::print is now Printer::printMachineInstruction, because TargetInstrInfo::print is history. (Because of this, we have to qualify the names of some TargetInstrInfo methods we call.) Print out the ImplicitUses field of any instruction we print that has the PrintImplUses bit set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6924 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-27 00:00:48 +00:00
I(SHLDrr32 , "shld", 0xA5, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::TB | X86II::PrintImplUses, O_CL, NoIR) // R32 >>= R32,R32 cl
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(SHRDir32 , "shrd", 0xAC, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::TB | X86II::Arg8, NoIR, NoIR) // R32 >>= R32,R32 imm8
Nice tasty llc fixes. These should fix LLC for x86 for everything in SingleSource except oopack and Oscar. (Sorry, Oscar.) include/llvm/Target/TargetInstrInfo.h: Remove virtual print method. Add accessors for ImplicitUses/Defs. lib/Target/TargetInstrInfo.cpp: Remove virtual print method. If you really wanted this, just use MI->print(O, TM); instead... lib/Target/X86: FloatingPoint.cpp: ...like this. X86InstrInfo.h: Remove virtual print method. Define the PrintImplUses target-specific flag bit. X86InstrInfo.def: Add the PrintImplUses flag to all the instructions which implicitly use CL, because the assembler needs to see the CL in order to generate the right instruction. Printer.cpp: Ditch fnIndex at Chris's request. Now we use CurrentFnName to name constants in the constant pool for each function instead. This avoids keeping state between runOnMachineFunction() invocations, which is a no-no. Having MangledGlobals be global is a bogon I'd like to get rid of too, but making it a static member of Printer causes link errors (why???). Make NumberForBB into a member of Printer instead of a global, too. Make printOp and printMemReference into methods of Printer. X86InstrInfo::print is now Printer::printMachineInstruction, because TargetInstrInfo::print is history. (Because of this, we have to qualify the names of some TargetInstrInfo methods we call.) Print out the ImplicitUses field of any instruction we print that has the PrintImplUses bit set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6924 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-27 00:00:48 +00:00
I(SHRDrr32 , "shrd", 0xAD, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::TB | X86II::PrintImplUses, O_CL, NoIR) // R32 >>= R32,R32 cl
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 22:55:53 +00:00
Add instruction selection code and tests for setcc instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4603 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-07 17:59:21 +00:00
// Condition code ops, incl. set if equal/not equal/...
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(SAHF , "sahf", 0x9E, 0, X86II::RawFrm, O_AH, NoIR) // flags = AH
I(SETBr , "setb", 0x92, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = < unsign
I(SETAEr , "setae", 0x93, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = >= unsign
Target/X86/Printer.cpp: Add sizePtr function, and use it instead of " <SIZE> PTR " string when emitting assembly. Target/X86/X86InstrInfo.def: Tidy up a bit: Squashed everything down to 118 chars wide, wrapping lines so that comment is at the same point on each line. Rename "NoImpRegs" as "NoIR". (most instructions have NoImpRegs twice on a line, so this saves 10 columns). Also, annotate various instructions with flags for size of memory operand. (MemArg16, MemArg32, MemArg64, etc.) Target/X86/X86InstrInfo.h: Define flags for size of memory operand. (MemArg16, MemArg32, MemArg64, etc.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4932 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-05 08:30:40 +00:00
I(SETEr , "sete", 0x94, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = ==
I(SETNEr , "setne", 0x95, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = !=
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(SETBEr , "setbe", 0x96, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = <= unsign
I(SETAr , "seta", 0x97, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = > unsign
I(SETLr , "setl", 0x9C, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = < signed
I(SETGEr , "setge", 0x9D, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = >= signed
I(SETLEr , "setle", 0x9E, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = <= signed
I(SETGr , "setg", 0x9F, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = > signed
// Conditional moves. These are modelled as X = cmovXX Y, Z. Eventually
// register allocated to cmovXX XY, Z
I(CMOVErr16 , "cmove", 0x44, M_2_ADDR_FLAG, X86II::TB | X86II::OpSize | X86II::MRMSrcReg, NoIR, NoIR) // if ==, R16 = R16
Add new cmovne32 instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6496 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-01 00:05:15 +00:00
I(CMOVNErr32 , "cmovne", 0x45, M_2_ADDR_FLAG, X86II::TB | X86II::MRMSrcReg, NoIR, NoIR) // if !=, R32 = R32
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
Add instruction selection code and tests for setcc instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4603 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-07 17:59:21 +00:00
// Integer comparisons
Rename many instructions to their Intel asm-compatible names. This involves removing the [bwl] suffixes from instruction names, as well as some other distinguishing marks (32/64/80 on fp insns, _i suffixes, etc.) Lowercase all instr. names as well for consistency's sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6790 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:34:44 +00:00
I(CMPrr8 , "cmp", 0x38, 0, X86II::Void | X86II::MRMDestReg , NoIR, NoIR) // compare R8,R8
I(CMPrr16 , "cmp", 0x39, 0, X86II::Void | X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // compare R16,R16
I(CMPrr32 , "cmp", 0x39, 0, X86II::Void | X86II::MRMDestReg , NoIR, NoIR) // compare R32,R32
I(CMPri8 , "cmp", 0x80, 0, X86II::Void | X86II::MRMS7r | X86II::Arg8 , NoIR, NoIR) // compare R8, imm8
I(CMPri16 , "cmp", 0x81, 0, X86II::Void | X86II::MRMS7r | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // compare R8, imm8
I(CMPri32 , "cmp", 0x81, 0, X86II::Void | X86II::MRMS7r | X86II::Arg32 , NoIR, NoIR) // compare R8, imm8
Add instruction selection code and tests for setcc instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4603 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-07 17:59:21 +00:00
include/llvm/CodeGen/MachineInstrBuilder.h: Add addClobber() inline convenience method. Fix typo in comment. lib/Target/X86/InstSelectSimple.cpp: Explicitly specify some implicit uses. Use MOVZX/MOVSX instead of MOV instructions with sign extend instructions. Take out LEAVE instructions. 32-bit IDIV and DIV use CDQ, not CWQ (CWQ is a typo). Fix typo in comment and remove some FIXME comments. lib/Target/X86/Printer.cpp: Include X86InstrInfo.h and llvm/Function.h. Add some simple code to Printer::runOnFunction to iterate over MachineBasicBlocks and call X86InstrInfo::print(). lib/Target/X86/X86InstrInfo.def: Make some more instructions with implicit defs "Void". Add more sign/zero extending "move" insns (movsx, movzx). lib/Target/X86/X86RegisterInfo.def: Add EFLAGS as a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4707 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-14 22:32:30 +00:00
// Sign extenders (first 3 are good for DIV/IDIV; the others are more general)
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(CBW , "cbw", 0x98, 0, X86II::Void | X86II::RawFrm | X86II::OpSize, O_AL, O_AH) // AX = signext(AL)
I(CWD , "cwd", 0x99, 0, X86II::Void | X86II::RawFrm, O_AX, O_DX) // DX:AX = signext(AX)
I(CDQ , "cdq", 0x99, 0, X86II::Void | X86II::RawFrm, O_EAX, O_EDX) // EDX:EAX = signext(EAX)
Target/X86/Printer.cpp: Add sizePtr function, and use it instead of " <SIZE> PTR " string when emitting assembly. Target/X86/X86InstrInfo.def: Tidy up a bit: Squashed everything down to 118 chars wide, wrapping lines so that comment is at the same point on each line. Rename "NoImpRegs" as "NoIR". (most instructions have NoImpRegs twice on a line, so this saves 10 columns). Also, annotate various instructions with flags for size of memory operand. (MemArg16, MemArg32, MemArg64, etc.) Target/X86/X86InstrInfo.h: Define flags for size of memory operand. (MemArg16, MemArg32, MemArg64, etc.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4932 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-05 08:30:40 +00:00
I(MOVSXr16r8 , "movsx", 0xBE, 0, X86II::MRMSrcReg | X86II::TB | // R16 = signext(R8)
X86II::OpSize, NoIR, NoIR)
I(MOVSXr32r8 , "movsx", 0xBE, 0, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 = signext(R8)
I(MOVSXr32r16 , "movsx", 0xBF, 0, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 = signext(R16)
I(MOVZXr16r8 , "movzx", 0xB6, 0, X86II::MRMSrcReg | X86II::TB | // R16 = zeroext(R8)
X86II::OpSize, NoIR, NoIR)
I(MOVZXr32r8 , "movzx", 0xB6, 0, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 = zeroext(R8)
I(MOVZXr32r16 , "movzx", 0xB7, 0, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 = zeroext(R16)
Implement signed and unsigned division and remainder git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4508 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-02 20:54:46 +00:00
* Use new pseudo instr form for instructions * Mark CALLpcrel as a RawFrm instruction as required * Eliminate invalid BSWAP16 instruction * Add xchg instructions * Add initial support for FP instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5153 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-25 05:11:46 +00:00
//===----------------------------------------------------------------------===//
// Floating point support
//===----------------------------------------------------------------------===//
// FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
// Floating point pseudo instructions...
RECAPITALIZE all the names of pseudo-instructions, and add a comment explaining the convention. :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6791 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:41:13 +00:00
I(FpMOV , "FMOV" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo | X86II::SpecialFP, NoIR, NoIR) // f1 = fmov f2
I(FpADD , "FADD" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo | X86II::TwoArgFP , NoIR, NoIR) // f1 = fadd f2, f3
I(FpSUB , "FSUB" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo | X86II::TwoArgFP , NoIR, NoIR) // f1 = fsub f2, f3
I(FpMUL , "FMUL" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo | X86II::TwoArgFP , NoIR, NoIR) // f1 = fmul f2, f3
I(FpDIV , "FDIV" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo | X86II::TwoArgFP , NoIR, NoIR) // f1 = fdiv f2, f3
I(FpUCOM , "FUCOM", 0, M_PSEUDO_FLAG, X86II::Void | X86II::ArgF80 | X86II::Pseudo | X86II::TwoArgFP , NoIR, NoIR) // FPSW = fucom f1, f2
I(FpGETRESULT , "FGETRESULT",0, M_PSEUDO_FLAG, X86II::Pseudo | X86II::SpecialFP, NoIR, NoIR) // FPR = ST(0)
I(FpSETRESULT , "FSETRESULT",0, M_PSEUDO_FLAG | M_TERMINATOR_FLAG, X86II::Void | X86II::Pseudo | X86II::SpecialFP, NoIR, NoIR) // ST(0) = FPR
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
// Floating point loads & stores... PREFIX ARGTYPE ENCODING FP INST TYPE REF MOD
Rename many instructions to their Intel asm-compatible names. This involves removing the [bwl] suffixes from instruction names, as well as some other distinguishing marks (32/64/80 on fp insns, _i suffixes, etc.) Lowercase all instr. names as well for consistency's sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6790 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:34:44 +00:00
I(FLDr32 , "fld", 0xD9, 0, X86II::ArgF32 | X86II::MRMS0m | X86II::ZeroArgFP, NoIR, NoIR) // load float
I(FLDr64 , "fld", 0xDD, 0, X86II::ArgF64 | X86II::MRMS0m | X86II::ZeroArgFP, NoIR, NoIR) // load double
I(FLDr80 , "fld", 0xDB, 0, X86II::ArgF80 | X86II::MRMS5m | X86II::ZeroArgFP, NoIR, NoIR) // load extended
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(FLDrr , "fld" , 0xC0, 0, X86II::D9 | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // push(ST(i))
Rename many instructions to their Intel asm-compatible names. This involves removing the [bwl] suffixes from instruction names, as well as some other distinguishing marks (32/64/80 on fp insns, _i suffixes, etc.) Lowercase all instr. names as well for consistency's sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6790 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:34:44 +00:00
I(FILDr16 , "fild", 0xDF, 0, X86II::Arg16 | X86II::MRMS0m | X86II::ZeroArgFP, NoIR, NoIR) // load signed short
I(FILDr32 , "fild", 0xDB, 0, X86II::Arg32 | X86II::MRMS0m | X86II::ZeroArgFP, NoIR, NoIR) // load signed int
I(FILDr64 , "fild", 0xDF, 0, X86II::Arg64 | X86II::MRMS5m | X86II::ZeroArgFP, NoIR, NoIR) // load signed long
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
Rename many instructions to their Intel asm-compatible names. This involves removing the [bwl] suffixes from instruction names, as well as some other distinguishing marks (32/64/80 on fp insns, _i suffixes, etc.) Lowercase all instr. names as well for consistency's sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6790 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:34:44 +00:00
I(FSTr32 , "fst", 0xD9, 0, X86II::Void | X86II::ArgF32 | X86II::MRMS2m | X86II::OneArgFP , NoIR, NoIR) // store float
I(FSTr64 , "fst", 0xDD, 0, X86II::Void | X86II::ArgF64 | X86II::MRMS2m | X86II::OneArgFP , NoIR, NoIR) // store double
I(FSTPr32 , "fstp", 0xD9, 0, X86II::Void | X86II::ArgF32 | X86II::MRMS3m , NoIR, NoIR) // store float, pop
I(FSTPr64 , "fstp", 0xDD, 0, X86II::Void | X86II::ArgF64 | X86II::MRMS3m , NoIR, NoIR) // store double, pop
I(FSTPr80 , "fstp", 0xDB, 0, X86II::Void | X86II::ArgF80 | X86II::MRMS7m | X86II::OneArgFP , NoIR, NoIR) // store extended, pop
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(FSTrr , "fst" , 0xD0, 0, X86II::DD | X86II::Void | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(i) = ST(0)
I(FSTPrr , "fstp" , 0xD8, 0, X86II::DD | X86II::Void | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(i) = ST(0), pop
Rename many instructions to their Intel asm-compatible names. This involves removing the [bwl] suffixes from instruction names, as well as some other distinguishing marks (32/64/80 on fp insns, _i suffixes, etc.) Lowercase all instr. names as well for consistency's sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6790 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:34:44 +00:00
I(FISTr16 , "fist", 0xDF, 0, X86II::Void | X86II::Arg16 | X86II::MRMS2m | X86II::OneArgFP , NoIR, NoIR) // store signed short
I(FISTr32 , "fist", 0xDB, 0, X86II::Void | X86II::Arg32 | X86II::MRMS2m | X86II::OneArgFP , NoIR, NoIR) // store signed int
I(FISTPr16 , "fistp", 0xDF, 0, X86II::Void | X86II::Arg16 | X86II::MRMS3m , NoIR, NoIR) // store short, pop
I(FISTPr32 , "fistp", 0xDB, 0, X86II::Void | X86II::Arg32 | X86II::MRMS3m , NoIR, NoIR) // store int, pop
I(FISTPr64 , "fistp", 0xDF, 0, X86II::Void | X86II::Arg64 | X86II::MRMS7m | X86II::OneArgFP , NoIR, NoIR) // store long, pop
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(FXCH , "fxch" , 0xC8, 0, X86II::D9 | X86II::Void | X86II::ArgF80 | X86II::AddRegFrm , O_ST0, O_ST0) // fxch ST(i), ST(0)
* Use new pseudo instr form for instructions * Mark CALLpcrel as a RawFrm instruction as required * Eliminate invalid BSWAP16 instruction * Add xchg instructions * Add initial support for FP instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5153 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-25 05:11:46 +00:00
// Floating point constant loads...
Rename many instructions to their Intel asm-compatible names. This involves removing the [bwl] suffixes from instruction names, as well as some other distinguishing marks (32/64/80 on fp insns, _i suffixes, etc.) Lowercase all instr. names as well for consistency's sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6790 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:34:44 +00:00
I(FLD0 , "fldz" , 0xEE, 0, X86II::D9 | X86II::ArgF80 | X86II::RawFrm | X86II::ZeroArgFP, NoIR, NoIR) // load +0.0
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(FLD1 , "fld1" , 0xE8, 0, X86II::D9 | X86II::ArgF80 | X86II::RawFrm | X86II::ZeroArgFP, NoIR, NoIR) // load +1.0
* Use new pseudo instr form for instructions * Mark CALLpcrel as a RawFrm instruction as required * Eliminate invalid BSWAP16 instruction * Add xchg instructions * Add initial support for FP instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5153 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-25 05:11:46 +00:00
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
// Binary arithmetic operations...
Rename many instructions to their Intel asm-compatible names. This involves removing the [bwl] suffixes from instruction names, as well as some other distinguishing marks (32/64/80 on fp insns, _i suffixes, etc.) Lowercase all instr. names as well for consistency's sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6790 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:34:44 +00:00
I(FADDST0r , "fadd", 0xC0, 0, X86II::D8 | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(0) = ST(0) + ST(i)
I(FADDrST0 , "fadd", 0xC0, 0, X86II::DC | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(i) = ST(i) + ST(0)
I(FADDPrST0 , "faddp", 0xC0, 0, X86II::DE | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(i) = ST(i) + ST(0), pop
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
Rename many instructions to their Intel asm-compatible names. This involves removing the [bwl] suffixes from instruction names, as well as some other distinguishing marks (32/64/80 on fp insns, _i suffixes, etc.) Lowercase all instr. names as well for consistency's sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6790 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:34:44 +00:00
I(FSUBRST0r , "fsubr" , 0xE8, 0, X86II::D8 | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(0) = ST(i) - ST(0)
I(FSUBrST0 , "fsub" , 0xE8, 0, X86II::DC | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(i) = ST(i) - ST(0)
I(FSUBPrST0 , "fsubp" , 0xE8, 0, X86II::DE | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(i) = ST(i) - ST(0), pop
* Use new pseudo instr form for instructions * Mark CALLpcrel as a RawFrm instruction as required * Eliminate invalid BSWAP16 instruction * Add xchg instructions * Add initial support for FP instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5153 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-25 05:11:46 +00:00
Rename many instructions to their Intel asm-compatible names. This involves removing the [bwl] suffixes from instruction names, as well as some other distinguishing marks (32/64/80 on fp insns, _i suffixes, etc.) Lowercase all instr. names as well for consistency's sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6790 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:34:44 +00:00
I(FSUBST0r , "fsub" , 0xE0, 0, X86II::D8 | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(0) = ST(0) - ST(i)
I(FSUBRrST0 , "fsubr" , 0xE0, 0, X86II::DC | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(i) = ST(0) - ST(i)
I(FSUBRPrST0 , "fsubrp", 0xE0, 0, X86II::DE | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(i) = ST(0) - ST(i), pop
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
Rename many instructions to their Intel asm-compatible names. This involves removing the [bwl] suffixes from instruction names, as well as some other distinguishing marks (32/64/80 on fp insns, _i suffixes, etc.) Lowercase all instr. names as well for consistency's sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6790 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:34:44 +00:00
I(FMULST0r , "fmul", 0xC8, 0, X86II::D8 | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(0) = ST(0) * ST(i)
I(FMULrST0 , "fmul", 0xC8, 0, X86II::DC | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(i) = ST(i) * ST(0)
I(FMULPrST0 , "fmulp", 0xC8, 0, X86II::DE | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(i) = ST(i) * ST(0), pop
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
Rename many instructions to their Intel asm-compatible names. This involves removing the [bwl] suffixes from instruction names, as well as some other distinguishing marks (32/64/80 on fp insns, _i suffixes, etc.) Lowercase all instr. names as well for consistency's sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6790 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:34:44 +00:00
I(FDIVRST0r , "fdivr" , 0xF8, 0, X86II::D8 | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(0) = ST(i) / ST(0)
I(FDIVrST0 , "fdiv" , 0xF8, 0, X86II::DC | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(i) = ST(i) / ST(0)
I(FDIVPrST0 , "fdivp" , 0xF8, 0, X86II::DE | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(i) = ST(i) / ST(0), pop
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
Rename many instructions to their Intel asm-compatible names. This involves removing the [bwl] suffixes from instruction names, as well as some other distinguishing marks (32/64/80 on fp insns, _i suffixes, etc.) Lowercase all instr. names as well for consistency's sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6790 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-19 19:34:44 +00:00
I(FDIVST0r , "fdiv" , 0xF0, 0, X86II::D8 | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(0) = ST(0) / ST(i)
I(FDIVRrST0 , "fdivr" , 0xF0, 0, X86II::DC | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(i) = ST(0) / ST(i)
I(FDIVRPrST0 , "fdivrp", 0xF0, 0, X86II::DE | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // ST(i) = ST(0) / ST(i), pop
* Use new pseudo instr form for instructions * Mark CALLpcrel as a RawFrm instruction as required * Eliminate invalid BSWAP16 instruction * Add xchg instructions * Add initial support for FP instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5153 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-25 05:11:46 +00:00
// Floating point compares
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(FUCOMr , "fucom" , 0xE0, 0, X86II::DD | X86II::Void | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // FPSW = compare ST(0) with ST(i)
I(FUCOMPr , "fucomp" , 0xE8, 0, X86II::DD | X86II::Void | X86II::ArgF80 | X86II::AddRegFrm , NoIR, NoIR) // compare, pop
I(FUCOMPPr , "fucompp" , 0xE9, 0, X86II::DA | X86II::Void | X86II::RawFrm , NoIR, NoIR) // compare ST(0) with ST(1), pop, pop
* Use new pseudo instr form for instructions * Mark CALLpcrel as a RawFrm instruction as required * Eliminate invalid BSWAP16 instruction * Add xchg instructions * Add initial support for FP instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5153 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-25 05:11:46 +00:00
// Floating point flag ops
* Function calls clobber fp registers * Use new M_TERMINATOR_FLAG flag * Add ::Void flag on several instructions so def-use info is correct! * Implement MANY FP instructions * Finalize pseudo FP instructions * Add set of Pseudo FP instruction description flags * Add support for MOVim instrs * Add support for 64 bit support instrs, like adc sbb, etc * Add conditional move git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5229 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:48:46 +00:00
I(FNSTSWr8 , "fnstsw" , 0xE0, 0, X86II::DF | X86II::Void | X86II::RawFrm , NoIR, O_AX) // AX = fp flags
I(FNSTCWm16 , "fnstcw" , 0xD9, 0, X86II::Void | X86II::Arg16 | X86II::MRMS7m , NoIR, NoIR) // [mem16] = X87 Control Word
I(FLDCWm16 , "fldcw" , 0xD9, 0, X86II::Void | X86II::Arg16 | X86II::MRMS5m , NoIR, NoIR) // X87 Control Word = [mem16]
* Use new pseudo instr form for instructions * Mark CALLpcrel as a RawFrm instruction as required * Eliminate invalid BSWAP16 instruction * Add xchg instructions * Add initial support for FP instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5153 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-25 05:11:46 +00:00
Add flag to specify when no value is produced by an instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4441 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-30 01:09:34 +00:00
// At this point, I is dead, so undefine the macro
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 22:55:53 +00:00
#undef I
Add reg clobber list for direct calls Represent empty use/def list as a null pointer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5101 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-18 01:05:31 +00:00
#undef NoIR
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