2004-07-23 17:56:30 +00:00
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//===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
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2003-11-20 03:32:25 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 19:59:42 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2003-11-20 03:32:25 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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2004-07-19 02:13:59 +00:00
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// This file implements the LiveInterval analysis pass. Given some numbering of
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// each the machine instructions (in this implemention depth-first order) an
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// interval [i, j) is said to be a live interval for register v if there is no
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2008-03-13 23:04:27 +00:00
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// instruction with number j' > j such that v is live at j' and there is no
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2004-07-19 02:13:59 +00:00
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// instruction with number i' < i such that v is live at i'. In this
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// implementation intervals can have holes, i.e. an interval might look like
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// [1,20), [50,65), [1000,1001).
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2003-11-20 03:32:25 +00:00
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//
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//===----------------------------------------------------------------------===//
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2004-07-23 17:56:30 +00:00
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#ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
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#define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
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2003-11-20 03:32:25 +00:00
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2009-08-19 20:52:54 +00:00
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#include "llvm/CodeGen/MachineBasicBlock.h"
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2003-11-20 03:32:25 +00:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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2005-09-21 04:18:25 +00:00
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#include "llvm/CodeGen/LiveInterval.h"
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2009-11-03 23:52:08 +00:00
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#include "llvm/CodeGen/SlotIndexes.h"
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2007-02-15 05:59:24 +00:00
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#include "llvm/ADT/BitVector.h"
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2007-04-17 20:32:26 +00:00
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#include "llvm/ADT/DenseMap.h"
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2009-01-07 02:08:57 +00:00
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#include "llvm/ADT/SmallPtrSet.h"
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2007-08-13 23:45:17 +00:00
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#include "llvm/ADT/SmallVector.h"
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2007-09-05 21:46:51 +00:00
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#include "llvm/Support/Allocator.h"
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2007-11-13 23:04:28 +00:00
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#include <cmath>
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2009-11-03 23:52:08 +00:00
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#include <iterator>
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2003-11-20 03:32:25 +00:00
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namespace llvm {
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2008-07-25 00:02:30 +00:00
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class AliasAnalysis;
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2004-08-04 09:46:26 +00:00
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class LiveVariables;
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2007-12-11 02:09:15 +00:00
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class MachineLoopInfo;
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2008-02-10 18:45:23 +00:00
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class TargetRegisterInfo;
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2007-12-31 04:13:23 +00:00
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class MachineRegisterInfo;
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Allow the live interval analysis pass to be a bit more aggressive about
numbering values in live ranges for physical registers.
The alpha backend currently generates code that looks like this:
vreg = preg
...
preg = vreg
use preg
...
preg = vreg
use preg
etc. Because vreg contains the value of preg coming in, each of the
copies back into preg contain that initial value as well.
In the case of the Alpha, this allows this testcase:
void "foo"(int %blah) {
store int 5, int *%MyVar
store int 12, int* %MyVar2
ret void
}
to compile to:
foo:
ldgp $29, 0($27)
ldiq $0,5
stl $0,MyVar
ldiq $0,12
stl $0,MyVar2
ret $31,($26),1
instead of:
foo:
ldgp $29, 0($27)
bis $29,$29,$0
ldiq $1,5
bis $0,$0,$29
stl $1,MyVar
ldiq $1,12
bis $0,$0,$29
stl $1,MyVar2
ret $31,($26),1
This does not seem to have any noticable effect on X86 code.
This fixes PR535.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20536 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-09 23:05:19 +00:00
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class TargetInstrInfo;
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2007-04-17 20:32:26 +00:00
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class TargetRegisterClass;
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2004-08-04 09:46:26 +00:00
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class VirtRegMap;
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2010-08-12 20:01:23 +00:00
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2004-08-04 09:46:26 +00:00
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class LiveIntervals : public MachineFunctionPass {
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2012-06-04 22:39:14 +00:00
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MachineFunction* MF;
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MachineRegisterInfo* MRI;
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const TargetMachine* TM;
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const TargetRegisterInfo* TRI;
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const TargetInstrInfo* TII;
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AliasAnalysis *AA;
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LiveVariables* LV;
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SlotIndexes* Indexes;
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2004-08-04 09:46:26 +00:00
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2007-09-05 21:46:51 +00:00
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/// Special pool allocator for VNInfo's (LiveInterval val#).
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///
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2010-03-30 20:16:45 +00:00
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VNInfo::Allocator VNInfoAllocator;
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2007-09-05 21:46:51 +00:00
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2008-08-13 22:08:30 +00:00
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typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
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2012-06-04 22:39:14 +00:00
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Reg2IntervalMap R2IMap;
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2004-08-04 09:46:26 +00:00
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2012-06-04 22:39:14 +00:00
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/// AllocatableRegs - A bit vector of allocatable registers.
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BitVector AllocatableRegs;
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2007-03-01 02:03:03 +00:00
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2012-06-04 22:39:14 +00:00
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/// ReservedRegs - A bit vector of reserved registers.
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BitVector ReservedRegs;
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2012-02-14 18:51:53 +00:00
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2012-02-08 17:33:45 +00:00
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/// RegMaskSlots - Sorted list of instructions with register mask operands.
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/// Always use the 'r' slot, RegMasks are normal clobbers, not early
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/// clobbers.
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SmallVector<SlotIndex, 8> RegMaskSlots;
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/// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a
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/// pointer to the corresponding register mask. This pointer can be
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/// recomputed as:
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///
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/// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
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/// unsigned OpNum = findRegMaskOperand(MI);
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/// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
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///
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/// This is kept in a separate vector partly because some standard
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/// libraries don't support lower_bound() with mixed objects, partly to
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/// improve locality when searching in RegMaskSlots.
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/// Also see the comment in LiveInterval::find().
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SmallVector<const uint32_t*, 8> RegMaskBits;
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2012-02-10 01:26:29 +00:00
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/// For each basic block number, keep (begin, size) pairs indexing into the
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/// RegMaskSlots and RegMaskBits arrays.
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/// Note that basic block numbers may not be layout contiguous, that's why
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/// we can't just keep track of the first register mask in each basic
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/// block.
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SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
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2004-08-04 09:46:26 +00:00
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public:
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2007-05-06 13:37:16 +00:00
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static char ID; // Pass identification, replacement for typeid
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2010-10-19 17:21:58 +00:00
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LiveIntervals() : MachineFunctionPass(ID) {
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initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
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}
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2007-05-01 21:15:47 +00:00
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2010-03-01 20:59:38 +00:00
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// Calculate the spill weight to assign to a single instruction.
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static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
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2007-11-12 06:35:08 +00:00
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2004-08-04 09:46:26 +00:00
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typedef Reg2IntervalMap::iterator iterator;
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2004-09-30 15:59:17 +00:00
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typedef Reg2IntervalMap::const_iterator const_iterator;
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2012-06-04 22:39:14 +00:00
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const_iterator begin() const { return R2IMap.begin(); }
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const_iterator end() const { return R2IMap.end(); }
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iterator begin() { return R2IMap.begin(); }
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iterator end() { return R2IMap.end(); }
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unsigned getNumIntervals() const { return (unsigned)R2IMap.size(); }
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2004-08-04 09:46:26 +00:00
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LiveInterval &getInterval(unsigned reg) {
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2012-06-04 22:39:14 +00:00
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Reg2IntervalMap::iterator I = R2IMap.find(reg);
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assert(I != R2IMap.end() && "Interval does not exist for register");
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2008-08-13 21:49:13 +00:00
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return *I->second;
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2004-08-04 09:46:26 +00:00
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}
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const LiveInterval &getInterval(unsigned reg) const {
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2012-06-04 22:39:14 +00:00
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Reg2IntervalMap::const_iterator I = R2IMap.find(reg);
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assert(I != R2IMap.end() && "Interval does not exist for register");
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2008-08-13 21:49:13 +00:00
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return *I->second;
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2004-08-04 09:46:26 +00:00
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}
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2007-02-19 21:49:54 +00:00
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bool hasInterval(unsigned reg) const {
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2012-06-04 22:39:14 +00:00
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return R2IMap.count(reg);
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2007-02-19 21:49:54 +00:00
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}
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2010-08-10 00:02:26 +00:00
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/// isAllocatable - is the physical register reg allocatable in the current
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/// function?
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bool isAllocatable(unsigned reg) const {
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2012-06-04 22:39:14 +00:00
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return AllocatableRegs.test(reg);
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2010-08-10 00:02:26 +00:00
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}
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2012-02-14 18:51:53 +00:00
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/// isReserved - is the physical register reg reserved in the current
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/// function
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bool isReserved(unsigned reg) const {
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2012-06-04 22:39:14 +00:00
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return ReservedRegs.test(reg);
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2012-02-14 18:51:53 +00:00
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}
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2008-07-22 22:46:49 +00:00
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/// getApproximateInstructionCount - computes an estimate of the number
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/// of instructions in a given LiveInterval.
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unsigned getApproximateInstructionCount(LiveInterval& I) {
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2012-04-25 16:32:23 +00:00
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return I.getSize()/SlotIndex::InstrDist;
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2008-10-23 20:43:13 +00:00
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}
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2007-06-08 17:18:56 +00:00
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// Interval creation
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LiveInterval &getOrCreateInterval(unsigned reg) {
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2012-06-04 22:39:14 +00:00
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Reg2IntervalMap::iterator I = R2IMap.find(reg);
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if (I == R2IMap.end())
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I = R2IMap.insert(std::make_pair(reg, createInterval(reg))).first;
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2008-08-13 21:49:13 +00:00
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return *I->second;
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2007-06-08 17:18:56 +00:00
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}
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2009-02-08 11:04:35 +00:00
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2008-06-05 17:15:43 +00:00
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/// addLiveRangeToEndOfBlock - Given a register and an instruction,
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/// adds a live range from that instruction to the end of its MBB.
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LiveRange addLiveRangeToEndOfBlock(unsigned reg,
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2009-09-04 20:41:11 +00:00
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MachineInstr* startInst);
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2004-08-04 09:46:26 +00:00
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2011-02-08 00:03:05 +00:00
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/// shrinkToUses - After removing some uses of a register, shrink its live
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/// range to just the remaining uses. This method does not compute reaching
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/// defs for new uses, and it doesn't remove dead defs.
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/// Dead PHIDef values are marked as unused.
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2011-03-07 23:29:10 +00:00
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/// New dead machine instructions are added to the dead vector.
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2011-03-17 20:37:07 +00:00
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/// Return true if the interval may have been separated into multiple
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/// connected components.
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bool shrinkToUses(LiveInterval *li,
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2011-03-07 23:29:10 +00:00
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SmallVectorImpl<MachineInstr*> *dead = 0);
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2011-02-08 00:03:05 +00:00
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2007-06-08 17:18:56 +00:00
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// Interval removal
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2004-08-04 09:46:26 +00:00
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2007-06-08 17:18:56 +00:00
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void removeInterval(unsigned Reg) {
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2012-06-04 22:39:14 +00:00
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DenseMap<unsigned, LiveInterval*>::iterator I = R2IMap.find(Reg);
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2008-08-13 21:49:13 +00:00
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delete I->second;
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2012-06-04 22:39:14 +00:00
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R2IMap.erase(I);
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2006-12-17 05:15:13 +00:00
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}
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2004-09-30 15:59:17 +00:00
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2011-01-12 22:28:48 +00:00
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SlotIndexes *getSlotIndexes() const {
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2012-06-04 22:39:14 +00:00
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return Indexes;
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2011-01-12 22:28:48 +00:00
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}
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2009-04-21 22:46:52 +00:00
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/// isNotInMIMap - returns true if the specified machine instr has been
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/// removed or was never entered in the map.
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2009-11-03 23:52:08 +00:00
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bool isNotInMIMap(const MachineInstr* Instr) const {
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2012-06-04 22:39:14 +00:00
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return !Indexes->hasIndex(Instr);
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2009-11-03 23:52:08 +00:00
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}
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/// Returns the base index of the given instruction.
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SlotIndex getInstructionIndex(const MachineInstr *instr) const {
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2012-06-04 22:39:14 +00:00
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return Indexes->getInstructionIndex(instr);
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2009-11-03 23:52:08 +00:00
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}
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2010-08-12 20:01:23 +00:00
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2009-11-03 23:52:08 +00:00
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/// Returns the instruction associated with the given index.
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MachineInstr* getInstructionFromIndex(SlotIndex index) const {
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2012-06-04 22:39:14 +00:00
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return Indexes->getInstructionFromIndex(index);
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2009-11-03 23:52:08 +00:00
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}
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/// Return the first index in the given basic block.
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SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
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2012-06-04 22:39:14 +00:00
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return Indexes->getMBBStartIdx(mbb);
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2010-08-12 20:01:23 +00:00
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}
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2009-11-03 23:52:08 +00:00
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/// Return the last index in the given basic block.
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SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
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2012-06-04 22:39:14 +00:00
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return Indexes->getMBBEndIdx(mbb);
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2010-08-12 20:01:23 +00:00
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}
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2009-11-03 23:52:08 +00:00
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2010-07-17 07:34:01 +00:00
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bool isLiveInToMBB(const LiveInterval &li,
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const MachineBasicBlock *mbb) const {
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return li.liveAt(getMBBStartIdx(mbb));
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}
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bool isLiveOutOfMBB(const LiveInterval &li,
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const MachineBasicBlock *mbb) const {
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return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());
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}
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2009-11-03 23:52:08 +00:00
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MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
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2012-06-04 22:39:14 +00:00
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return Indexes->getMBBFromIndex(index);
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2009-11-03 23:52:08 +00:00
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}
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2009-11-14 00:02:51 +00:00
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SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
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2012-06-04 22:39:14 +00:00
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return Indexes->insertMachineInstrInMaps(MI);
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2007-02-22 23:03:39 +00:00
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}
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2006-08-24 22:43:55 +00:00
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void RemoveMachineInstrFromMaps(MachineInstr *MI) {
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2012-06-04 22:39:14 +00:00
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Indexes->removeMachineInstrFromMaps(MI);
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2006-08-24 22:43:55 +00:00
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}
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2007-06-08 17:18:56 +00:00
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2008-02-13 03:01:43 +00:00
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void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
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2012-06-04 22:39:14 +00:00
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Indexes->replaceMachineInstrInMaps(MI, NewMI);
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2009-11-03 23:52:08 +00:00
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}
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bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
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SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
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2012-06-04 22:39:14 +00:00
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return Indexes->findLiveInMBBs(Start, End, MBBs);
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2009-11-03 23:52:08 +00:00
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}
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2010-03-30 20:16:45 +00:00
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VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
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2007-09-05 21:46:51 +00:00
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2007-06-08 17:18:56 +00:00
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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/// runOnMachineFunction - pass entry point
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virtual bool runOnMachineFunction(MachineFunction&);
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/// print - Implement the dump method.
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2009-08-23 06:03:38 +00:00
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virtual void print(raw_ostream &O, const Module* = 0) const;
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2007-06-08 17:18:56 +00:00
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2007-12-06 00:01:56 +00:00
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/// isReMaterializable - Returns true if every definition of MI of every
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/// val# of the specified interval is re-materializable. Also returns true
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/// by reference if all of the defs are load instructions.
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2008-09-30 15:44:16 +00:00
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bool isReMaterializable(const LiveInterval &li,
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2011-03-10 01:21:58 +00:00
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const SmallVectorImpl<LiveInterval*> *SpillIs,
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2008-09-30 15:44:16 +00:00
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bool &isLoad);
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2007-12-06 00:01:56 +00:00
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2012-02-10 01:23:55 +00:00
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/// intervalIsInOneMBB - If LI is confined to a single basic block, return
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/// a pointer to that block. If LI is live in to or out of any block,
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/// return NULL.
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MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
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2009-01-13 06:05:10 +00:00
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2011-02-08 21:13:03 +00:00
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/// addKillFlags - Add kill flags to any instruction that kills a virtual
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/// register.
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void addKillFlags();
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2012-02-15 01:23:52 +00:00
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/// handleMove - call this method to notify LiveIntervals that
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/// instruction 'mi' has been moved within a basic block. This will update
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/// the live intervals for all operands of mi. Moves between basic blocks
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/// are not supported.
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2012-02-21 22:29:38 +00:00
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void handleMove(MachineInstr* MI);
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/// moveIntoBundle - Update intervals for operands of MI so that they
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/// begin/end on the SlotIndex for BundleStart.
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///
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/// Requires MI and BundleStart to have SlotIndexes, and assumes
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/// existing liveness is accurate. BundleStart should be the first
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/// instruction in the Bundle.
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void handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart);
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2012-01-27 22:36:19 +00:00
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2012-02-08 17:33:45 +00:00
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// Register mask functions.
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//
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// Machine instructions may use a register mask operand to indicate that a
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// large number of registers are clobbered by the instruction. This is
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// typically used for calls.
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//
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// For compile time performance reasons, these clobbers are not recorded in
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// the live intervals for individual physical registers. Instead,
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// LiveIntervalAnalysis maintains a sorted list of instructions with
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// register mask operands.
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2012-02-10 01:26:29 +00:00
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/// getRegMaskSlots - Returns a sorted array of slot indices of all
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2012-02-08 17:33:45 +00:00
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/// instructions with register mask operands.
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ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
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2012-02-10 01:26:29 +00:00
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/// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all
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/// instructions with register mask operands in the basic block numbered
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/// MBBNum.
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ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
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std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
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return getRegMaskSlots().slice(P.first, P.second);
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}
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/// getRegMaskBits() - Returns an array of register mask pointers
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/// corresponding to getRegMaskSlots().
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ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
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/// getRegMaskBitsInBlock - Returns an array of mask pointers corresponding
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/// to getRegMaskSlotsInBlock(MBBNum).
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ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const {
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std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
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return getRegMaskBits().slice(P.first, P.second);
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}
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2012-02-08 17:33:45 +00:00
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/// checkRegMaskInterference - Test if LI is live across any register mask
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/// instructions, and compute a bit mask of physical registers that are not
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/// clobbered by any of them.
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///
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/// Returns false if LI doesn't cross any register mask instructions. In
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/// that case, the bit vector is not filled in.
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bool checkRegMaskInterference(LiveInterval &LI,
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BitVector &UsableRegs);
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2010-08-12 20:01:23 +00:00
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private:
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2006-09-15 03:57:23 +00:00
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/// computeIntervals - Compute live intervals.
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2006-09-14 06:42:17 +00:00
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void computeIntervals();
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2009-09-14 21:33:42 +00:00
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2004-08-04 09:46:26 +00:00
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/// handleRegisterDef - update intervals for a register def
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/// (calls handlePhysicalRegisterDef and
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/// handleVirtualRegisterDef)
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2006-09-03 08:07:11 +00:00
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void handleRegisterDef(MachineBasicBlock *MBB,
|
2009-09-04 20:41:11 +00:00
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MachineBasicBlock::iterator MI,
|
2009-11-03 23:52:08 +00:00
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SlotIndex MIIdx,
|
2008-07-10 07:35:43 +00:00
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MachineOperand& MO, unsigned MOIdx);
|
2004-08-04 09:46:26 +00:00
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2010-05-05 18:27:40 +00:00
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/// isPartialRedef - Return true if the specified def at the specific index
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/// is partially re-defining the specified live interval. A common case of
|
2010-08-12 20:01:23 +00:00
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/// this is a definition of the sub-register.
|
2010-05-05 18:27:40 +00:00
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bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
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LiveInterval &interval);
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|
2004-08-04 09:46:26 +00:00
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/// handleVirtualRegisterDef - update intervals for a virtual
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/// register def
|
2006-09-03 08:07:11 +00:00
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void handleVirtualRegisterDef(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MI,
|
2009-11-03 23:52:08 +00:00
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SlotIndex MIIdx, MachineOperand& MO,
|
2009-09-04 20:41:11 +00:00
|
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unsigned MOIdx,
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|
LiveInterval& interval);
|
2004-08-04 09:46:26 +00:00
|
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|
Allow the live interval analysis pass to be a bit more aggressive about
numbering values in live ranges for physical registers.
The alpha backend currently generates code that looks like this:
vreg = preg
...
preg = vreg
use preg
...
preg = vreg
use preg
etc. Because vreg contains the value of preg coming in, each of the
copies back into preg contain that initial value as well.
In the case of the Alpha, this allows this testcase:
void "foo"(int %blah) {
store int 5, int *%MyVar
store int 12, int* %MyVar2
ret void
}
to compile to:
foo:
ldgp $29, 0($27)
ldiq $0,5
stl $0,MyVar
ldiq $0,12
stl $0,MyVar2
ret $31,($26),1
instead of:
foo:
ldgp $29, 0($27)
bis $29,$29,$0
ldiq $1,5
bis $0,$0,$29
stl $1,MyVar
ldiq $1,12
bis $0,$0,$29
stl $1,MyVar2
ret $31,($26),1
This does not seem to have any noticable effect on X86 code.
This fixes PR535.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20536 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-09 23:05:19 +00:00
|
|
|
/// handlePhysicalRegisterDef - update intervals for a physical register
|
2006-08-24 22:43:55 +00:00
|
|
|
/// def.
|
2004-08-04 09:46:26 +00:00
|
|
|
void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
|
|
|
|
MachineBasicBlock::iterator mi,
|
2009-11-03 23:52:08 +00:00
|
|
|
SlotIndex MIIdx, MachineOperand& MO,
|
2012-02-04 05:20:49 +00:00
|
|
|
LiveInterval &interval);
|
2004-08-04 09:46:26 +00:00
|
|
|
|
2007-02-19 21:49:54 +00:00
|
|
|
/// handleLiveInRegister - Create interval for a livein register.
|
2007-02-21 22:41:17 +00:00
|
|
|
void handleLiveInRegister(MachineBasicBlock* mbb,
|
2009-11-03 23:52:08 +00:00
|
|
|
SlotIndex MIIdx,
|
2012-02-10 03:19:36 +00:00
|
|
|
LiveInterval &interval);
|
2007-02-19 21:49:54 +00:00
|
|
|
|
2008-02-22 09:24:50 +00:00
|
|
|
/// getReMatImplicitUse - If the remat definition MI has one (for now, we
|
|
|
|
/// only allow one) virtual register operand, then its uses are implicitly
|
|
|
|
/// using the register. Returns the virtual register.
|
|
|
|
unsigned getReMatImplicitUse(const LiveInterval &li,
|
|
|
|
MachineInstr *MI) const;
|
|
|
|
|
|
|
|
/// isValNoAvailableAt - Return true if the val# of the specified interval
|
|
|
|
/// which reaches the given instruction also reaches the specified use
|
|
|
|
/// index.
|
|
|
|
bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
|
2009-11-03 23:52:08 +00:00
|
|
|
SlotIndex UseIdx) const;
|
2008-02-22 09:24:50 +00:00
|
|
|
|
2007-08-13 23:45:17 +00:00
|
|
|
/// isReMaterializable - Returns true if the definition MI of the specified
|
2007-12-06 00:01:56 +00:00
|
|
|
/// val# of the specified interval is re-materializable. Also returns true
|
|
|
|
/// by reference if the def is a load.
|
2007-08-29 20:45:00 +00:00
|
|
|
bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
|
2008-09-30 15:44:16 +00:00
|
|
|
MachineInstr *MI,
|
2011-03-10 01:21:58 +00:00
|
|
|
const SmallVectorImpl<LiveInterval*> *SpillIs,
|
2008-09-30 15:44:16 +00:00
|
|
|
bool &isLoad);
|
2007-08-13 23:45:17 +00:00
|
|
|
|
2008-08-13 21:49:13 +00:00
|
|
|
static LiveInterval* createInterval(unsigned Reg);
|
2004-08-04 09:46:26 +00:00
|
|
|
|
2009-09-14 21:33:42 +00:00
|
|
|
void printInstrs(raw_ostream &O) const;
|
|
|
|
void dumpInstrs() const;
|
2012-02-17 18:44:18 +00:00
|
|
|
|
|
|
|
class HMEditor;
|
2004-08-04 09:46:26 +00:00
|
|
|
};
|
2003-11-20 03:32:25 +00:00
|
|
|
} // End llvm namespace
|
|
|
|
|
|
|
|
#endif
|