2001-11-08 04:48:50 +00:00
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// $Id$
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//***************************************************************************
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// File:
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// PhyRegAlloc.cpp
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//
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// Purpose:
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// Register allocation for LLVM.
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//
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// History:
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// 9/10/01 - Ruchira Sasanka - created.
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//**************************************************************************/
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2001-09-14 21:18:34 +00:00
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#include "llvm/CodeGen/PhyRegAlloc.h"
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2001-11-08 04:48:50 +00:00
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineFrameInfo.h"
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2001-09-14 21:18:34 +00:00
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2001-11-08 04:48:50 +00:00
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// ***TODO: There are several places we add instructions. Validate the order
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// of adding these instructions.
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2001-10-28 18:12:02 +00:00
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2001-09-19 16:26:23 +00:00
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cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
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"enable register allocation debugging information",
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clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
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clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"),
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clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
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2001-09-15 21:11:11 +00:00
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//----------------------------------------------------------------------------
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// Constructor: Init local composite objects and create register classes.
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//----------------------------------------------------------------------------
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2001-11-08 04:48:50 +00:00
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PhyRegAlloc::PhyRegAlloc(Method *M,
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2001-09-14 21:18:34 +00:00
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const TargetMachine& tm,
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MethodLiveVarInfo *const Lvi)
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: RegClassList(),
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2001-11-08 04:48:50 +00:00
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TM(tm),
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Meth(M),
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mcInfo(MachineCodeForMethod::get(M)),
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LVI(Lvi), LRI(M, tm, RegClassList),
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2001-09-14 21:18:34 +00:00
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MRI( tm.getRegInfo() ),
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NumOfRegClasses(MRI.getNumOfRegClasses()),
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2001-11-08 04:48:50 +00:00
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AddedInstrMap()
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2001-11-13 23:09:30 +00:00
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2001-09-14 21:18:34 +00:00
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{
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// **TODO: use an actual reserved color list
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ReservedColorListType *RCL = new ReservedColorListType();
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// create each RegisterClass and put in RegClassList
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for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
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RegClassList.push_back( new RegClass(M, MRI.getMachineRegClass(rc), RCL) );
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}
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2001-09-15 21:11:11 +00:00
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//----------------------------------------------------------------------------
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// This method initally creates interference graphs (one in each reg class)
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// and IGNodeList (one in each IG). The actual nodes will be pushed later.
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//----------------------------------------------------------------------------
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2001-09-14 21:18:34 +00:00
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void PhyRegAlloc::createIGNodeListsAndIGs()
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{
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2001-10-16 01:23:19 +00:00
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if(DEBUG_RA ) cout << "Creating LR lists ..." << endl;
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2001-09-14 21:18:34 +00:00
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// hash map iterator
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LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
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// hash map end
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LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
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for( ; HMI != HMIEnd ; ++HMI ) {
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2001-09-30 23:11:59 +00:00
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if( (*HMI).first ) {
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2001-09-14 21:18:34 +00:00
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2001-09-30 23:11:59 +00:00
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LiveRange *L = (*HMI).second; // get the LiveRange
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2001-09-14 21:18:34 +00:00
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2001-09-30 23:11:59 +00:00
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if( !L) {
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if( DEBUG_RA) {
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2001-10-16 01:23:19 +00:00
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cout << "\n*?!?Warning: Null liver range found for: ";
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printValue( (*HMI).first) ; cout << endl;
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2001-09-30 23:11:59 +00:00
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}
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continue;
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}
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2001-09-14 21:18:34 +00:00
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// if the Value * is not null, and LR
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// is not yet written to the IGNodeList
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if( !(L->getUserIGNode()) ) {
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RegClass *const RC = // RegClass of first value in the LR
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//RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
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RegClassList[ L->getRegClass()->getID() ];
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RC-> addLRToIG( L ); // add this LR to an IG
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}
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}
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}
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// init RegClassList
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->createInterferenceGraph();
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if( DEBUG_RA)
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2001-10-16 01:23:19 +00:00
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cout << "LRLists Created!" << endl;
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2001-09-14 21:18:34 +00:00
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}
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2001-09-15 21:11:11 +00:00
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//----------------------------------------------------------------------------
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// This method will add all interferences at for a given instruction.
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2001-09-14 21:18:34 +00:00
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// Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
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// class as that of live var. The live var passed to this function is the
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// LVset AFTER the instruction
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2001-09-15 21:11:11 +00:00
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//----------------------------------------------------------------------------
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2001-09-14 21:18:34 +00:00
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void PhyRegAlloc::addInterference(const Value *const Def,
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const LiveVarSet *const LVSet,
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const bool isCallInst) {
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LiveVarSet::const_iterator LIt = LVSet->begin();
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// get the live range of instruction
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const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
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IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
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assert( IGNodeOfDef );
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RegClass *const RCOfDef = LROfDef->getRegClass();
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// for each live var in live variable set
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for( ; LIt != LVSet->end(); ++LIt) {
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if( DEBUG_RA > 1) {
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2001-10-16 01:23:19 +00:00
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cout << "< Def="; printValue(Def);
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cout << ", Lvar="; printValue( *LIt); cout << "> ";
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2001-09-14 21:18:34 +00:00
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}
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// get the live range corresponding to live var
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LiveRange *const LROfVar = LRI.getLiveRangeForValue(*LIt );
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// LROfVar can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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if( LROfVar) {
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if(LROfDef == LROfVar) // do not set interf for same LR
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continue;
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// if 2 reg classes are the same set interference
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if( RCOfDef == LROfVar->getRegClass() ){
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RCOfDef->setInterference( LROfDef, LROfVar);
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}
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2001-09-15 19:06:58 +00:00
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else if(DEBUG_RA > 1) {
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2001-09-14 21:18:34 +00:00
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// we will not have LRs for values not explicitly allocated in the
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// instruction stream (e.g., constants)
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2001-10-16 01:23:19 +00:00
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cout << " warning: no live range for " ;
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printValue( *LIt); cout << endl; }
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2001-09-14 21:18:34 +00:00
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2001-10-19 17:21:03 +00:00
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}
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2001-09-14 21:18:34 +00:00
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2001-10-19 17:21:03 +00:00
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}
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2001-09-14 21:18:34 +00:00
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}
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2001-10-19 17:21:03 +00:00
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//----------------------------------------------------------------------------
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// For a call instruction, this method sets the CallInterference flag in
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// the LR of each variable live int the Live Variable Set live after the
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// call instruction (except the return value of the call instruction - since
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// the return value does not interfere with that call itself).
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//----------------------------------------------------------------------------
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void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
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const LiveVarSet *const LVSetAft )
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{
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// Now find the LR of the return value of the call
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2001-10-21 16:43:41 +00:00
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2001-10-19 17:21:03 +00:00
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// We do this because, we look at the LV set *after* the instruction
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// to determine, which LRs must be saved across calls. The return value
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// of the call is live in this set - but it does not interfere with call
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// (i.e., we can allocate a volatile register to the return value)
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LiveRange *RetValLR = NULL;
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2001-10-21 16:43:41 +00:00
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const Value *RetVal = MRI.getCallInstRetVal( MInst );
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2001-10-19 17:21:03 +00:00
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2001-10-21 16:43:41 +00:00
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if( RetVal ) {
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RetValLR = LRI.getLiveRangeForValue( RetVal );
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assert( RetValLR && "No LR for RetValue of call");
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2001-10-19 17:21:03 +00:00
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}
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if( DEBUG_RA)
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cout << "\n For call inst: " << *MInst;
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LiveVarSet::const_iterator LIt = LVSetAft->begin();
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// for each live var in live variable set after machine inst
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for( ; LIt != LVSetAft->end(); ++LIt) {
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// get the live range corresponding to live var
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LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
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if( LR && DEBUG_RA) {
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cout << "\n\tLR Aft Call: ";
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LR->printSet();
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}
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// LR can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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if( LR && (LR != RetValLR) ) {
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LR->setCallInterference();
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if( DEBUG_RA) {
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cout << "\n ++Added call interf for LR: " ;
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LR->printSet();
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}
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}
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}
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}
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2001-09-15 21:11:11 +00:00
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//----------------------------------------------------------------------------
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// This method will walk thru code and create interferences in the IG of
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// each RegClass.
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//----------------------------------------------------------------------------
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2001-09-14 21:18:34 +00:00
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void PhyRegAlloc::buildInterferenceGraphs()
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{
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2001-10-16 01:23:19 +00:00
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if(DEBUG_RA) cout << "Creating interference graphs ..." << endl;
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2001-09-14 21:18:34 +00:00
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
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// get the iterator for machine instructions
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const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::const_iterator
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MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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2001-09-30 23:11:59 +00:00
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2001-11-03 17:13:27 +00:00
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const MachineInstr * MInst = *MInstIterator;
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2001-09-14 21:18:34 +00:00
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// get the LV set after the instruction
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const LiveVarSet *const LVSetAI =
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LVI->getLiveVarSetAfterMInst(MInst, *BBI);
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const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
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2001-10-19 17:21:03 +00:00
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if( isCallInst ) {
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//cout << "\nFor call inst: " << *MInst;
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// set the isCallInterference flag of each live range wich extends
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// accross this call instruction. This information is used by graph
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// coloring algo to avoid allocating volatile colors to live ranges
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// that span across calls (since they have to be saved/restored)
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setCallInterferences( MInst, LVSetAI);
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}
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2001-10-16 01:23:19 +00:00
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2001-09-14 21:18:34 +00:00
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// iterate over MI operands to find defs
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for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
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2001-11-14 15:33:58 +00:00
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if( OpI.isDef() ) {
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2001-09-14 21:18:34 +00:00
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// create a new LR iff this operand is a def
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addInterference(*OpI, LVSetAI, isCallInst );
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} //if this is a def
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} // for all operands
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2001-10-16 01:23:19 +00:00
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2001-11-14 15:33:58 +00:00
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// if there are multiple defs in this instruction e.g. in SETX
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//
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if( (TM.getInstrInfo()).isPseudoInstr( MInst->getOpCode()) )
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addInterf4PseudoInstr(MInst);
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2001-10-16 01:23:19 +00:00
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// Also add interference for any implicit definitions in a machine
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// instr (currently, only calls have this).
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unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
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if( NumOfImpRefs > 0 ) {
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for(unsigned z=0; z < NumOfImpRefs; z++)
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if( MInst->implicitRefIsDefined(z) )
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addInterference( MInst->getImplicitRef(z), LVSetAI, isCallInst );
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}
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2001-11-03 20:41:22 +00:00
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/*
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2001-11-03 17:13:27 +00:00
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// record phi instrns in PhiInstList
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if( TM.getInstrInfo().isDummyPhiInstr(MInst->getOpCode()) )
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PhiInstList.push_back( MInst );
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2001-11-03 20:41:22 +00:00
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*/
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2001-11-03 17:13:27 +00:00
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2001-09-14 21:18:34 +00:00
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} // for all machine instructions in BB
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} // for all BBs in method
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// add interferences for method arguments. Since there are no explict
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// defs in method for args, we have to add them manually
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addInterferencesForArgs(); // add interference for method args
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if( DEBUG_RA)
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2001-10-16 01:23:19 +00:00
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cout << "Interference graphs calculted!" << endl;
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2001-09-14 21:18:34 +00:00
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}
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2001-11-14 15:33:58 +00:00
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//--------------------------------------------------------------------------
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// Pseudo instructions will be exapnded to multiple instructions by the
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// assembler. Consequently, all the opernds must get distinct registers
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//--------------------------------------------------------------------------
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void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
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2001-11-15 15:00:53 +00:00
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bool setInterf = false;
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2001-11-14 15:33:58 +00:00
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// iterate over MI operands to find defs
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for( MachineInstr::val_op_const_iterator It1(MInst);!It1.done(); ++It1) {
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const LiveRange *const LROfOp1 = LRI.getLiveRangeForValue( *It1 );
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2001-11-15 15:00:53 +00:00
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if( !LROfOp1 && It1.isDef() )
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assert( 0 && "No LR for Def in PSEUDO insruction");
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//if( !LROfOp1 ) continue;
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2001-11-14 15:33:58 +00:00
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MachineInstr::val_op_const_iterator It2 = It1;
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|
++It2;
|
|
|
|
|
|
|
|
for( ; !It2.done(); ++It2) {
|
|
|
|
|
|
|
|
const LiveRange *const LROfOp2 = LRI.getLiveRangeForValue( *It2 );
|
|
|
|
|
|
|
|
if( LROfOp2) {
|
|
|
|
|
|
|
|
RegClass *const RCOfOp1 = LROfOp1->getRegClass();
|
|
|
|
RegClass *const RCOfOp2 = LROfOp2->getRegClass();
|
|
|
|
|
|
|
|
if( RCOfOp1 == RCOfOp2 ){
|
|
|
|
RCOfOp1->setInterference( LROfOp1, LROfOp2 );
|
|
|
|
//cerr << "\nSet interfs for PSEUDO inst: " << *MInst;
|
2001-11-15 15:00:53 +00:00
|
|
|
setInterf = true;
|
2001-11-14 15:33:58 +00:00
|
|
|
}
|
|
|
|
|
2001-11-15 15:00:53 +00:00
|
|
|
|
2001-11-14 15:33:58 +00:00
|
|
|
} // if Op2 has a LR
|
|
|
|
|
|
|
|
} // for all other defs in machine instr
|
|
|
|
|
|
|
|
} // for all operands in an instruction
|
|
|
|
|
2001-11-15 15:00:53 +00:00
|
|
|
if( !setInterf && (MInst->getNumOperands() > 2) ) {
|
|
|
|
cerr << "\nInterf not set for any operand in pseudo instr:\n";
|
|
|
|
cerr << *MInst;
|
|
|
|
assert(0 && "Interf not set for pseudo instr with > 2 operands" );
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2001-11-14 15:33:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2001-09-14 21:18:34 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
2001-09-15 21:11:11 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// This method will add interferences for incoming arguments to a method.
|
|
|
|
//----------------------------------------------------------------------------
|
2001-09-14 21:18:34 +00:00
|
|
|
void PhyRegAlloc::addInterferencesForArgs()
|
|
|
|
{
|
|
|
|
// get the InSet of root BB
|
|
|
|
const LiveVarSet *const InSet = LVI->getInSetOfBB( Meth->front() );
|
|
|
|
|
|
|
|
// get the argument list
|
|
|
|
const Method::ArgumentListType& ArgList = Meth->getArgumentList();
|
|
|
|
|
|
|
|
// get an iterator to arg list
|
|
|
|
Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
|
|
|
|
|
|
|
|
|
|
|
|
for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
|
|
|
|
addInterference( *ArgIt, InSet, false ); // add interferences between
|
|
|
|
// args and LVars at start
|
|
|
|
if( DEBUG_RA > 1) {
|
2001-10-18 22:36:26 +00:00
|
|
|
cout << " - %% adding interference for argument ";
|
2001-10-16 01:23:19 +00:00
|
|
|
printValue( (const Value *) *ArgIt); cout << endl;
|
2001-09-14 21:18:34 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2001-09-15 21:11:11 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// This method is called after register allocation is complete to set the
|
|
|
|
// allocated reisters in the machine code. This code will add register numbers
|
|
|
|
// to MachineOperands that contain a Value.
|
|
|
|
//----------------------------------------------------------------------------
|
2001-09-14 21:18:34 +00:00
|
|
|
|
|
|
|
void PhyRegAlloc::updateMachineCode()
|
|
|
|
{
|
|
|
|
|
|
|
|
Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
|
|
|
|
|
|
|
|
for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
|
|
|
|
|
2001-09-15 19:06:58 +00:00
|
|
|
// get the iterator for machine instructions
|
|
|
|
MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
|
|
|
|
MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
|
|
|
|
|
|
|
|
// iterate over all the machine instructions in BB
|
|
|
|
for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
|
|
|
|
|
2001-09-30 23:11:59 +00:00
|
|
|
MachineInstr *MInst = *MInstIterator;
|
|
|
|
|
2001-11-10 21:21:36 +00:00
|
|
|
// do not process Phis
|
|
|
|
if( (TM.getInstrInfo()).isPhi( MInst->getOpCode()) )
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
2001-10-16 01:23:19 +00:00
|
|
|
// if this machine instr is call, insert caller saving code
|
|
|
|
|
|
|
|
if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) )
|
2001-10-28 18:12:02 +00:00
|
|
|
MRI.insertCallerSavingCode(MInst, *BBI, *this );
|
2001-09-30 23:11:59 +00:00
|
|
|
|
|
|
|
|
2001-10-28 18:12:02 +00:00
|
|
|
// reset the stack offset for temporary variables since we may
|
|
|
|
// need that to spill
|
2001-11-15 22:02:06 +00:00
|
|
|
//mcInfo.popAllTempValues(TM);
|
|
|
|
// TODO ** : do later
|
2001-11-08 04:48:50 +00:00
|
|
|
|
2001-09-15 19:06:58 +00:00
|
|
|
//for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
|
|
|
|
|
2001-11-13 23:09:30 +00:00
|
|
|
|
|
|
|
// Now replace set the registers for operands in the machine instruction
|
|
|
|
|
2001-09-15 19:06:58 +00:00
|
|
|
for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
|
|
|
|
|
|
|
MachineOperand& Op = MInst->getOperand(OpNum);
|
|
|
|
|
|
|
|
if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
|
|
|
Op.getOperandType() == MachineOperand::MO_CCRegister) {
|
|
|
|
|
|
|
|
const Value *const Val = Op.getVRegValue();
|
|
|
|
|
|
|
|
// delete this condition checking later (must assert if Val is null)
|
2001-09-19 16:26:23 +00:00
|
|
|
if( !Val) {
|
|
|
|
if (DEBUG_RA)
|
2001-10-16 01:23:19 +00:00
|
|
|
cout << "Warning: NULL Value found for operand" << endl;
|
2001-09-15 19:06:58 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
assert( Val && "Value is NULL");
|
|
|
|
|
2001-10-28 18:12:02 +00:00
|
|
|
LiveRange *const LR = LRI.getLiveRangeForValue(Val);
|
2001-09-15 19:06:58 +00:00
|
|
|
|
|
|
|
if ( !LR ) {
|
2001-09-18 22:43:57 +00:00
|
|
|
|
|
|
|
// nothing to worry if it's a const or a label
|
|
|
|
|
2001-09-19 16:09:04 +00:00
|
|
|
if (DEBUG_RA) {
|
2001-10-16 16:34:44 +00:00
|
|
|
cout << "*NO LR for operand : " << Op ;
|
|
|
|
cout << " [reg:" << Op.getAllocatedRegNum() << "]";
|
|
|
|
cout << " in inst:\t" << *MInst << endl;
|
2001-09-19 16:09:04 +00:00
|
|
|
}
|
2001-09-18 22:43:57 +00:00
|
|
|
|
2001-10-16 01:23:19 +00:00
|
|
|
// if register is not allocated, mark register as invalid
|
2001-10-15 16:26:38 +00:00
|
|
|
if( Op.getAllocatedRegNum() == -1)
|
2001-10-16 01:23:19 +00:00
|
|
|
Op.setRegForValue( MRI.getInvalidRegNum());
|
2001-09-18 22:43:57 +00:00
|
|
|
|
2001-09-30 23:11:59 +00:00
|
|
|
|
2001-09-15 19:06:58 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned RCID = (LR->getRegClass())->getID();
|
|
|
|
|
2001-10-28 18:12:02 +00:00
|
|
|
if( LR->hasColor() ) {
|
|
|
|
Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
|
|
|
|
// LR did NOT receive a color (register). Now, insert spill code
|
|
|
|
// for spilled opeands in this machine instruction
|
2001-09-15 19:06:58 +00:00
|
|
|
|
2001-11-08 16:43:25 +00:00
|
|
|
//assert(0 && "LR must be spilled");
|
|
|
|
insertCode4SpilledLR(LR, MInst, *BBI, OpNum );
|
2001-09-15 19:06:58 +00:00
|
|
|
|
2001-10-28 18:12:02 +00:00
|
|
|
}
|
2001-09-18 22:43:57 +00:00
|
|
|
}
|
|
|
|
|
2001-10-16 01:23:19 +00:00
|
|
|
} // for each operand
|
|
|
|
|
|
|
|
|
2001-11-13 23:09:30 +00:00
|
|
|
// If there are instructions to be added, *before* this machine
|
|
|
|
// instruction, add them now.
|
|
|
|
|
|
|
|
if( AddedInstrMap[ MInst ] ) {
|
|
|
|
|
|
|
|
deque<MachineInstr *> &IBef = (AddedInstrMap[MInst])->InstrnsBefore;
|
|
|
|
|
|
|
|
if( ! IBef.empty() ) {
|
|
|
|
|
|
|
|
deque<MachineInstr *>::iterator AdIt;
|
|
|
|
|
|
|
|
for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
|
|
|
|
|
|
|
|
if( DEBUG_RA) {
|
|
|
|
cerr << "For inst " << *MInst;
|
|
|
|
cerr << " PREPENDed instr: " << **AdIt << endl;
|
|
|
|
}
|
|
|
|
|
|
|
|
MInstIterator = MIVec.insert( MInstIterator, *AdIt );
|
|
|
|
++MInstIterator;
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2001-10-16 01:23:19 +00:00
|
|
|
// If there are instructions to be added *after* this machine
|
|
|
|
// instruction, add them now
|
|
|
|
|
2001-10-23 21:38:00 +00:00
|
|
|
if( AddedInstrMap[ MInst ] &&
|
|
|
|
! (AddedInstrMap[ MInst ]->InstrnsAfter).empty() ) {
|
2001-10-16 01:23:19 +00:00
|
|
|
|
2001-10-23 21:38:00 +00:00
|
|
|
// if there are delay slots for this instruction, the instructions
|
|
|
|
// added after it must really go after the delayed instruction(s)
|
|
|
|
// So, we move the InstrAfter of the current instruction to the
|
|
|
|
// corresponding delayed instruction
|
|
|
|
|
|
|
|
unsigned delay;
|
|
|
|
if((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
|
|
|
|
move2DelayedInstr(MInst, *(MInstIterator+delay) );
|
2001-10-16 01:23:19 +00:00
|
|
|
|
2001-10-23 21:38:00 +00:00
|
|
|
if(DEBUG_RA) cout<< "\nMoved an added instr after the delay slot";
|
|
|
|
}
|
|
|
|
|
|
|
|
else {
|
|
|
|
|
2001-10-16 01:23:19 +00:00
|
|
|
|
2001-10-23 21:38:00 +00:00
|
|
|
// Here we can add the "instructions after" to the current
|
|
|
|
// instruction since there are no delay slots for this instruction
|
2001-10-16 01:23:19 +00:00
|
|
|
|
2001-10-23 21:38:00 +00:00
|
|
|
deque<MachineInstr *> &IAft = (AddedInstrMap[MInst])->InstrnsAfter;
|
|
|
|
|
|
|
|
if( ! IAft.empty() ) {
|
|
|
|
|
|
|
|
deque<MachineInstr *>::iterator AdIt;
|
|
|
|
|
|
|
|
++MInstIterator; // advance to the next instruction
|
|
|
|
|
|
|
|
for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
|
|
|
|
|
2001-11-13 23:09:30 +00:00
|
|
|
if(DEBUG_RA) {
|
|
|
|
cerr << "For inst " << *MInst;
|
2001-11-09 23:49:42 +00:00
|
|
|
cerr << " APPENDed instr: " << **AdIt << endl;
|
2001-11-13 23:09:30 +00:00
|
|
|
}
|
|
|
|
|
2001-10-23 21:38:00 +00:00
|
|
|
MInstIterator = MIVec.insert( MInstIterator, *AdIt );
|
|
|
|
++MInstIterator;
|
|
|
|
}
|
2001-10-16 01:23:19 +00:00
|
|
|
|
2001-10-23 21:38:00 +00:00
|
|
|
// MInsterator already points to the next instr. Since the
|
|
|
|
// for loop also increments it, decrement it to point to the
|
|
|
|
// instruction added last
|
|
|
|
--MInstIterator;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
} // if not delay
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
} // for each machine instruction
|
|
|
|
}
|
|
|
|
}
|
2001-10-16 01:23:19 +00:00
|
|
|
|
2001-10-18 22:36:26 +00:00
|
|
|
|
2001-11-08 16:43:25 +00:00
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// This method inserts spill code for AN operand whose LR was spilled.
|
|
|
|
// This method may be called several times for a single machine instruction
|
|
|
|
// if it contains many spilled operands. Each time it is called, it finds
|
|
|
|
// a register which is not live at that instruction and also which is not
|
|
|
|
// used by other spilled operands of the same instruction. Then it uses
|
|
|
|
// this register temporarily to accomodate the spilled value.
|
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
|
|
|
|
MachineInstr *MInst,
|
|
|
|
const BasicBlock *BB,
|
|
|
|
const unsigned OpNum) {
|
|
|
|
|
2001-11-15 20:23:19 +00:00
|
|
|
assert(! TM.getInstrInfo().isCall(MInst->getOpCode()) &&
|
|
|
|
(! TM.getInstrInfo().isReturn(MInst->getOpCode())) &&
|
|
|
|
"Arg of a call/ret must be handled elsewhere");
|
|
|
|
|
2001-11-08 16:43:25 +00:00
|
|
|
MachineOperand& Op = MInst->getOperand(OpNum);
|
|
|
|
bool isDef = MInst->operandIsDefined(OpNum);
|
|
|
|
unsigned RegType = MRI.getRegType( LR );
|
|
|
|
int SpillOff = LR->getSpillOffFromFP();
|
|
|
|
RegClass *RC = LR->getRegClass();
|
|
|
|
const LiveVarSet *LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
|
2001-11-12 23:26:35 +00:00
|
|
|
|
|
|
|
/**** NOTE: THIS SHOULD USE THE RIGHT SIZE FOR THE REG BEING PUSHED ****/
|
2001-11-08 16:43:25 +00:00
|
|
|
int TmpOff =
|
2001-11-12 23:26:35 +00:00
|
|
|
mcInfo.pushTempValue(TM, 8 /* TM.findOptimalStorageSize(LR->getType()) */);
|
2001-11-08 16:43:25 +00:00
|
|
|
|
2001-11-08 19:11:30 +00:00
|
|
|
MachineInstr *MIBef=NULL, *AdIMid=NULL, *MIAft=NULL;
|
2001-11-15 20:23:19 +00:00
|
|
|
|
|
|
|
int TmpRegU = getUsableUniRegAtMI(RC, RegType, MInst,LVSetBef, MIBef, MIAft);
|
|
|
|
|
2001-11-08 19:11:30 +00:00
|
|
|
// get the added instructions for this instruciton
|
|
|
|
AddedInstrns *AI = AddedInstrMap[ MInst ];
|
|
|
|
if ( !AI ) {
|
|
|
|
AI = new AddedInstrns();
|
|
|
|
AddedInstrMap[ MInst ] = AI;
|
|
|
|
}
|
|
|
|
|
2001-11-15 20:23:19 +00:00
|
|
|
|
2001-11-08 16:43:25 +00:00
|
|
|
if( !isDef ) {
|
|
|
|
|
|
|
|
// for a USE, we have to load the value of LR from stack to a TmpReg
|
|
|
|
// and use the TmpReg as one operand of instruction
|
|
|
|
|
|
|
|
// actual loading instruction
|
2001-11-15 20:23:19 +00:00
|
|
|
AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpRegU,RegType);
|
2001-11-08 16:43:25 +00:00
|
|
|
|
|
|
|
if( MIBef )
|
2001-11-08 19:11:30 +00:00
|
|
|
(AI->InstrnsBefore).push_back(MIBef);
|
2001-11-08 16:43:25 +00:00
|
|
|
|
2001-11-08 19:11:30 +00:00
|
|
|
(AI->InstrnsBefore).push_back(AdIMid);
|
2001-11-08 16:43:25 +00:00
|
|
|
|
|
|
|
if( MIAft)
|
2001-11-08 19:11:30 +00:00
|
|
|
(AI->InstrnsAfter).push_front(MIAft);
|
|
|
|
|
2001-11-08 16:43:25 +00:00
|
|
|
|
|
|
|
}
|
|
|
|
else { // if this is a Def
|
|
|
|
|
|
|
|
// for a DEF, we have to store the value produced by this instruction
|
|
|
|
// on the stack position allocated for this LR
|
|
|
|
|
|
|
|
// actual storing instruction
|
2001-11-15 20:23:19 +00:00
|
|
|
AdIMid = MRI.cpReg2MemMI(TmpRegU, MRI.getFramePointer(), SpillOff,RegType);
|
2001-11-08 16:43:25 +00:00
|
|
|
|
|
|
|
if( MIBef )
|
2001-11-08 19:11:30 +00:00
|
|
|
(AI->InstrnsBefore).push_back(MIBef);
|
2001-11-08 16:43:25 +00:00
|
|
|
|
2001-11-13 23:09:30 +00:00
|
|
|
(AI->InstrnsAfter).push_front(AdIMid);
|
2001-11-08 16:43:25 +00:00
|
|
|
|
|
|
|
if( MIAft)
|
2001-11-08 19:11:30 +00:00
|
|
|
(AI->InstrnsAfter).push_front(MIAft);
|
2001-11-08 16:43:25 +00:00
|
|
|
|
|
|
|
} // if !DEF
|
|
|
|
|
|
|
|
cerr << "\nFor Inst " << *MInst;
|
2001-11-10 21:21:36 +00:00
|
|
|
cerr << " - SPILLED LR: "; LR->printSet();
|
2001-11-08 16:43:25 +00:00
|
|
|
cerr << "\n - Added Instructions:";
|
|
|
|
if( MIBef ) cerr << *MIBef;
|
|
|
|
cerr << *AdIMid;
|
|
|
|
if( MIAft ) cerr << *MIAft;
|
|
|
|
|
2001-11-15 20:23:19 +00:00
|
|
|
Op.setRegForValue( TmpRegU ); // set the opearnd
|
2001-11-08 16:43:25 +00:00
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2001-10-28 18:12:02 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// We can use the following method to get a temporary register to be used
|
|
|
|
// BEFORE any given machine instruction. If there is a register available,
|
|
|
|
// this method will simply return that register and set MIBef = MIAft = NULL.
|
|
|
|
// Otherwise, it will return a register and MIAft and MIBef will contain
|
|
|
|
// two instructions used to free up this returned register.
|
2001-11-03 20:41:22 +00:00
|
|
|
// Returned register number is the UNIFIED register number
|
2001-10-28 18:12:02 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
|
2001-11-15 20:23:19 +00:00
|
|
|
int PhyRegAlloc::getUsableUniRegAtMI(RegClass *RC,
|
2001-10-28 18:12:02 +00:00
|
|
|
const int RegType,
|
|
|
|
const MachineInstr *MInst,
|
|
|
|
const LiveVarSet *LVSetBef,
|
|
|
|
MachineInstr *MIBef,
|
|
|
|
MachineInstr *MIAft) {
|
|
|
|
|
2001-11-15 20:23:19 +00:00
|
|
|
int RegU = getUnusedUniRegAtMI(RC, MInst, LVSetBef);
|
|
|
|
|
2001-10-28 18:12:02 +00:00
|
|
|
|
2001-11-15 20:23:19 +00:00
|
|
|
if( RegU != -1) {
|
2001-11-15 15:00:53 +00:00
|
|
|
// we found an unused register, so we can simply use it
|
2001-10-28 18:12:02 +00:00
|
|
|
MIBef = MIAft = NULL;
|
|
|
|
}
|
|
|
|
else {
|
2001-11-03 20:41:22 +00:00
|
|
|
// we couldn't find an unused register. Generate code to free up a reg by
|
2001-10-28 18:12:02 +00:00
|
|
|
// saving it on stack and restoring after the instruction
|
|
|
|
|
2001-11-08 04:48:50 +00:00
|
|
|
/**** NOTE: THIS SHOULD USE THE RIGHT SIZE FOR THE REG BEING PUSHED ****/
|
|
|
|
int TmpOff = mcInfo.pushTempValue(TM, /*size*/ 8);
|
|
|
|
|
2001-11-15 20:23:19 +00:00
|
|
|
RegU = getUniRegNotUsedByThisInst(RC, MInst);
|
|
|
|
MIBef = MRI.cpReg2MemMI(RegU, MRI.getFramePointer(), TmpOff, RegType );
|
|
|
|
MIAft = MRI.cpMem2RegMI(MRI.getFramePointer(), TmpOff, RegU, RegType );
|
2001-10-28 18:12:02 +00:00
|
|
|
}
|
|
|
|
|
2001-11-15 20:23:19 +00:00
|
|
|
return RegU;
|
2001-10-28 18:12:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// This method is called to get a new unused register that can be used to
|
|
|
|
// accomodate a spilled value.
|
|
|
|
// This method may be called several times for a single machine instruction
|
|
|
|
// if it contains many spilled operands. Each time it is called, it finds
|
|
|
|
// a register which is not live at that instruction and also which is not
|
|
|
|
// used by other spilled operands of the same instruction.
|
2001-11-03 20:41:22 +00:00
|
|
|
// Return register number is relative to the register class. NOT
|
|
|
|
// unified number
|
2001-10-28 18:12:02 +00:00
|
|
|
//----------------------------------------------------------------------------
|
2001-11-15 20:23:19 +00:00
|
|
|
int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
|
2001-10-28 18:12:02 +00:00
|
|
|
const MachineInstr *MInst,
|
|
|
|
const LiveVarSet *LVSetBef) {
|
|
|
|
|
|
|
|
unsigned NumAvailRegs = RC->getNumOfAvailRegs();
|
|
|
|
|
|
|
|
bool *IsColorUsedArr = RC->getIsColorUsedArr();
|
|
|
|
|
2001-11-15 20:23:19 +00:00
|
|
|
for(unsigned i=0; i < NumAvailRegs; i++) // Reset array
|
2001-10-28 18:12:02 +00:00
|
|
|
IsColorUsedArr[i] = false;
|
|
|
|
|
|
|
|
LiveVarSet::const_iterator LIt = LVSetBef->begin();
|
|
|
|
|
|
|
|
// for each live var in live variable set after machine inst
|
|
|
|
for( ; LIt != LVSetBef->end(); ++LIt) {
|
|
|
|
|
|
|
|
// get the live range corresponding to live var
|
|
|
|
LiveRange *const LRofLV = LRI.getLiveRangeForValue(*LIt );
|
|
|
|
|
|
|
|
// LR can be null if it is a const since a const
|
|
|
|
// doesn't have a dominating def - see Assumptions above
|
|
|
|
if( LRofLV )
|
|
|
|
if( LRofLV->hasColor() )
|
|
|
|
IsColorUsedArr[ LRofLV->getColor() ] = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// It is possible that one operand of this MInst was already spilled
|
|
|
|
// and it received some register temporarily. If that's the case,
|
|
|
|
// it is recorded in machine operand. We must skip such registers.
|
|
|
|
|
2001-11-15 20:23:19 +00:00
|
|
|
setRelRegsUsedByThisInst(RC, MInst);
|
2001-10-28 18:12:02 +00:00
|
|
|
|
|
|
|
unsigned c; // find first unused color
|
|
|
|
for( c=0; c < NumAvailRegs; c++)
|
|
|
|
if( ! IsColorUsedArr[ c ] ) break;
|
|
|
|
|
|
|
|
if(c < NumAvailRegs)
|
2001-11-15 20:23:19 +00:00
|
|
|
return MRI.getUnifiedRegNum(RC->getID(), c);
|
2001-10-28 18:12:02 +00:00
|
|
|
else
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2001-11-15 20:23:19 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// Get any other register in a register class, other than what is used
|
|
|
|
// by operands of a machine instruction. Returns the unified reg number.
|
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
|
|
|
|
const MachineInstr *MInst) {
|
|
|
|
|
|
|
|
bool *IsColorUsedArr = RC->getIsColorUsedArr();
|
|
|
|
unsigned NumAvailRegs = RC->getNumOfAvailRegs();
|
|
|
|
|
|
|
|
|
|
|
|
for(unsigned i=0; i < NumAvailRegs ; i++) // Reset array
|
|
|
|
IsColorUsedArr[i] = false;
|
|
|
|
|
|
|
|
setRelRegsUsedByThisInst(RC, MInst);
|
|
|
|
|
|
|
|
unsigned c; // find first unused color
|
|
|
|
for( c=0; c < RC->getNumOfAvailRegs(); c++)
|
|
|
|
if( ! IsColorUsedArr[ c ] ) break;
|
|
|
|
|
|
|
|
if(c < NumAvailRegs)
|
|
|
|
return MRI.getUnifiedRegNum(RC->getID(), c);
|
|
|
|
else
|
|
|
|
assert( 0 && "FATAL: No free register could be found in reg class!!");
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2001-10-28 18:12:02 +00:00
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// This method modifies the IsColorUsedArr of the register class passed to it.
|
|
|
|
// It sets the bits corresponding to the registers used by this machine
|
2001-11-15 15:00:53 +00:00
|
|
|
// instructions. Both explicit and implicit operands are set.
|
2001-10-28 18:12:02 +00:00
|
|
|
//----------------------------------------------------------------------------
|
2001-11-15 20:23:19 +00:00
|
|
|
void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
|
2001-10-28 18:12:02 +00:00
|
|
|
const MachineInstr *MInst ) {
|
|
|
|
|
|
|
|
bool *IsColorUsedArr = RC->getIsColorUsedArr();
|
|
|
|
|
|
|
|
for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
|
|
|
|
|
|
|
const MachineOperand& Op = MInst->getOperand(OpNum);
|
|
|
|
|
|
|
|
if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
2001-11-15 15:00:53 +00:00
|
|
|
Op.getOperandType() == MachineOperand::MO_CCRegister ) {
|
2001-10-28 18:12:02 +00:00
|
|
|
|
|
|
|
const Value *const Val = Op.getVRegValue();
|
|
|
|
|
2001-11-15 20:23:19 +00:00
|
|
|
if( Val )
|
|
|
|
if( MRI.getRegClassIDOfValue(Val) == RC->getID() ) {
|
2001-10-28 18:12:02 +00:00
|
|
|
int Reg;
|
2001-11-15 15:00:53 +00:00
|
|
|
if( (Reg=Op.getAllocatedRegNum()) != -1) {
|
2001-10-28 18:12:02 +00:00
|
|
|
IsColorUsedArr[ Reg ] = true;
|
2001-11-15 15:00:53 +00:00
|
|
|
}
|
|
|
|
else {
|
|
|
|
// it is possilbe that this operand still is not marked with
|
|
|
|
// a register but it has a LR and that received a color
|
|
|
|
|
|
|
|
LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
|
|
|
|
if( LROfVal)
|
|
|
|
if( LROfVal->hasColor() )
|
|
|
|
IsColorUsedArr[ LROfVal->getColor() ] = true;
|
|
|
|
}
|
2001-10-28 18:12:02 +00:00
|
|
|
|
2001-11-15 15:00:53 +00:00
|
|
|
} // if reg classes are the same
|
|
|
|
}
|
|
|
|
else if (Op.getOperandType() == MachineOperand::MO_MachineRegister) {
|
|
|
|
IsColorUsedArr[ Op.getMachineRegNum() ] = true;
|
2001-10-28 18:12:02 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// If there are implicit references, mark them as well
|
|
|
|
|
|
|
|
for(unsigned z=0; z < MInst->getNumImplicitRefs(); z++) {
|
|
|
|
|
|
|
|
LiveRange *const LRofImpRef =
|
|
|
|
LRI.getLiveRangeForValue( MInst->getImplicitRef(z) );
|
|
|
|
|
|
|
|
if( LRofImpRef )
|
|
|
|
if( LRofImpRef->hasColor() )
|
|
|
|
IsColorUsedArr[ LRofImpRef->getColor() ] = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2001-10-23 21:38:00 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// If there are delay slots for an instruction, the instructions
|
|
|
|
// added after it must really go after the delayed instruction(s).
|
|
|
|
// So, we move the InstrAfter of that instruction to the
|
|
|
|
// corresponding delayed instruction using the following method.
|
2001-10-16 01:23:19 +00:00
|
|
|
|
2001-10-23 21:38:00 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
void PhyRegAlloc:: move2DelayedInstr(const MachineInstr *OrigMI,
|
|
|
|
const MachineInstr *DelayedMI) {
|
2001-10-16 01:23:19 +00:00
|
|
|
|
|
|
|
|
2001-10-23 21:38:00 +00:00
|
|
|
// "added after" instructions of the original instr
|
|
|
|
deque<MachineInstr *> &OrigAft = (AddedInstrMap[OrigMI])->InstrnsAfter;
|
2001-09-15 19:06:58 +00:00
|
|
|
|
2001-10-23 21:38:00 +00:00
|
|
|
// "added instructions" of the delayed instr
|
|
|
|
AddedInstrns *DelayAdI = AddedInstrMap[DelayedMI];
|
|
|
|
|
|
|
|
if(! DelayAdI ) { // create a new "added after" if necessary
|
|
|
|
DelayAdI = new AddedInstrns();
|
|
|
|
AddedInstrMap[DelayedMI] = DelayAdI;
|
2001-09-15 19:06:58 +00:00
|
|
|
}
|
|
|
|
|
2001-10-23 21:38:00 +00:00
|
|
|
// "added after" instructions of the delayed instr
|
|
|
|
deque<MachineInstr *> &DelayedAft = DelayAdI->InstrnsAfter;
|
2001-09-15 19:06:58 +00:00
|
|
|
|
2001-10-23 21:38:00 +00:00
|
|
|
// go thru all the "added after instructions" of the original instruction
|
|
|
|
// and append them to the "addded after instructions" of the delayed
|
|
|
|
// instructions
|
2001-09-15 19:06:58 +00:00
|
|
|
|
2001-10-23 21:38:00 +00:00
|
|
|
deque<MachineInstr *>::iterator OrigAdIt;
|
|
|
|
|
|
|
|
for( OrigAdIt = OrigAft.begin(); OrigAdIt != OrigAft.end() ; ++OrigAdIt ) {
|
|
|
|
DelayedAft.push_back( *OrigAdIt );
|
|
|
|
}
|
|
|
|
|
|
|
|
// empty the "added after instructions" of the original instruction
|
|
|
|
OrigAft.clear();
|
|
|
|
|
|
|
|
}
|
2001-09-15 19:06:58 +00:00
|
|
|
|
2001-09-15 21:11:11 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// This method prints the code with registers after register allocation is
|
|
|
|
// complete.
|
|
|
|
//----------------------------------------------------------------------------
|
2001-09-15 19:06:58 +00:00
|
|
|
void PhyRegAlloc::printMachineCode()
|
|
|
|
{
|
|
|
|
|
2001-10-16 01:23:19 +00:00
|
|
|
cout << endl << ";************** Method ";
|
|
|
|
cout << Meth->getName() << " *****************" << endl;
|
2001-09-15 19:06:58 +00:00
|
|
|
|
|
|
|
Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
|
|
|
|
|
|
|
|
for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
|
|
|
|
|
2001-10-16 01:23:19 +00:00
|
|
|
cout << endl ; printLabel( *BBI); cout << ": ";
|
2001-09-14 21:18:34 +00:00
|
|
|
|
|
|
|
// get the iterator for machine instructions
|
|
|
|
MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
|
|
|
|
MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
|
|
|
|
|
|
|
|
// iterate over all the machine instructions in BB
|
|
|
|
for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
|
|
|
|
|
|
|
|
MachineInstr *const MInst = *MInstIterator;
|
|
|
|
|
2001-09-15 19:06:58 +00:00
|
|
|
|
2001-10-16 01:23:19 +00:00
|
|
|
cout << endl << "\t";
|
|
|
|
cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
|
2001-09-15 19:06:58 +00:00
|
|
|
|
2001-09-14 21:18:34 +00:00
|
|
|
|
|
|
|
//for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
|
|
|
|
|
|
|
|
for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
|
|
|
|
|
|
|
MachineOperand& Op = MInst->getOperand(OpNum);
|
|
|
|
|
|
|
|
if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
2001-10-18 22:36:26 +00:00
|
|
|
Op.getOperandType() == MachineOperand::MO_CCRegister /*||
|
|
|
|
Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
|
2001-09-14 21:18:34 +00:00
|
|
|
|
2001-09-18 22:43:57 +00:00
|
|
|
const Value *const Val = Op.getVRegValue () ;
|
2001-09-15 21:11:11 +00:00
|
|
|
// ****this code is temporary till NULL Values are fixed
|
2001-09-18 22:43:57 +00:00
|
|
|
if( ! Val ) {
|
2001-10-16 01:23:19 +00:00
|
|
|
cout << "\t<*NULL*>";
|
2001-09-14 21:18:34 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2001-09-18 22:43:57 +00:00
|
|
|
// if a label or a constant
|
2001-09-30 23:11:59 +00:00
|
|
|
if( (Val->getValueType() == Value::BasicBlockVal) ) {
|
2001-09-14 21:18:34 +00:00
|
|
|
|
2001-10-16 01:23:19 +00:00
|
|
|
cout << "\t"; printLabel( Op.getVRegValue () );
|
2001-09-15 19:06:58 +00:00
|
|
|
}
|
2001-09-18 22:43:57 +00:00
|
|
|
else {
|
|
|
|
// else it must be a register value
|
|
|
|
const int RegNum = Op.getAllocatedRegNum();
|
|
|
|
|
2001-10-19 21:39:31 +00:00
|
|
|
cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
|
2001-11-15 20:23:19 +00:00
|
|
|
if (Val->hasName() )
|
|
|
|
cout << "(" << Val->getName() << ")";
|
|
|
|
else
|
|
|
|
cout << "(" << Val << ")";
|
|
|
|
|
|
|
|
if( Op.opIsDef() )
|
|
|
|
cout << "*";
|
|
|
|
|
|
|
|
const LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
|
|
|
|
if( LROfVal )
|
|
|
|
if( LROfVal->hasSpillOffset() )
|
|
|
|
cout << "$";
|
2001-09-18 22:43:57 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
|
2001-10-16 01:23:19 +00:00
|
|
|
cout << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
|
2001-09-15 19:06:58 +00:00
|
|
|
}
|
|
|
|
|
2001-09-14 21:18:34 +00:00
|
|
|
else
|
2001-10-16 01:23:19 +00:00
|
|
|
cout << "\t" << Op; // use dump field
|
2001-09-14 21:18:34 +00:00
|
|
|
}
|
|
|
|
|
2001-10-16 01:23:19 +00:00
|
|
|
|
2001-09-15 19:06:58 +00:00
|
|
|
|
2001-10-16 01:23:19 +00:00
|
|
|
unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
|
|
|
|
if( NumOfImpRefs > 0 ) {
|
|
|
|
|
|
|
|
cout << "\tImplicit:";
|
2001-09-15 19:06:58 +00:00
|
|
|
|
2001-10-16 01:23:19 +00:00
|
|
|
for(unsigned z=0; z < NumOfImpRefs; z++) {
|
|
|
|
printValue( MInst->getImplicitRef(z) );
|
|
|
|
cout << "\t";
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
} // for all machine instructions
|
|
|
|
|
|
|
|
|
|
|
|
cout << endl;
|
|
|
|
|
|
|
|
} // for all BBs
|
2001-09-15 19:06:58 +00:00
|
|
|
|
2001-10-16 01:23:19 +00:00
|
|
|
cout << endl;
|
2001-09-14 21:18:34 +00:00
|
|
|
}
|
|
|
|
|
2001-09-18 22:43:57 +00:00
|
|
|
|
2001-09-30 23:11:59 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
//
|
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
void PhyRegAlloc::colorCallRetArgs()
|
|
|
|
{
|
|
|
|
|
|
|
|
CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
|
|
|
|
CallRetInstrListType::const_iterator It = CallRetInstList.begin();
|
|
|
|
|
|
|
|
for( ; It != CallRetInstList.end(); ++It ) {
|
|
|
|
|
2001-10-15 16:26:38 +00:00
|
|
|
const MachineInstr *const CRMI = *It;
|
|
|
|
unsigned OpCode = CRMI->getOpCode();
|
2001-09-30 23:11:59 +00:00
|
|
|
|
|
|
|
// get the added instructions for this Call/Ret instruciton
|
|
|
|
AddedInstrns *AI = AddedInstrMap[ CRMI ];
|
|
|
|
if ( !AI ) {
|
|
|
|
AI = new AddedInstrns();
|
|
|
|
AddedInstrMap[ CRMI ] = AI;
|
|
|
|
}
|
|
|
|
|
2001-10-28 18:12:02 +00:00
|
|
|
// Tmp stack poistions are needed by some calls that have spilled args
|
|
|
|
// So reset it before we call each such method
|
2001-11-15 22:02:06 +00:00
|
|
|
//mcInfo.popAllTempValues(TM);
|
|
|
|
|
|
|
|
|
2001-11-08 04:48:50 +00:00
|
|
|
|
2001-10-15 16:26:38 +00:00
|
|
|
if( (TM.getInstrInfo()).isCall( OpCode ) )
|
2001-10-28 18:12:02 +00:00
|
|
|
MRI.colorCallArgs( CRMI, LRI, AI, *this );
|
2001-09-30 23:11:59 +00:00
|
|
|
|
2001-10-15 16:26:38 +00:00
|
|
|
else if ( (TM.getInstrInfo()).isReturn(OpCode) )
|
|
|
|
MRI.colorRetValue( CRMI, LRI, AI );
|
2001-09-30 23:11:59 +00:00
|
|
|
|
|
|
|
else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" );
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2001-10-19 21:39:31 +00:00
|
|
|
|
|
|
|
|
2001-09-30 23:11:59 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
void PhyRegAlloc::colorIncomingArgs()
|
|
|
|
{
|
|
|
|
const BasicBlock *const FirstBB = Meth->front();
|
|
|
|
const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin());
|
|
|
|
assert( FirstMI && "No machine instruction in entry BB");
|
|
|
|
|
|
|
|
AddedInstrns *AI = AddedInstrMap[ FirstMI ];
|
|
|
|
if ( !AI ) {
|
|
|
|
AI = new AddedInstrns();
|
|
|
|
AddedInstrMap[ FirstMI ] = AI;
|
|
|
|
}
|
|
|
|
|
|
|
|
MRI.colorMethodArgs(Meth, LRI, AI );
|
|
|
|
}
|
|
|
|
|
2001-09-18 22:43:57 +00:00
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// Used to generate a label for a basic block
|
|
|
|
//----------------------------------------------------------------------------
|
2001-09-15 19:06:58 +00:00
|
|
|
void PhyRegAlloc::printLabel(const Value *const Val)
|
|
|
|
{
|
|
|
|
if( Val->hasName() )
|
2001-10-16 01:23:19 +00:00
|
|
|
cout << Val->getName();
|
2001-09-15 19:06:58 +00:00
|
|
|
else
|
2001-10-16 01:23:19 +00:00
|
|
|
cout << "Label" << Val;
|
2001-09-15 19:06:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2001-10-19 21:39:31 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// This method calls setSugColorUsable method of each live range. This
|
|
|
|
// will determine whether the suggested color of LR is really usable.
|
|
|
|
// A suggested color is not usable when the suggested color is volatile
|
|
|
|
// AND when there are call interferences
|
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
void PhyRegAlloc::markUnusableSugColors()
|
|
|
|
{
|
2001-10-28 18:12:02 +00:00
|
|
|
if(DEBUG_RA ) cout << "\nmarking unusable suggested colors ..." << endl;
|
2001-10-19 21:39:31 +00:00
|
|
|
|
|
|
|
// hash map iterator
|
|
|
|
LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
|
|
|
|
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
|
|
|
|
|
|
|
|
for( ; HMI != HMIEnd ; ++HMI ) {
|
|
|
|
|
|
|
|
if( (*HMI).first ) {
|
|
|
|
|
|
|
|
LiveRange *L = (*HMI).second; // get the LiveRange
|
|
|
|
|
|
|
|
if(L) {
|
|
|
|
if( L->hasSuggestedColor() ) {
|
|
|
|
|
|
|
|
int RCID = (L->getRegClass())->getID();
|
|
|
|
if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
|
|
|
|
L->isCallInterference() )
|
|
|
|
L->setSuggestedColorUsable( false );
|
|
|
|
else
|
|
|
|
L->setSuggestedColorUsable( true );
|
|
|
|
}
|
|
|
|
} // if L->hasSuggestedColor()
|
|
|
|
}
|
|
|
|
} // for all LR's in hash map
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
2001-10-28 18:12:02 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// The following method will set the stack offsets of the live ranges that
|
|
|
|
// are decided to be spillled. This must be called just after coloring the
|
|
|
|
// LRs using the graph coloring algo. For each live range that is spilled,
|
|
|
|
// this method allocate a new spill position on the stack.
|
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
void PhyRegAlloc::allocateStackSpace4SpilledLRs()
|
|
|
|
{
|
|
|
|
if(DEBUG_RA ) cout << "\nsetting LR stack offsets ..." << endl;
|
|
|
|
|
|
|
|
// hash map iterator
|
|
|
|
LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
|
|
|
|
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
|
|
|
|
|
|
|
|
for( ; HMI != HMIEnd ; ++HMI ) {
|
|
|
|
if( (*HMI).first ) {
|
|
|
|
LiveRange *L = (*HMI).second; // get the LiveRange
|
|
|
|
if(L)
|
|
|
|
if( ! L->hasColor() )
|
2001-11-12 23:40:22 +00:00
|
|
|
/**** NOTE: THIS SHOULD USE THE RIGHT SIZE FOR THE REG BEING PUSHED ****/
|
|
|
|
L->setSpillOffFromFP(mcInfo.allocateSpilledValue(TM, Type::LongTy /*L->getType()*/ ));
|
2001-10-28 18:12:02 +00:00
|
|
|
}
|
|
|
|
} // for all LR's in hash map
|
|
|
|
}
|
2001-10-19 21:39:31 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
2001-09-18 22:43:57 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// The entry pont to Register Allocation
|
|
|
|
//----------------------------------------------------------------------------
|
2001-09-14 21:18:34 +00:00
|
|
|
|
|
|
|
void PhyRegAlloc::allocateRegisters()
|
|
|
|
{
|
2001-09-30 23:11:59 +00:00
|
|
|
|
|
|
|
// make sure that we put all register classes into the RegClassList
|
|
|
|
// before we call constructLiveRanges (now done in the constructor of
|
|
|
|
// PhyRegAlloc class).
|
|
|
|
|
2001-09-14 21:18:34 +00:00
|
|
|
constructLiveRanges(); // create LR info
|
|
|
|
|
2001-09-30 23:11:59 +00:00
|
|
|
if( DEBUG_RA )
|
2001-09-14 21:18:34 +00:00
|
|
|
LRI.printLiveRanges();
|
2001-09-30 23:11:59 +00:00
|
|
|
|
2001-09-14 21:18:34 +00:00
|
|
|
createIGNodeListsAndIGs(); // create IGNode list and IGs
|
|
|
|
|
|
|
|
buildInterferenceGraphs(); // build IGs in all reg classes
|
|
|
|
|
2001-09-30 23:11:59 +00:00
|
|
|
|
|
|
|
if( DEBUG_RA ) {
|
2001-09-14 21:18:34 +00:00
|
|
|
// print all LRs in all reg classes
|
|
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
|
|
RegClassList[ rc ]->printIGNodeList();
|
2001-09-30 23:11:59 +00:00
|
|
|
|
2001-09-14 21:18:34 +00:00
|
|
|
// print IGs in all register classes
|
|
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
|
|
RegClassList[ rc ]->printIG();
|
|
|
|
}
|
2001-09-30 23:11:59 +00:00
|
|
|
|
2001-09-14 21:18:34 +00:00
|
|
|
LRI.coalesceLRs(); // coalesce all live ranges
|
2001-09-30 23:11:59 +00:00
|
|
|
|
2001-11-03 17:13:27 +00:00
|
|
|
// coalscing could not get rid of all phi's, add phi elimination
|
|
|
|
// instructions
|
|
|
|
// insertPhiEleminateInstrns();
|
|
|
|
|
2001-09-14 21:18:34 +00:00
|
|
|
if( DEBUG_RA) {
|
|
|
|
// print all LRs in all reg classes
|
|
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
|
|
RegClassList[ rc ]->printIGNodeList();
|
2001-09-30 23:11:59 +00:00
|
|
|
|
2001-09-14 21:18:34 +00:00
|
|
|
// print IGs in all register classes
|
|
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
|
|
RegClassList[ rc ]->printIG();
|
|
|
|
}
|
|
|
|
|
2001-10-19 21:39:31 +00:00
|
|
|
|
|
|
|
// mark un-usable suggested color before graph coloring algorithm.
|
|
|
|
// When this is done, the graph coloring algo will not reserve
|
|
|
|
// suggested color unnecessarily - they can be used by another LR
|
|
|
|
markUnusableSugColors();
|
|
|
|
|
|
|
|
// color all register classes using the graph coloring algo
|
2001-09-30 23:11:59 +00:00
|
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
|
|
RegClassList[ rc ]->colorAllRegs();
|
2001-09-18 22:43:57 +00:00
|
|
|
|
2001-10-28 18:12:02 +00:00
|
|
|
// Atter grpah coloring, if some LRs did not receive a color (i.e, spilled)
|
|
|
|
// a poistion for such spilled LRs
|
|
|
|
allocateStackSpace4SpilledLRs();
|
2001-09-18 22:43:57 +00:00
|
|
|
|
2001-11-15 22:02:06 +00:00
|
|
|
mcInfo.popAllTempValues(TM); // TODO **Check
|
|
|
|
|
2001-09-30 23:11:59 +00:00
|
|
|
// color incoming args and call args
|
|
|
|
colorIncomingArgs();
|
|
|
|
colorCallRetArgs();
|
2001-09-14 21:18:34 +00:00
|
|
|
|
2001-10-18 22:36:26 +00:00
|
|
|
|
2001-09-15 21:11:11 +00:00
|
|
|
updateMachineCode();
|
2001-09-19 16:26:23 +00:00
|
|
|
if (DEBUG_RA) {
|
2001-11-08 04:48:50 +00:00
|
|
|
MachineCodeForMethod::get(Meth).dump();
|
2001-09-19 16:26:23 +00:00
|
|
|
printMachineCode(); // only for DEBUGGING
|
|
|
|
}
|
2001-11-13 23:09:30 +00:00
|
|
|
|
2001-11-15 22:02:06 +00:00
|
|
|
|
|
|
|
|
|
|
|
/*
|
2001-11-15 20:23:19 +00:00
|
|
|
printMachineCode(); // only for DEBUGGING
|
|
|
|
|
|
|
|
cout << "\nAllocted for method " << Meth->getName();
|
|
|
|
char ch;
|
|
|
|
cin >> ch;
|
|
|
|
*/
|
2001-11-15 22:02:06 +00:00
|
|
|
|
2001-11-13 23:09:30 +00:00
|
|
|
|
2001-09-14 21:18:34 +00:00
|
|
|
}
|
|
|
|
|
2001-09-18 22:43:57 +00:00
|
|
|
|
|
|
|
|