Commit Graph

3658 Commits

Author SHA1 Message Date
Daniel Sanders
33550d78ea Merging r217432:
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r217432 | tomatabacu | 2014-09-09 11:15:38 +0100 (Tue, 09 Sep 2014) | 12 lines

[mips] Add assembler support for .set push/pop directive.

Summary:
These directives are used to save the current assembler options (in the case of ".set push") and restore the previously saved options (in the case of ".set pop").

Contains work done by Matheus Almeida.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4821
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@232082 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 19:12:54 +00:00
Hal Finkel
ce361cb525 Merging r222672:
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r222672 | uweigand | 2014-11-24 18:09:47 +0000 (Mon, 24 Nov 2014) | 10 lines

[PowerPC] Fix PR 21652 - copy st_other bits on symbol assignment

When processing an assignment in the integrated assembler that sets
a symbol to the value of another symbol, we need to copy the st_other
bits that encode the local entry point offset.

Modeled after MipsTargetELFStreamer::emitAssignment handling of the
ELF::STO_MIPS_MICROMIPS flag.


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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@223743 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-09 02:30:53 +00:00
Daniel Sanders
7bea0cea87 Merging r218745:
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r218745 | dsanders | 2014-10-01 09:26:55 +0100 (Wed, 01 Oct 2014) | 7 lines

[mips] Fix disassembly of [ls][wd]c[23], cache, and pref                          
                                                                                  
Fixes PR21015, and PR20993.                                                       
                                                                                  
Patch by Jun Koi


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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@222696 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 21:47:34 +00:00
Bill Wendling
7f154753ce Merging r213665:
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r213665 | tnorthover | 2014-07-22 08:47:09 -0700 (Tue, 22 Jul 2014) | 11 lines

X86: drop relocations on __eh_frame sections globally.

Without this, we produce non-extern relocations when targeting older OS X
versions that ld64 can't cope with in the particular context of __eh_frame
sections (who'd want generic relocation-processing anyway?).

This means that an updated linker (ld64 from Xcode 3.2.6 or later) may be
needed when targeting such platforms with a modern version of LLVM, but this is
probably the case anyway and a reasonable requirement.

PR20212, rdar://problem/17544795
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@214689 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 04:29:47 +00:00
Bill Wendling
7eef54e612 Merging r213883:
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r213883 | compnerd | 2014-07-24 10:46:36 -0700 (Thu, 24 Jul 2014) | 5 lines

X86: correct library call setup for Windows itanium

This target is identical to the Windows MSVC (and follows Microsoft ABI for C).
Correct the library call setup for this target.  The same set of library calls
are missing on this environment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@214686 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 04:27:37 +00:00
Daniel Sanders
6816d66d99 [mips] Add MipsOptionRecord abstraction and use it to implement .reginfo/.MIPS.options
This abstraction allows us to support the various records that can be placed in
the .MIPS.options section in the future. We currently use it to record register
usage information (the ODK_REGINFO record in our ELF64 spec).

Each .MIPS.options record should subclass MipsOptionRecord and provide an
implementation of EmitMipsOptionRecord.

Patch by Matheus Almeida and Toma Tabacu



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 13:30:55 +00:00
Ulrich Weigand
76fcace66e [MC] Pass MCSymbolData to needsRelocateWithSymbol
As discussed in a previous checking to support the .localentry
directive on PowerPC, we need to inspect the actual target symbol
in needsRelocateWithSymbol to make the appropriate decision based
on that symbol's st_other bits.

Currently, needsRelocateWithSymbol does not get the target symbol.
However, it is directly available to its sole caller.  This patch
therefore simply extends the needsRelocateWithSymbol by a new
parameter "const MCSymbolData &SD", passes in the target symbol,
and updates all derived implementations.

In particular, in the PowerPC implementation, this patch removes
the FIXME added by the previous checkin.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213487 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-20 23:15:06 +00:00
Ulrich Weigand
5ee5fc4c47 [PowerPC] ELFv2 MC support for .localentry directive
A second binutils feature needed to support ELFv2 is the .localentry
directive.  In the ELFv2 ABI, functions may have two entry points:
one for calling the routine locally via "bl", and one for calling the
function via function pointer (either at the source level, or implicitly
via a PLT stub for global calls).  The two entry points share a single
ELF symbol, where the ELF symbol address identifies the global entry
point address, while the local entry point is found by adding a delta
offset to the symbol address.  That offset is encoded into three
platform-specific bits of the ELF symbol st_other field.

The .localentry directive instructs the assembler to set those fields
to encode a particular offset.  This is typically used by a function
prologue sequence like this:

func:
        addis r2, r12, (.TOC.-func)@ha
        addi r2, r2, (.TOC.-func)@l
        .localentry func, .-func

Note that according to the ABI, when calling the global entry point,
r12 must be set to point the global entry point address itself; while
when calling the local entry point, r2 must be set to point to the TOC
base.  The two instructions between the global and local entry point in
the above example translate the first requirement into the second.

This patch implements support in the PowerPC MC streamers to emit the
.localentry directive (both into assembler and ELF object output), as
well as support in the assembler parser to parse that directive.

In addition, there is another change required in MC fixup/relocation
handling to properly deal with relocations targeting function symbols
with two entry points: When the target function is known local, the MC
layer would immediately handle the fixup by inserting the target
address -- this is wrong, since the call may need to go to the local
entry point instead.  The GNU assembler handles this case by *not*
directly resolving fixups targeting functions with two entry points,
but always emits the relocation and relies on the linker to handle
this case correctly.  This patch changes LLVM MC to do the same (this
is done via the processFixupValue routine).

Similarly, there are cases where the assembler would normally emit a
relocation, but "simplify" it to a relocation targeting a *section*
instead of the actual symbol.  For the same reason as above, this
may be wrong when the target symbol has two entry points.  The GNU
assembler again handles this case by not performing this simplification
in that case, but leaving the relocation targeting the full symbol,
which is then resolved by the linker.  This patch changes LLVM MC
to do the same (via the needsRelocateWithSymbol routine).
NOTE: The method used in this patch is overly pessimistic, since the
needsRelocateWithSymbol routine currently does not have access to the
actual target symbol, and thus must always assume that it might have
two entry points.  This will be improved upon by a follow-on patch
that modifies common code to pass the target symbol when calling
needsRelocateWithSymbol.

Reviewed by Hal Finkel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213485 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-20 23:06:03 +00:00
Ulrich Weigand
0d9bcaacd1 [PowerPC] ELFv2 MC support for .abiversion directive
ELFv2 binaries are marked by a bit in the ELF header e_flags field.
A new assembler directive .abiversion can be used to set that flag.
This patch implements support in the PowerPC MC streamers to emit the
.abiversion directive (both into assembler and ELF binary output),
as well as support in the assembler parser to parse the .abiversion
directive.

Reviewed by Hal Finkel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213484 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-20 22:56:57 +00:00
Hal Finkel
d644d17dd4 [PowerPC] 32-bit ELF PIC support
This adds initial support for PPC32 ELF PIC (Position Independent Code; the
-fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
backend.

Patch by Justin Hibbits!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213427 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-18 23:29:49 +00:00
David Peixotto
12f33da20b MC: support different sized constants in constant pools
On AArch64 the pseudo instruction ldr <reg>, =... supports both
32-bit and 64-bit constants. Add support for 64 bit constants for
the pools to support the pseudo instruction fully.

Changes the AArch64 ldr-pseudo tests to use 32-bit registers and
adds tests with 64-bit registers.

Patch by Janne Grunau!

Differential Revision: http://reviews.llvm.org/D4279



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213387 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-18 16:05:14 +00:00
Adam Nemet
6ae2941874 [X86] AVX512: Add disassembler support for compressed displacement
There are two parts here.  First is to modify tablegen to adjust the encoding
type ENCODING_RM with the scaling factor.

The second is to use the new encoding types to compute the correct
displacement in the decoder.

Fixes <rdar://problem/17608489>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213281 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 17:04:56 +00:00
Saleem Abdulrasool
a056166dc2 MC: fix MCAsmInfo usage for windows-itanium
Windows itanium uses the GNUCOFF assmebly format, not ELF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213274 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 16:27:40 +00:00
Daniel Sanders
8f69856b52 [mips] .reginfo is 8 byte aligned on N32.
Differential Revision: http://reviews.llvm.org/D4540


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213246 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 10:10:04 +00:00
Daniel Sanders
3da6527068 [mips] Correct ELF e_flags for the N32 ABI when using a mips-* triple rather than a mips64-* triple
Summary:
Generally speaking, mips-* vs mips64-* should not be used to make decisions
about the content or format of the ELF. This should be based on the ABI
and CPU in use. For example, `mips-linux-gnu-clang -mips64r2 -mabi=64`
should produce an ELF64 as should `mips64-linux-gnu-clang -mabi=64`.
Conversely, `mips64-linux-gnu-clang -mabi=n32` should produce an ELF32 as
should `mips-linux-gnu-clang -mips64r2 -mabi=n32`.

This patch fixes the e_flags but leaves the ELF32 vs ELF64 issue for now
since there is no apparent way to base this decision on the ABI and CPU.

Differential Revision: http://reviews.llvm.org/D4539


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213244 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 10:02:08 +00:00
Daniel Sanders
0a342e9992 [mips] Correct .MIPS.abiflags for -mfpxx on MIPS32r6
Summary:
The cpr1_size field describes the minimum register width to run the program
rather than the size of the registers on the target. MIPS32r6 was acting
as if -mfp64 has been given because it starts off with 64-bit FPU registers.

Differential Revision: http://reviews.llvm.org/D4538


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213243 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 09:57:23 +00:00
Daniel Sanders
4b5e7542df [mips] Fix ELF e_flags related to -mabicalls and -mplt.
Summary:
These options are not implemented yet but we act as if they are always
given.

The integrated assembler is driven by the clang driver so the e_flag test
cases should match the e_flags emitted by GCC+GAS rather than GAS
by itself.

Differential Revision: http://reviews.llvm.org/D4536


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213242 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 09:52:56 +00:00
Tilmann Scheller
2dade438d7 [AArch64] Add negative tests for the SIMD & FP LDP instructions.
LDP is unpredictable if the registers in the pair are identical, these tests check that we don't assemble instructions like that and error out instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213074 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 16:33:24 +00:00
Daniel Sanders
6d6a055c60 [mips] Correct .MIPS.abiflags fp_abi field for -mfpxx and without .module
Summary: Previously all the test cases set it after initialization with '.module fp=xx'.

Differential Revision: http://reviews.llvm.org/D4489


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213071 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 15:31:39 +00:00
Daniel Sanders
52a51e197f Re-commit: [mips] Correct section alignments and EntrySizes for .bss, .text, .data, .reginfo, .MIPS.options, and .MIPS.abiflags
The lld tests will temporarily fail again but Simon Atanasyan will commit a fix for those shortly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212946 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 15:05:51 +00:00
Daniel Sanders
b70b4892a4 Revert: [mips] Correct section alignments and EntrySizes for .bss, .text, .data, .reginfo, .MIPS.options, and .MIPS.abiflags
This commit causes multiple lld tests to fail. Reverting while I investigate the issue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212945 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 14:43:45 +00:00
Daniel Sanders
05aee6b5f4 [mips] Correct section alignments and EntrySizes for .bss, .text, .data, .reginfo, .MIPS.options, and .MIPS.abiflags
Summary:
.bss, .text, and .data are at least 16-byte aligned.
.reginfo is 4-byte aligned and has a 24-byte EntrySize.
.MIPS.abiflags has an 24-byte EntrySize.
.MIPS.options is 8-byte aligned and has 1-byte EntrySize.

Using a 1-byte EntrySize for .MIPS.options seems strange because the
records are neither 1-byte long nor fixed-length but this matches the value
that GAS emits.

Differential Revision: http://reviews.llvm.org/D4487


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212939 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 14:02:14 +00:00
Daniel Sanders
e99ebb9b2f [mips] Correct the AFL_FLAGS1_ODDSPREG flag in .MIPS.abiflags when no '.module oddspreg' is used
Differential Revision: http://reviews.llvm.org/D4486


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212932 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 10:26:15 +00:00
Simon Atanasyan
b2b56ed1a6 [Mips] Support SHT_MIPS_ABIFLAGS section type flag in the llvm-readobj,
obj2yaml and yaml2obj tools.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212908 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-13 15:28:54 +00:00
David Majnemer
f803b3d992 MC: Let non-temporary COFF aliases be in symtab
MC was aping a binutils bug where aliases would default their linkage to
private instead of internal.

I've sent a patch to the binutils maintainers and they've recently
applied it to the GNU assembler sources.

This fixes PR20152.

Differential Revision: http://reviews.llvm.org/D4395

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212899 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-13 04:31:19 +00:00
Arnaud A. de Grandmaison
a9af0558b2 [AArch64] Add logical alias instructions to MC AsmParser
This patch teaches the AsmParser to accept some logical+immediate
instructions and convert them as shown:

  bic  Rd, Rn, #imm  ->  and Rd, Rn, #~imm
  bics Rd, Rn, #imm  ->  ands Rd, Rn, #~imm
  orn  Rd, Rn, #imm  ->  orr Rd, Rn, #~imm
  eon  Rd, Rn, #imm  ->  eor Rd, Rn, #~imm

Those instructions are an alternate syntax available to assembly coders,
and are needed in order to support code already compiling with some other
assemblers. For example, the bic construct is used by the linux kernel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212722 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 15:12:26 +00:00
Daniel Sanders
24a071b8c5 [mips] Add support for -modd-spreg/-mno-odd-spreg
Summary:
When -mno-odd-spreg is in effect, 32-bit floating point values are not
permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit
floating point comparison results from being written to odd registers.

This option has three purposes:
* It allows support for certain MIPS implementations such as loongson-3a that
  do not allow the use of odd registers for single precision arithmetic.
* When using -mfpxx, -mno-odd-spreg is the default and this allows us to
  statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1
  instructions to/from odd registers are guaranteed not to appear for any
  reason. Once this has been established, the user can then re-enable
  -modd-spreg to regain the use of all 32 single-precision registers.
* When using -mfp64 and -mno-odd-spreg together, an O32 extension named
  O32 FP64A is used as the ABI. This is intended to provide almost all
  functionality of an FR=1 processor but can also be executed on a FR=0 core
  with the assistance of a hardware compatibility mode which emulates FR=0
  behaviour on an FR=1 processor.

* Added '.module oddspreg' and '.module nooddspreg' each of which update
  the .MIPS.abiflags section appropriately
* Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller
  doesn't have to remember to do it.
* MipsABIFlags now calculates the flags1 and flags2 member on demand rather
  than trying to maintain them in the same format they will be emitted in.

There is one portion of the -mfp64 and -mno-odd-spreg combination that is not
implemented yet. Moves to/from odd-numbered double-precision registers must not
use mtc1. I will fix this in a follow-up.

Differential Revision: http://reviews.llvm.org/D4383


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 13:38:23 +00:00
Richard Sandiford
9aa8beb9d6 [SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRA
These instructions aren't used for codegen since the original L*DB instructions
are suitable for fround.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212703 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 11:00:55 +00:00
Daniel Sanders
388704618e [mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions
Summary:
It seems we accidentally read the wrong column of the table MIPS64r6 spec
and used the names for c.cond.fmt instead of cmp.cond.fmt.

Differential Revision: http://reviews.llvm.org/D4387


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212607 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-09 10:40:20 +00:00
Ehsan Akhgari
bab04b583c [ms-coff] Add a test for proper handling of full Windows path names in the .drectve section
Summary: This test ensures that we can correctly specify a full Windows path to the clang ASAN runtime libraries.  This is in preparation to fix PR20246.

Reviewers: rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D4427

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212580 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-09 00:40:50 +00:00
Daniel Sanders
fbdb8e1eac [mips] Improve encapsulation of the .MIPS.abiflags implementation and limit scope of related enums
Summary:
Follow on to r212519 to improve the encapsulation and limit the scope of the enums.

Also merged two very similar parser functions, fixed a bug where ASE's
were not being reported, and marked CPR1's as being 128-bit when MSA is
enabled.

Differential Revision: http://reviews.llvm.org/D4384


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-08 10:11:38 +00:00
Arnaud A. de Grandmaison
60d8767211 Truncate the immediate in logical operation to the register width
And continue to produce an error if the 32 most significant bits are not all ones or zeros.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212520 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-08 09:53:04 +00:00
Vladimir Medic
ffbc2a1325 Mips.abiflags is a new implicitly generated section that will be present on all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212519 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-08 08:59:22 +00:00
Adam Nemet
f189d9cdf7 [X86] AVX512: Only allow k1-k7 as predicates to vpcmp*
As destination k0 is allowed but not as predicate/writemask.

I also modified the test to allow checking of error messages by the assembler.
I applied a similar approach to the test ret.s in the same directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212504 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-08 00:22:32 +00:00
Ehsan Akhgari
61b3d72ce4 Revert r212375 because of test failures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212376 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-05 19:46:10 +00:00
Ehsan Akhgari
1ca7c65b4c Add a test case for the tilde operator in Microsoft inline assembly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212375 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-05 19:40:35 +00:00
Daniel Sanders
2093081c8e [mips][mips64r6] Set ELF e_flags for MIPS32r6/MIPS64r6. Also do MIPS-I to MIPS-V
Differential Revision: http://reviews.llvm.org/D4386


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212346 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-04 15:21:53 +00:00
Tim Northover
0f9d1b381e ARM: when falling back to scattered relocs, keep the type.
The linker relies on relocation type info (e.g. is it a branch?) to perform the
correct actions, so we should keep that even when we end up using a scattered
relocation for whatever reason.

rdar://problem/17553104

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212333 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-04 10:58:05 +00:00
Tim Northover
5b003bb869 llvm-readobj: fix MachO relocatoin printing a bit.
There were two issues here:
1. At the very least, scattered relocations cannot use the same code to
   determine the corresponding symbol being referred to. For some reason we
   pretend there is no symbol, even when one actually exists in the symtab, so to
   match this behaviour getRelocationSymbol should simply return symbols_end for
   scattered relocations.
2. Printing "-" when we can't get a symbol (including the scattered case, but
   not exclusively), isn't that helpful. In both cases there *is* interesting
   information in that field, so we should print it. As hex will do.

Small part of rdar://problem/17553104

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212332 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-04 10:57:56 +00:00
Daniel Sanders
a39d3ab819 [mips][mips64r6] Correct the encoding of dmuh, dmuhu, dmul, and dmulu.
We have detected a documentation bug in the encoding tables of the released
MIPS64r6 specification that has resulted in the wrong encodings being used for
these instructions in LLVM. This commit corrects them.



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2014-07-04 10:08:27 +00:00
Alexey Volkov
1bd30dce7b [X86] Limit maximum nop length on Silvermont
Silvermont can only decode one instruction per cycle if the instruction exceeds 8 bytes.
Also in Silvermont instructions with more than 3 prefixes will cause 3 cycle penalty.
Maximum nop length is limited to 7 bytes when used for padding on Silvermont.
For other x86 processors max nop length remains unchanged 15 bytes.

Differential Revision: http://reviews.llvm.org/D4374


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2014-07-04 07:14:56 +00:00
Adam Nemet
df5d431084 [X86] AVX512: Add writemask variants for vperm*2*
This includes assembler and codegen support (see the new tests in
avx512-encodings.s and avx512-shuffle.ll).

<rdar://problem/17492620>

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2014-07-02 21:25:54 +00:00
Saleem Abdulrasool
8f9108459e aarch64: support target-specific .req assembler directive
Based on the support for .req on ARM. The aarch64 variant has to keep track if
the alias register was a vector register (v0-31) or a general purpose or
VFP/Advanced SIMD ([bhsdq]0-31) register.

Patch by Janne Grunau!

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2014-07-02 04:50:23 +00:00
Adam Nemet
1cbd129d6a [X86] AVX512: Allow writemasks with vpcmp
For now I only updated the _alt variants.  The main variants are used by
codegen and that will need a bit more work to trigger.

<rdar://problem/17492620>

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2014-07-01 18:03:45 +00:00
Rafael Espindola
4551671908 Avoid revocations when possible.
This is a small targeted fix for pr20119. The code needs quiet a bit of
refactoring and I added some FIXMEs about it, but I want to get the testcase
passing first.

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2014-07-01 14:34:30 +00:00
Reid Kleckner
cc2a78f941 Fix .seh_stackalloc 0
seh_stackalloc 0 is not representable in Win64 SEH info, so emitting it
is a bug.

Reviewers: rnk

Differential Revision: http://reviews.llvm.org/D4334

Patch by Vadim Chugunov!

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2014-07-01 00:42:47 +00:00
Scott Douglass
a1ff0aed40 ARM: take care not to set the ThumbFunc bit on TLS data symbols
This fixes LNT SingleSource/UnitTests/Threads with -mthumb.

Differential Revision: http://reviews.llvm.org/D4324


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2014-06-30 09:37:24 +00:00
David Majnemer
d7d427732e MC: Fix associative sections on COFF
COFF sections in MC were represented by a tuple of section-name and
COMDAT-name.  This is not sufficient to represent a .text section
associated with another .text section; we need a way to distinguish
between the key section and the one marked associative.

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2014-06-27 17:19:44 +00:00
Adam Nemet
a50d4dd9b0 [X86] AVX512: Add vbroadcasti*
For now I used a separate template for these sub-vector/tuple broadcasts
rather than sharing the mem variants with avx512_int_broadcast_rm.

<rdar://problem/17402869>

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2014-06-27 00:43:38 +00:00
Renato Golin
7eacf4e813 Added parsing co-processor names starting with "cr"
Additional compliant GAS names for coprocessor register name
are enabled for all instruction with parameter MCK_CoprocReg:
LDC,LDC2,STC,STC2,CDP,CDP2,MCR,MCR2,MCRR,MCRR2,MRC,MRC2,MRRC,MRRC2

Patch by Andrey Kuharev.

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2014-06-26 13:10:53 +00:00