Commit Graph

3658 Commits

Author SHA1 Message Date
Matheus Almeida
86992065e6 [mips] Move disassembler test (Mips MSA test_bit) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208586 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:10:00 +00:00
Matheus Almeida
5e3662ae95 [mips] Move disassembler tests (Mips MSA test_2r, test_2rf, test_3r, test_3rf) into
correct folder.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208584 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:03:20 +00:00
Daniel Sanders
e44de6afea Revert: r208582 - [mips][mips64r6] Add sel.s and sel.d
Accidentally committed an unreviewed patch. Reverted it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208583 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 15:43:41 +00:00
Daniel Sanders
87010f33a8 [mips][mips64r6] Add sel.s and sel.d
Summary:
Also use named constants for common opcode fields.

Depends on D3669

Reviewers: jkolek, vmedic, zoran.jovanovic

Differential Revision: http://reviews.llvm.org/D3670

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208582 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 15:39:10 +00:00
Daniel Sanders
b1b144c65a [mips][mips64r6] Add d?div, d?mod, d?divu, d?modu
Summary: Depends on D3668

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3669

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208579 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 15:24:16 +00:00
Daniel Sanders
d76eeb1bce [mips][mips64r6] Added mul/mulu/muh/muhu
Summary: The 'mul' line of the test is temporarily commented out because it currently matches the MIPS32 mul instead of the MIPS32r6 mul. This line will be uncommented when we disable the MIPS32 mul on MIPS32r6.

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3668

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208576 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 15:12:45 +00:00
Daniel Sanders
b6569388b9 [mips] Marked up instructions added in MIPS32 and tested that IAS for -mcpu=mips2 does not accept them
Summary:
To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are explicitly tested.

Depends on D3695

Reviewers: vmedic

Differential Revision: http://reviews.llvm.org/D3696

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208549 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 13:04:32 +00:00
Daniel Sanders
31546cd352 [mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-V that was available in MIPS32R2

Most of these instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now. It happens
because many of the MIPS V instructions have not been implemented.

Depends on D3694

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3695

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208546 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 12:52:44 +00:00
Daniel Sanders
b396af3752 [mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64
Summary:
DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no
effect on the CodeGen tests since expansion of i64 prevented their use
anyway.

The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as
well. This is not a functional change since DCLZ is still prohibited by
being a MIPS64 instruction (MIPS16 is only compatible with MIPS32).

No functional change

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3694

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208544 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 12:41:59 +00:00
Daniel Sanders
d46b2e219d [mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2
Summary:
dsbh and dshd are not available on Mips32r2. No codegen test changes
required since expansion of i64 prevented the use of these instructions
anyway.

Depends on D3690

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3692

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208542 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 12:15:41 +00:00
Bradley Smith
b0b587163d [ARM64] Add proper bounds checking/diagnostics to logical shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208540 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 11:49:16 +00:00
Bradley Smith
0ce7616654 [ARM64] Correct more bounds checks/diagnostics for arithmetic shift operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208528 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 09:41:43 +00:00
Daniel Sanders
7ef85447c9 [mips] Marked up instructions added in MIPS-IV and tested that IAS for -mcpu=mips[123] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-IV that was available in MIPS32

A small number of instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now.

Depends on D3676

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3677

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208414 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 14:06:17 +00:00
Daniel Sanders
70f6f7ee3e [mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-III that was available in MIPS32

A small number of instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now.

There's some obvious InstAlias's that ought to be marked MIPS-III but arent.
This is because they are not currently tested. I intend to catch these with
a final pass through the tablegen records to find tablegen records without
ISA annotations.

Depends on D3674

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208408 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 13:02:27 +00:00
Daniel Sanders
6b68224e9a [mips] Added missing daddu test to the valid instruction tests.
Summary: Depends on D3673

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3674

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208398 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 09:32:01 +00:00
Daniel Sanders
76056a0145 [mips] Added missing dsra -> dsrav and sra -> srav aliases.
Summary: dsll, dsrl, sll, and srl already exist.

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3673

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208397 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 09:24:49 +00:00
Daniel Sanders
4f83e2ca5d [mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS.
Summary:
I've noticed a bug in my test generator script that caused 64-bit objects
to be disassembled as if it were using the O32 ABI, giving the wrong register
names. As a result, it generated assembly files that are rejected by GAS when
assembling for the correct ABI. This was caused by the generator setting the
ELF e_flags incorrectly before disassembling the object.

This patch corrects the invalid tests that have already been committed by
replacing the ABI-dependent register names with numeric registers. In addition
to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed
to produce the invalid-*.s tests which test that instructions defined in later ISA's
are not accepted.

Depends on D3648

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208327 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 15:17:29 +00:00
Daniel Sanders
7bd400ebfd [mips] Implement l[wd]c3, and s[wd]c3.
Summary:
These instructions were added in MIPS-I, and MIPS-II but were removed in
MIPS-III. Interestingly, GAS continues to accept them when assembling for
MIPS-III.

For the moment, these instructions will follow GAS and accept them for
MIPS-III and newer but this will be tightened up when the invalid-*.s
tests are added.

Depends on D3647

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3648

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208311 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 13:02:11 +00:00
Daniel Sanders
13517260e3 [mips] Marked up instructions added in MIPS-II and tested that IAS for -mcpu=mips1 does not accept them
Summary:
A small number of instructions are rejected with the wrong error message.
These have been placed in a separate test for now. There seems to be some
parsing quirk that triggers when these instructions are disabled.

Depends on D3571

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3647

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208305 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 12:40:48 +00:00
Daniel Sanders
dd9080a246 [mips] Implement tlbp, tlbr, tlbwi, and tlbwr
Reviewers: vmedic, dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3571

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208301 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 11:51:18 +00:00
Saleem Abdulrasool
f6efab64b4 test: fix silly typo
Oh silly Darwin and your case insensitive file system.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208274 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 01:41:04 +00:00
Saleem Abdulrasool
dade1d5db5 ARM: support FK_SecRel_2 relocations on WoA
This adds FK_SecRel_2 relocation support to ARM.  This enables the building of
object files for armv7-windows-msvc which enables CodeView line tables for
debugging as opposed to armv7-windows-itanium which currently uses DWARF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208273 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 01:35:57 +00:00
Daniel Sanders
7858e495e9 [mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V
Summary:
These processors will only be available for the integrated assembler at
first (CodeGen will emit a fatal error saying they are not implemented).

The intention is to work through the existing instructions and correctly
annotate the ISA they were added in so that we have a sufficiently good
base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain
instructions and I believe it is best to define ISA's using set-union's
as far as possible rather than using set-subtraction.

Reviewers: vmedic

Subscribers: emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D3569

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208221 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 16:25:22 +00:00
Tim Northover
c6f683627d AArch64/ARM64: disable test directory if ARM64 not present
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208186 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:42:06 +00:00
Tim Northover
3524723195 AArch64/ARM64: implement diagnosis of unpredictable loads & stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208091 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 14:15:14 +00:00
Tim Northover
4d28f030f7 AArch64/ARM64: add two more MC tests to ARM64 set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208085 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 12:50:58 +00:00
Tim Northover
c08733f867 AArch64/ARM64: enable MC-level diagnostic tests for NEON insts.
Obviously we can't expect the two backends to produce identical diagnostics,
since what's possible depends quite a bit on how the .td files are structured.
I think the ARM64 diagnostics are basically of the same quality in all the
changed cases, so I've split the CHECK lines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208084 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 12:50:55 +00:00
Tim Northover
09b3bd8ca3 AArch64/ARM64: make NEON vector list parsing a bit more robust
It doesn't change the results, but it seems silly not to diagnose obvious
problems early on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208083 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 12:50:51 +00:00
Tim Northover
6e64f90dc5 AArch64/ARM64: produce more informative diagnostic assembling some immediates
No tests here, they'll be added when the entire neon-diagnostics.s test from
AArch64 is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208079 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 11:18:53 +00:00
Christian Pirker
80fd09110d ARM: For thumb fixups store halfwords high first and low second
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208076 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 10:05:11 +00:00
Joerg Sonnenberger
b85d6905b5 Fix spelling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207982 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 17:58:46 +00:00
Rafael Espindola
bd7cb3a62d Move test to the ARM64 directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207972 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 16:14:37 +00:00
Rafael Espindola
260b6b05b9 Convert a CodeGen test into a MC test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207971 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 15:34:13 +00:00
Saleem Abdulrasool
a7321a6e53 MC: support FK_SecRel_4 for Windows on ARM
Add handling for FK_SecRel_4 (4-byte section relative relocations).  These are
used by the generation of DWARF debug information (the abbrevations use section
relative relocations).  This will also be used in generation of CodeView line
tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207941 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-04 23:13:15 +00:00
Rafael Espindola
930ca98433 Fix pr19645.
The fix itself is fairly simple: move getAccessVariant to MCValue so that we
replace the old weak expression evaluation with the far more general
EvaluateAsRelocatable.

This then requires that EvaluateAsRelocatable stop when it finds a non
trivial reference kind. And that in turn requires the ELF writer to look
harder for weak references.

Last but not least, this found a case where we were being bug by bug
compatible with gas and accepting an invalid input. I reported pr19647
to track it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207920 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-03 19:57:04 +00:00
Saleem Abdulrasool
735f9edde1 MC: place .file records into the correct section
.file records are supposed to have a section identifier of 65534
(IMAGE_SCN_DEBUG) rather than 0.  This is spelt out clearly within the PE/COFF
specification.  Fix this minor oversight with the implementation for support for
.file records.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207851 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-02 17:45:24 +00:00
Rafael Espindola
dbd5d9d0b8 Don't propagate StorageClass and ComplexType to aliases.
This matches gas' behaviour on COFF.

I think that this yak is now sufficiently shaved for aliases with offset
to work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207786 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 19:02:03 +00:00
Rafael Espindola
23d27597a3 Compute the correct section for zed = foo + 1 in COFF.
This fixes pr19147.

There are a few more related issues to fix, but the testcase in the bug now
passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207763 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 13:37:57 +00:00
Rafael Espindola
1b68a68c04 Don't force symbols to be globals in .thumb_set.
We currently force symbols to be globals in .thumb_set. The intent
seems to be that given

.thumb_set foo, bar

we emit an undefined symbol to bar if it is never defined. The side
effect is that we mark bar as global, even if it is defined, which gas
does not.

Producing an undefined reference to bar is a general difference from MC and gas.
For example, given

a = b

gas will produce an undefined reference to b, MC will not. I would be surprised
if any code depends on this, but it it does, we should fix the general
difference, not special case .thumb_set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207757 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 12:45:43 +00:00
Tim Northover
3c5651a003 AArch64/ARM64: rewrite test to use FileCheck & add ARM64 lines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207754 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 12:30:01 +00:00
Tim Northover
fadbf53e7e AArch64/ARM64: port basic disassembly tests to ARM64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207753 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 12:29:56 +00:00
Tim Northover
f2f35a9ca3 AArch64/ARM64: print BFM instructions as BFI or BFXIL
The canonical form of the BFM instruction is always one of the more explicit
extract or insert operations, which makes reading output much easier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207752 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 12:29:38 +00:00
Richard Barton
8b88679164 Correction to assert statemtent to allow 32-bit unsigned numbers with the top bit set.
This fixes an ARM assembler crash - regression test added.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207747 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 11:37:44 +00:00
Bradley Smith
e29cd17aeb [ARM64] Conditionalize CPU specific system registers on subtarget features
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207742 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 10:25:36 +00:00
Matheus Almeida
4c715625d9 [mips] Move expansion of .cpsetup to target streamer.
Summary:
There are two functional changes:
1) The directive is not expanded for the ASM->ASM code path.
2) If PIC is not set, there's no expansion for the ASM->OBJ code path (same behaviour as GAS).

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3482

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207741 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 10:24:46 +00:00
Daniel Sanders
873f87c2de [mips] Removed two-operand alias for sllv, sr[al]v, rotrv, dsllv, dsr[al]v, and drotrv
GAS doesn't actually accept these particular cases.

The mnemonic without the trailing 'v' still supports two-operand aliases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207740 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 10:08:36 +00:00
Oliver Stannard
5604ab9da4 Record the DWARF version in MCContext
Record the DWARF version in MCContext, and use it when
emitting the dwarf version into the debug info.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207739 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 08:46:02 +00:00
Rafael Espindola
b77f8919bc Start fixing pr19147.
This makes the coff writer compute the correct symbol value for the test in
pr19147. The section is still incorrect, that will be fixed in a followup patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207728 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 00:10:17 +00:00
James Molloy
d96bbedc6a Move a testcase from ELF to ARM64, incorrectly placed in r207627.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207706 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 21:31:11 +00:00
James Molloy
6f327421c5 Add a testcase for r207627.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 20:06:26 +00:00
Matheus Almeida
1afb0ccb40 [mips] Add instruction alias (negu).
Summary: negu $reg is equivalent to negu $reg, $reg.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3510

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207673 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:53:49 +00:00
Matheus Almeida
3fa0a85ce8 [mips] Add instruction alias (sltu).
Summary:
The pattern sltu $r1, $r2, $imm is found in handwritten assembly which
is just a shorthand version of sltui $r1, $r2, $imm.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3508

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207671 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:29:56 +00:00
Hans Wennborg
a8febf2283 ELFObjectWriter: deduplicate suffices in strtab
We already do this for shstrtab, so might as well do it for strtab. This
extracts the string table building code into a separate class. The idea
is to use it for other object formats too.

I mostly wanted to do this for the general principle, but it does save a
little bit on object file size. I tried this on a clang bootstrap and
saved 0.54% on the sum of object file sizes (1.14 MB out of 212 MB for
a release build).

Differential Revision: http://reviews.llvm.org/D3533

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207670 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:25:02 +00:00
Tim Northover
b1c1b8a78d ARM64: print fp immediates without using scientific notation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207669 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:13:34 +00:00
Tim Northover
83286f081d AArch64/ARM64: implement remaining TLS relocations (purely MC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207668 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:13:26 +00:00
Tim Northover
50de5e4f57 AArch64/ARM64: add specific diagnostic for MRS/MSR and enable tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207667 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:13:20 +00:00
Tim Northover
52f60f81d9 AArch64/ARM64: accept and print floating-point immediate 0 as "#0.0"
It's been decided that in the future, the floating-point immediate in
instructions like "fcmeq v0.2s, v1.2s, #0.0" will be canonically "0.0", which
has been implemented on AArch64 already but not ARM64.

This fixes that issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207666 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:13:07 +00:00
Matheus Almeida
c3a5ef59e4 [mips] Add instruction alias (dsll and dsrl).
Summary:
The pattern dsll/dsrl $rd, $rt, $rs is found in handwritten assembly which
is just a shorthand version of dsllv/dsrlv $rd, $rt, $rs.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3486

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207664 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:00:49 +00:00
Rafael Espindola
41fb117905 Relax the test a bit.
It is not relevant where the symbol and section names are stored, just their
values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207662 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:32:21 +00:00
Rafael Espindola
3dbcd2e69e Rename the test, it is testing the symver directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207658 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:27:44 +00:00
Matheus Almeida
6c71a5f6e4 [mips] Add instruction alias (sll and srl).
Summary:
The pattern sll/srl $rd, $rt, $rs is found in handwritten assembly which
is just a shorthand version of sllv/srlv $rd, $rt, $rs.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3483

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207657 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:23:04 +00:00
Matheus Almeida
99b44bacab [mips] Update tests with encoding information for slt, slti, sltiu and sltu.
Summary:
Also renamed non-portable register names (e.g. $t2) so that we don't end up
with a different encoding for what appears to be an equivalent instruction.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3505

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207655 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 14:52:57 +00:00
Tim Northover
ee053f4f51 ARM64: enable AArch64's basic-a64-instructions test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207650 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:37:10 +00:00
Tim Northover
44a2f5610d ARM64: print lsr instead of lsrv for variable shifts (etc)
The canonical syntax for shifts by a variable amount does not end with 'v', but
that syntax should be supported as an alias (presumably for legacy reasons).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207649 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:37:07 +00:00
Tim Northover
7870967ba1 ARM64: use 32-bit operations for uxtb & uxth
Testing will be enabled shortly with basic-a64-instructions.s

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207648 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:37:02 +00:00
Tim Northover
bfb7bc89df AArch64/ARM64: copy support for bCC instead of b.CC across.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207646 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:36:56 +00:00
Tim Northover
d805bf8d61 AArch64/ARM64: use HS instead of CS & LO instead of CC.
On instructions using the NZCV register, a couple of conditions have dual
representations: HS/CS and LO/CC (meaning unsigned-higher-or-same/carry-set and
unsigned-lower/carry-clear). The first of these is more descriptive in most
circumstances, so we should print it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207644 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:14:03 +00:00
Tim Northover
4e29e3a10a ARM64: accept ELF-relocated load/store insts without a #.
E.g. we print "ldr x0, [x0, :lo12:symbol]" so we need to accept that syntax
too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207639 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 12:00:20 +00:00
Matheus Almeida
00bdeb4c54 [mips] Add support for .cpload.
Summary:
This directive is used for setting up $gp in the beginning of a function.
It expands to three instructions if PIC is enabled:
lui   $gp, %hi(_gp_disp)
addui $gp, $gp, %lo(_gp_disp)
addu  $gp, $gp, $reg

_gp_disp is a special symbol that the linker sets to the distance between
the lui instruction and the context pointer (_gp).

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3480

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207637 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:28:42 +00:00
Matheus Almeida
737de9db8e [mips] Emit all three relocation operations for each relocation entry on Mips64 big-endian systems.
Summary:
The N64 ABI allows up to three operations to be specified per relocation record
independently of the endianness.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3529

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207636 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:21:10 +00:00
Tim Northover
ebde5a5e49 ARM64: use hex immediates for movz/movk instructions
Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to
piece together an immediate in 16-bit chunks, hex is probably the most
appropriate format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207635 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:40 +00:00
Tim Northover
87476b607c ARM64: hexify printing various immediate operands
This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they
accept weird shifts which are more naturally understandable in hex notation).

Also changes BRK/HINT etc, which is probably a neutral change, but easier than
the alternative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
Tim Northover
2a2cce79be ARM64: print canonical syntax for add/sub (imm) instructions.
Since these instructions only accept a 12-bit immediate, possibly shifted left
by 12, the canonical syntax used by the architecture reference manual is "#N {,
lsl #12 }". We should accept an immediate that has already been shifted, (e.g.

Also, print a comment giving the full addend since it can be helpful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207633 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:15 +00:00
Saleem Abdulrasool
f3ce0c061e ARM: print COFF function header for Windows on ARM
Emit the COFF header when printing out the function.  This is important as the
header contains two important pieces of information: the storage class for the
symbol and the symbol type information.  This bit of information is required for
the linker to correctly identify the type of symbol that it is dealing with.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207613 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 06:14:25 +00:00
Joerg Sonnenberger
edc4595472 Parse and create GOT_PREL relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207526 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 13:42:02 +00:00
Rafael Espindola
1c5f439f41 Centralize the handling of the thumb bit.
This patch centralizes the handling of the thumb bit around
MCStreamer::isThumbFunc and makes isThumbFunc handle aliases.

This fixes a corner case, but the main advantage is having just one
way to check if a MCSymbol is thumb or not. This should still be
refactored to be ARM only, but at least now it is just one predicate
that has to be refactored instead of 3 (isThumbFunc,
ELF_Other_ThumbFunc, and SF_ThumbFunc).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 12:46:50 +00:00
Rafael Espindola
1c509556ee Add an option for evaluating past symbols.
When evaluating an assembly expression for a relocation, we want to
stop at MCSymbols that are in the symbol table, even if they are variables.
This is needed since the semantics may require that the relocation use them.

That is not the case when computing the value of a symbol in the symbol table.
There are no relocations in this case and we have to keep going until we hit
a section or find out that the expression doesn't have an assembly time
value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207445 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-28 20:53:11 +00:00
Rafael Espindola
0af058ff9c Don't include an invalid symbol in the symbol table.
The symbol table itself has no relocations, so it is not possible to represent
things like

a = undefined + 1

With the patch we just omit these variables. That matches the behaviour of the
gnu assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207419 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-28 13:39:57 +00:00
Rafael Espindola
086e9aaa55 List the entire symbol table in this test.
This will allow us to extend this test to show that other symbols don't
show up in the symbol table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207418 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-28 13:26:35 +00:00
Rafael Espindola
c074b096d5 Produce an error instead of a crash in an expr we cannot represent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207414 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-28 12:40:50 +00:00
Tim Northover
16aac4387f ARM64: diagnose use of v16-v31 in certain indexed NEON instructions.
Someone couldn't bear to have a completely orthogonal set of floating-point
registers, so we've got some instructions that only accept v0-v15 (coming in
ARMv9, V128_prime: you're allowed v2, v3, v5, v7, ...).

Anyway, we were permitting even the out of range registers during assembly
(CodeGen handled it correctly). This adds a diagnostic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207412 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-28 11:27:43 +00:00
Rafael Espindola
2dc04b4604 Add emitThumbSet to the arm target streamer.
This fixes the asm printer implementation and lets the parser be unaware of
what .thumb_set is.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207381 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-27 20:23:58 +00:00
Saleem Abdulrasool
189a2a91c7 MC: duplicate .file test for WoA (SVN r207341)
Since the COFF tests are dependent on X86, duplicate the test for ARM.  Use the
default check prefix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207365 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-27 16:10:57 +00:00
Saleem Abdulrasool
86e4b7dadb COFF: move ARM COFF test to ARM directory
The COFF tests all assume X86.  Just move the new COFF tests under ARM to
appease the build bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207346 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-27 04:29:32 +00:00
Saleem Abdulrasool
2d0d7fd085 Add WoA object file emission support
Introduce support for WoA PE/COFF object file emission from LLVM.  Add the new
target specific PE/COFF Streamer (ARMWinCOFFStreamer) that handles the ARM
specific behaviour of PE/COFF object emission.  ARM exception information is not
yet emitted and is a TODO item.

The ARM specific object writer (ARMWinCOFFObjectWriter) handles the ARM specific
relocation handling in conjunction with the WinCOFFObjectWriter in the MC layer.
The MC layer needs to be updated to deal with the relocation adjustments.
Branch relocations are adjusted by 4 bytes (unlikely their ELF counterparts).

Minor tweaks to switch multiple conditional checks into equivalent switch
statements.  The ObjectFileInfo is updated to relax the object file setup for
Windows COFF.  Move the architecture checks into an assertion.  Windows COFF is
currently only supported on x86, x86_64, and ARM (thumb).  Rather than
defaulting to ELF, we will refuse to generate an object file.  This is better
though as you do not get an (arbitrary) object file which is different from the
request.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207345 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-27 03:48:22 +00:00
Bradley Smith
8aa927abb5 [ARM64] Print preferred aliases for SFBM/UBFM in InstPrinter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207219 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-25 10:25:29 +00:00
Kevin Qin
78eedb15c9 [ARM64] Support crc predicate on ARM64.
According to the specification, CRC is an optional extension of the
architecture.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207214 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-25 09:25:42 +00:00
Tim Northover
d8b6fe2c41 AArch64/ARM64: add ARM64 runs to more MC tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207120 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 15:04:26 +00:00
Tim Northover
7b59710b6f AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too.
This skips a couple of compare ones due to the different syntaxt for
floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle
ARM64 to make it work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207119 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 15:04:20 +00:00
Tim Northover
a05d37e1f4 AArch64: print NEON lists with a space.
This matches ARM64 behaviour, which I think is clearer. It also puts all the
churn from that difference into one easily ignored commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207116 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 14:06:20 +00:00
Tim Northover
c80e56729b AArch64/ARM64: enable remaining MC elf tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207112 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:56:41 +00:00
Tim Northover
d4daf1762d AArch64/ARM64: allow negative addends, at least on ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207111 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:56:38 +00:00
Tim Northover
421c65b9b4 ARM64: support relocated "TBZ/TBNZ" instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207110 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:56:34 +00:00
Tim Northover
332497fc56 AArch64/ARM64: support relocated ADR instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207109 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:56:30 +00:00
Tim Northover
4fec4077fc AArch64/ARM64: add support for :abs_gN_s: MOVZ modifiers
We only need assembly support, so it's fairly easy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207108 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:56:27 +00:00
Tim Northover
d4b4f400e8 AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operands
These can have different relocations in ELF. In particular both:

    b.eq global
    ldr x0, global

are valid, giving different relocations. The only possible way to distinguish
them is via a different fixup, so the operands had to be separated throughout
the backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207105 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:12:10 +00:00
Tim Northover
92f4b34653 AArch64/ARM64: enable some MC tests on ARM64
This will also (as with CodeGen) disable testing when the ARM64 backend is not
present.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207104 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:12:01 +00:00
Stepan Dyatkovskiy
5c025f2f6e Fix for PR18921, "vmov" part.
Added support for bytes replication feature, so it could be GAS compatible.

E.g. instructions below:
"vmov.i32 d0, 0xffffffff"
"vmvn.i32 d0, 0xabababab"
"vmov.i32 d0, 0xabababab"
"vmov.i16 d0, 0xabab"
are incorrect, but we could deal with such cases.

For first one we should emit:
"vmov.i8 d0, 0xff"
For second one ("vmvn"):
"vmov.i8 d0, 0x54"
For last two instructions it should emit:
"vmov.i8 d0, 0xab"

P.S.: In ARMAsmParser.cpp I have also fixed few nearby style issues in old code.
Just for keeping method bodies in harmony with themselves.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207080 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 06:03:01 +00:00
Saleem Abdulrasool
646d516502 MC: disable test on thumbv7-windows
This is dependent on changes that are not fully ready to be merged yet (WoA
object file emission).  The test can be re-enabled for that target later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207038 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 21:55:18 +00:00
Saleem Abdulrasool
ac30dfdaa3 MC: move test from Generic to COFF
This is a COFF specific test, move it to COFF to fix the Hexagon buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207030 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 21:41:07 +00:00
Saleem Abdulrasool
dc71f098bc MC: move ARM64 test from AArch64 directory
The test was changed from aarch64 to arm64 but not moved.  The test would fail
if the backend was not built.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207029 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 21:29:40 +00:00
Saleem Abdulrasool
49babc916a MC: honour IMAGE_SCN_CNT_INITIALIZED_DATA
Emit the flag to indicate to the assembler that a section contains data if there
is pre-populated data present.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207028 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 21:29:34 +00:00
Elena Demikhovsky
3890a42255 X86Disassembler - fixed a bug in immediate print
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206953 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 07:21:04 +00:00
Stepan Dyatkovskiy
8c5b3146ed Integrated assbemler, macros: added 'vararg' argument qualifier support.
Note, currently we have no 'vararg' support for darwin macros.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206951 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 06:56:28 +00:00
Kevin Qin
81ea345894 [ARM64] Enable feature predicates for NEON / FP / CRYPTO.
AArch64 has feature predicates for NEON, FP and CRYPTO instructions.
This allows the compiler to generate code without using FP, NEON
or CRYPTO instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206949 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 06:22:48 +00:00
Rafael Espindola
8c8fae7268 Follow aliases when determining if a symbol is thumb.
This fixes pr19484.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206917 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 19:11:07 +00:00
Kevin Enderby
29c96f133e Fix the assembler to print a better relocatable expression error
diagnostic that includes location information.

Currently if one has this assembly:

	.quad (0x1234 + (4 * SOME_VALUE))

where SOME_VALUE is undefined ones gets the less than
useful error message with no location information:

% clang -c x.s
clang -cc1as: fatal error: error in backend: expected relocatable expression

With this fix one now gets a more useful error message
with location information:

% clang -c x.s 
x.s:5:8: error: expected relocatable expression
 .quad (0x1234 + (4 * SOME_VALUE))
       ^

To do this I plumbed the SMLoc through the MCObjectStreamer
EmitValue() and EmitValueImpl() interfaces so it could be used
when creating the MCFixup.

rdar://12391022


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206906 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 17:27:29 +00:00
Robert Khasanov
c13297fa76 [AVX512] Implemented integer conversions up/down with masking.
Added encoding tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206884 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 11:36:19 +00:00
Jim Grosbach
91c655736e ARM64: Improve diagnostics for malformed reg+reg addressing mode.
Make sure only general purpose registers are valid for offset regs and
that 32-bit regs are only valid for sxtw and uxtw extends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206799 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 21:45:57 +00:00
Rafael Espindola
bc26ff9180 Handle _GLOBAL_OFFSET_TABLE_ in 64 bit mode.
With this MC is able to handle _GLOBAL_OFFSET_TABLE_ in 64 bit mode, which is
needed for medium and large code models.

This fixes pr19470.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206793 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 21:15:45 +00:00
Yaron Keren
2fa9e6ca34 Patch by Ray Donnelly to print register names instead of numbers.
http://reviews.llvm.org/D3422



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206683 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-19 05:40:09 +00:00
Kevin Enderby
1a47d66496 Change the ARM assembler to require a :lower16: or :upper16 on non-constant
expressions for mov instructions instead of silently truncating by default.

For the ARM assembler, we want to avoid misleadingly allowing something
like "mov r0, <symbol>" especially when we turn it into a movw and the
expression <symbol> does not have a :lower16: or :upper16" as part of the
expression.  We don't want the behavior of silently truncating, which can be
unexpected and lead to bugs that are difficult to find since this is an easy
mistake to make.

This does change the previous behavior of llvm but actually matches an
older gnu assembler that would not allow this but print less useful errors
of like “invalid constant (0x927c0) after fixup” and “unsupported relocation on
symbol foo”.  The error for llvm is "immediate expression for mov requires
:lower16: or :upper16" with correct location information on the operand
as shown in the added test cases.

rdar://12342160


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206669 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 23:06:39 +00:00
David Blaikie
2e3463ec43 Compress debug sections only when beneficial.
Both ZLIB and the debug info compressed section header ("ZLIB" + the
size of the uncompressed data) take some constant overhead so in some
cases the compressed data is actually larger than the uncompressed data.
In these cases, just don't compress or rename the section at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206659 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 21:52:26 +00:00
David Blaikie
037da24c10 Update the fragments of symbols in compressed sections.
While unnamed relocations are already cached in side tables in
ELFObjectWriter::RecordRelocation, symbols still need their fragments
updated to refer to the newly compressed fragment (even if that fragment
isn't big enough to fit the offset). Even though we only create
temporary symbols in debug info sections this comes up in 32 bit builds
where even temporary symbols in mergeable sections (such as debug_str)
have to be emitted as named symbols.

I tried a few other ways to do this but they all didn't work for various
reasons:

1) Canonicalize the MCSymbolData in RecordRelocation, nulling out the
Fragment (so it didn't have to be updated by CompressDebugSection). This
doesn't work because some code relies on symbols having fragments to
indicate that they're defined, I think.

2) Canonicalize the MCSymbolData in RecordRelocation to be "first
fragment + absolute offset" so it would be cheaper to just test and
update the fragment in CompressDebugSections. This doesn't work because
the offset computed in RecordRelocation isn't that of the symbol's
fragment, it's the passed in fragment (I haven't figured out what that
fragment is - perhaps it's the location where the relocation is to be
written). And if the fragment offset has to be computed only for this
use we might as well just do it when we need to, in
CompressDebugSection.

I also added an assert to help catch this a bit more clearly, even
though it is UB. The test case improvements would either assert fail
and/or valgrind vail without the fix, even if they wouldn't necessarily
fail the FileCheck output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206653 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 21:24:12 +00:00
Chandler Carruth
64eed05a3a Revert r206565 (and r206566 which updated tests).
This commit was attributed to a different person from the person who
posted the patch to the list, and the person who posted it the list
claimed when they did that they were not the author, but that the author
was yet a third person. I don't know what is going on here, but
reverting until the attribution is clear and the author has explicitly
contributed the patch.

Also, the review hasn't really involved any of the MC maintainers and
that seems questionable too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206576 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 09:35:51 +00:00
Yaron Keren
188195c3f9 Updated test with register names following r206565.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206566 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 08:50:09 +00:00
Jim Grosbach
4af58f145d ARM64: [su]xtw use W regs as inputs, not X regs.
Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing
mode handling.

PR19455 and rdar://16650642

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206495 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-17 20:47:31 +00:00
Craig Topper
61070beae0 [X86] Add disassembler support for the 0x0f 0x7f form of movq %mm, %mm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206447 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-17 06:33:45 +00:00
Konrad Anheim
685d699870 Test commit - Added a new line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206399 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 16:45:18 +00:00
Matheus Almeida
e4439438f6 [mips] Use TwoOperandAliasConstraint for shift instructions.
This enables TableGen to generate an additional two operand
matcher for our shift_rotate_imm and shift_rotate_reg class of instructions.

The tests were also updated so that they include now encoding information
for all affected instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206398 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 16:28:59 +00:00
Matheus Almeida
c308f165a0 [mips] Add initial support for NaN2008 in the back-end.
This is so that EF_MIPS_NAN2008 is set if we are using IEEE 754-2008
NaN encoding (-mnan=2008). This patch also adds support for parsing
'.nan legacy' and '.nan 2008' assembly directives. The handling of
these directives should match GAS' behaviour i.e., the last directive
in use sets the ELF header bit (EF_MIPS_NAN2008).

Differential Revision: http://reviews.llvm.org/D3346


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206396 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 15:48:55 +00:00
Tim Northover
9a8aff0062 AArch64/ARM64: produce correct relocation for conditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 15:27:52 +00:00
Saleem Abdulrasool
c09746dc9c COFF: fix an off by one error
Adjust the tests to validate the number of auxiliary entries used to store the
filename.

Thanks to majnemer's sharp eye for catching the missing - 1 in the round up
calculation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206359 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 06:22:53 +00:00
Saleem Abdulrasool
73a7844c65 COFF: add support for .file symbols
Add support for emitting .file records.  This is mostly a quality of
implementation change (more complete support for COFF file emission) that was
noticed while working on COFF file emission for Windows on ARM.

A .file record is emitted as a symbol with storage class FILE (103) and the name
".file".  A series of auxiliary format 4 records follow which contain the file
name.  The filename is stored as an ANSI string and is padded with NULL if the
length is not a multiple of COFF::SymbolSize (18).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206355 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 04:15:32 +00:00
Tim Northover
2a83cb71ad AArch64/ARM64: only mangle MOVZ/MOVN during encoding when needed
Sometimes we need emit the bits that would actually be a MOVN when producing a
relocated MOVZ instruction (don't ask). But not always, a check which ARM64 got
wrong until now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206289 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 14:00:15 +00:00
Stepan Dyatkovskiy
5fba9d3b5e Optional hash symbol feature support for ARM64
http://reviews.llvm.org/D3328



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206276 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 11:43:09 +00:00
Quentin Colombet
67ed710684 [MC] Emit an error if cfi_startproc is used before a symbol is defined.
Currently, we bind those directives with the last symbol, so if none
has been defined, this would lead to a crash of the compiler.

<rdar://problem/15939159>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206236 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 01:17:45 +00:00
Kaelyn Takata
de2b2a32f4 Fix up MCFixup::getAccessVariant to handle unary expressions.
This allows correct relocations to be generated for a symbolic
address that is being adjusted by a negative constant. Since r204294,
such expressions have triggered undefined behavior when LLVM was built
without assertions.

Credit goes to Rafael for this patch; I'm submitting it on his behalf
as he is on vacation this week.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206192 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-14 16:50:22 +00:00
Rafael Espindola
0a3dcf2c51 Don't lose the thumb bit by using relocations with sections.
This fixes a regression from r205076.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206047 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-11 19:18:01 +00:00
Daniel Sanders
ae6f7070ba Revert: r205182 - llvm/test/MC/Mips/mips64r2/valid-xfail.s: This REQUIRES asserts. Seems it doesn't fail with -Asserts.
This was most likely caused by an uninitialized value and the relevant code was re-written in r205292. Reverting to see if it still fails on any of the buildbots.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206033 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-11 15:33:36 +00:00
Kaelyn Takata
c39b659b89 Remove the use of "%e" as it is not a valid expansion like "%t".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205991 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-10 21:55:58 +00:00
David Blaikie
fe25521451 Reimplement debug info compression by compressing the whole section, rather than a fragment.
To support compressing the debug_line section that contains multiple
fragments (due, I believe, to variation in choices of line table
encoding depending on the size of instruction ranges in the actual
program code) we needed to support compressing multiple MCFragments in a
single pass.

This patch implements that behavior by mutating the post-relaxed and
relocated section to be the compressed form of its former self,
including renaming the section.

This is a more flexible (and less invasive, to a degree) implementation
that will allow for other features such as "use compression only if it's
smaller than the uncompressed data".

Compressing debug_frame would be a possible further extension to this
work, but I've left it for now. The hurdle there is alignment sections -
which might require going as far as to refactor
MCAssembler.cpp:writeFragment to handle writing to a byte buffer or an
MCObjectWriter (there's already a virtual call there, so it shouldn't
add substantial compile-time cost) which could in turn involve
refactoring MCAsmBackend::writeNopData to use that same abstraction...
which involves touching all the backends. This would remove the limited
handling of fragment writing seen in
ELFObjectWriter.cpp:getUncompressedData which would be nice - but it's
more invasive.

I did discover that I (perhaps obviously) don't need to handle
relocations when I rewrite the fragments - since the relocations have
already been applied and computed (and stored into
ELFObjectWriter::Relocations) by this stage (necessarily, because we
need to have written any immediate values or assembly-time relocations
into the data already before we compress it, which we have). The test
case doesn't necessarily cover that in detail - I can add more test
coverage if that's preferred.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205990 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-10 21:53:53 +00:00
David Blaikie
22f3236dd6 Revert debug info compression support.
To support compression for debug_line and debug_frame a different
approach is required. To simplify review, revert the old implementation
and XFAIL the test case. New implementation to follow shortly.

Reverts r205059 and r204958.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205989 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-10 21:53:47 +00:00
Kevin Enderby
e7ef041ba4 For the ARM integrated assembler add checking of the
alignments on vld/vst instructions.  And report errors for
alignments that are not supported.

While this is a large diff and an big test case, the changes
are very straight forward.  But pretty much had to touch
all vld/vst instructions changing the addrmode to one of the
new ones that where added will do the proper checking for
the specific instruction.

FYI, re-committing this with a tweak so MemoryOp's default
constructor is trivial and will work with MSVC 2012. Thanks
to Reid Kleckner and Jim Grosbach for help with the tweak.

rdar://11312406


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205986 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-10 20:18:58 +00:00
Daniel Sanders
feb96be96e [mips] Switch the MIPS-III and MIPS-IV assembler tests to use -mcpu=mips4.
Summary:
It is now the smallest superset for these ISA's.

FeatureMips4 now contains FeatureFPIdx since [ls][dw]xc1 were added in MIPS-IV.
Made the FPIdx feature bit lowercase so that it can be used in the -mattr option.

Depends on D3274

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3275

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205964 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-10 13:16:49 +00:00
Reid Kleckner
6a6b4d5dfa Revert "For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported."
It doesn't build with MSVC 2012, because MSVC doesn't allow union
members that have non-trivial default constructors.  This change added
'SMLoc AlignmentLoc' to MemoryOp, which made MemoryOp's default ctor
non-trivial.

This reverts commit r205930.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205944 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-10 00:52:14 +00:00
Kevin Enderby
34d14bb534 For the ARM integrated assembler add checking of the
alignments on vld/vst instructions.  And report errors for
alignments that are not supported.

While this is a large diff and an big test case, the changes
are very straight forward.  But pretty much had to touch
all vld/vst instructions changing the addrmode to one of the
new ones that where added will do the proper checking for
the specific instruction.

rdar://11312406


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205930 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 21:32:59 +00:00
Alp Toker
46d36be2eb Fix some doc and comment typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205899 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:47:27 +00:00
Bradley Smith
35fb92dadd [ARM64] Change SYS without a register to an alias to make disassembling more consistant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205898 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:58 +00:00
Bradley Smith
62293d1147 [ARM64] Correctly disassemble ISB operand as ISB not DBarrier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205897 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:54 +00:00
Bradley Smith
c669ad900d [ARM64] Properly support both apple and standard syntax for FMOV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205896 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:49 +00:00
Bradley Smith
cb9ca905e3 [ARM64] Flag setting logical/add/sub immediate instructions don't use SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205895 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:44 +00:00
Bradley Smith
19b573d9c9 [ARM64] Conditional branches must always print their condition code, even AL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205894 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:39 +00:00
Bradley Smith
42c672649c [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205893 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:36 +00:00
Bradley Smith
ae30bea9d7 [ARM64] Add missing shifted register MVN alias to ORN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205891 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:26 +00:00
Bradley Smith
7face75878 [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205890 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:22 +00:00
Bradley Smith
7b5940c0c0 [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a dumb alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205889 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:18 +00:00
Bradley Smith
250f973d7f [ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205888 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:12 +00:00
Bradley Smith
9a9fa81c1a [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:07 +00:00
Bradley Smith
86c067813c [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205886 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:03 +00:00
Bradley Smith
5a09ce9ad1 [ARM64] Rename LR to the UAL-compliant 'X30'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205885 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:43:59 +00:00
Bradley Smith
37fe6627f6 [ARM64] Rename FP to the UAL-compliant 'X29'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205884 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:43:50 +00:00
Bradley Smith
6af2db2222 [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205883 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:43:40 +00:00
Bradley Smith
f797751ca0 [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205882 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:43:35 +00:00
Bradley Smith
5c73bde178 [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205881 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:43:31 +00:00
Bradley Smith
98422af96f [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205879 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:43:24 +00:00
Bradley Smith
47c311bafe [ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205878 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:43:20 +00:00
Bradley Smith
8acef8d96d [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205877 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:43:15 +00:00
Bradley Smith
a8f8d292ca [ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205876 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:43:11 +00:00
Bradley Smith
3d41487f0e [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205875 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:43:06 +00:00
Bradley Smith
436fe613fc [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205874 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:43:01 +00:00
Bradley Smith
4be472c874 [ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205871 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:49 +00:00
Bradley Smith
96e05ca4bf [ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205869 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:42 +00:00
Bradley Smith
fb7edfa9a5 [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205868 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:36 +00:00
Bradley Smith
a493b7786a [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205865 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:11 +00:00
Bradley Smith
a5b549e03c [ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205864 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:07 +00:00
Bradley Smith
4580af747e [ARM64] Add missing 1Q -> 1q vector kind alias
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205863 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:01 +00:00
Bradley Smith
1ff9280e05 [ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205862 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:41:58 +00:00
Bradley Smith
f5234a2c6c [ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205861 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:41:53 +00:00
Bradley Smith
35b8c724c7 [ARM64] STRHro and STRBro were not being decoded at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205860 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:41:49 +00:00
Bradley Smith
6307036c7c [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205859 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:41:45 +00:00
Bradley Smith
7ac29214ce [ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205858 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:41:38 +00:00
David Majnemer
e4d89ec8de WinCOFF: Emit common symbols as specified in the COFF spec
Summary:
Local common symbols were properly inserted into the .bss section.
However, putting external common symbols in the .bss section would give
them a strong definition.

Instead, encode them as undefined, external symbols who's symbol value
is equivalent to their size.

Reviewers: Bigcheese, rafael, rnk

CC: llvm-commits

Differential Revision: http://reviews.llvm.org/D3324

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205811 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 22:33:40 +00:00
Kevin Enderby
9143956488 Fix the ARM VLD3 (single 3-element structure to all lanes)
size 16 double-spaced registers instruction printing.

This:
	vld3.16 {d0[], d2[], d4[]}, [r4]!

was being printed as:

	vld3.16	{d0[], d1[], d2[]}, [r4]!

rdar://16531387


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205779 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 18:00:52 +00:00
NAKAMURA Takumi
60db02b6fe X86MCAsmInfoGNUCOFF: Set PointerSize as 8 for targeting x64. It caused DW_LNE_set_address was misemitted on x64.
FIXME: I haven't investigate whether CalleeSaveStackSlotSize should be 8.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205772 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 15:28:50 +00:00
Saleem Abdulrasool
2a65dd3101 ARM: consolidate MachO checks for ARM asm parser
This consolidates the duplicated MachO checks in the directive parsing for
various directives that are unsupported for Mach-O.  The error message change is
unimportant as this restores the behaviour to that prior to the addition of the
new directive handling.  Furthermore, use a more direct check for MachO
targeting rather than an indirect feature check of the assembler.

Also simplify the test execution command to avoid temporary files.  Further more,
perform the check in both object and assembly emission.

Whether all non-applicable directives are handled is another question.  .fnstart
is marked as being unsupported, however, the complementary .fnend is not.  The
additional unwinding directives are also still honoured.  This change does not
change that, though, it would be good to validate and mark them as being
unsupported if they are unsupported for the MachO emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205678 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-05 22:09:51 +00:00
Kai Nacke
a1329ecb8e [mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.
This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.
It is only for the assembler. Test case is included.

Reviewed by: Daniel.Sanders@imgtec.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205631 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 16:21:59 +00:00
Stepan Dyatkovskiy
148692bafe Fix for PR18921 (LDRD/STRD part)::
Removed "GNU Assembler extension (compatibility)" definitions from ARMInstrInfo.td
Fixed ARMAsmParser::ParseInstruction GNU compatability branch, so it also works for thumb mode from now.
Added new tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205622 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 10:17:56 +00:00
Stepan Dyatkovskiy
a669270654 Fixed register class in STRD instruction for Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205612 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 08:14:13 +00:00
Saleem Abdulrasool
5fe5b3dcc8 ARM: update even more tests
More updating of tests to be explicit about the target triple rather than
relying on the default target triple supporting ARM mode.

Indicate to lit that object emission is not yet available for Windows on ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205545 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 17:35:22 +00:00
Saleem Abdulrasool
27b1252c13 ARM: fixup more tests to specify the target more explicitly
This changes the tests that were targeting ARM EABI to explicitly specify the
environment rather than relying on the default.  This breaks with the new
Windows on ARM support when running the tests on Windows where the default
environment is no longer EABI.

Take the opportunity to avoid a pointless redirect (helps when trying to debug
with providing a command line invocation which can be copy and pasted) and
removing a few greps in favour of FileCheck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205541 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 16:01:44 +00:00
Daniel Sanders
769a6f2116 [mips] Add negative tests confirm that supported ISA's don't allow instructions added in later ISA's
Summary:
test/MC/Mips/<isa1>/invalid-<isa2>.s
    Test that <isa1> does not support <isa2>'s instructions.
test/MC/Mips/<isa1>/invalid-<isa2>-xfail.s
    Things that should be invalid but currently aren't. Will XPASS if any
    become invalid.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3262

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205538 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 14:14:22 +00:00
Daniel Sanders
8750f9a291 [mips] Implement ehb, ssnop, and pause in assembler
Summary: Add negative tests for pause

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3246

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205537 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 13:21:51 +00:00
Zoran Jovanovic
4d24300247 Implementation of 16-bit microMIPS instructions MFHI and MFLO.
Differential Revision: http://llvm-reviews.chandlerc.com/D3141


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205532 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 12:47:34 +00:00
Daniel Sanders
8ef79fa708 [mips] Add initial (experimental) MIPS-IV support.
Summary:
Adds the 'mips4' processor and a simple test of the ELF e_flags.

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

I made one small change to the testcase so that it uses
mips64-unknown-linux instead of mips4-unknown-linux.

This patch indirectly adds FeatureCondMov to FeatureMips64. This is ok
because it's supposed to be there anyway and it turns out that
FeatureCondMov is not a predicate of any instructions at the moment
(this is a bug that hasn't been noticed because there are no targets
without the conditional move instructions yet).

CC: theraven

Differential Revision: http://llvm-reviews.chandlerc.com/D3244

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205530 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 12:13:36 +00:00
Zoran Jovanovic
60f5dfea66 MicroMIPS specific little endian fixup data byte ordering.
Differential Revision: http://llvm-reviews.chandlerc.com/D3245


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205528 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 12:01:01 +00:00
Stepan Dyatkovskiy
37e5cfa4aa PR19320:
The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP.
It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205524 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 11:29:15 +00:00
Sasa Stankovic
10914379f6 [mips] Extend MipsMCExpr class to handle %higher(sym1 - sym2 + const) and
%highest(sym1 - sym2 + const) relocations. Remove "ABS_" from VK_Mips_HI
and VK_Mips_LO enums in MipsMCExpr, to be consistent with VK_Mips_HIGHER
and VK_Mips_HIGHEST.

This change also deletes test file test/MC/Mips/higher_highest.ll and moves
its CHECK's to the new test file test/MC/Mips/higher-highest-addressing.s.
The deleted file tests that R_MIPS_HIGHER and R_MIPS_HIGHEST relocations are
emitted in the .o file. Since it uses -force-mips-long-branch option, it was
created when MipsLongBranch's implementation was emitting R_MIPS_HIGHER and
R_MIPS_HIGHEST relocations in the .o file. It was disabled when MipsLongBranch
started to directly calculate offsets.

Differential Revision: http://llvm-reviews.chandlerc.com/D3230


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 10:37:45 +00:00
Kai Nacke
b96fc4a5ea [mips] Add more Octeon cnMips instructions
Adds the instructions ext/ext32/cins/cins32.
It also changes pop/dpop to accept the two operand version and
adds a simple pattern to generate baddu.
Tests for the two operand versions (including baddu/dmul/dpop/pop)
and the code generation pattern for baddu are included.

Reviewed by: Daniel.Sanders@imgtec.com


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205449 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 18:40:43 +00:00
Rafael Espindola
5d853bf42d Work around gold bug http://sourceware.org/PR16794.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205416 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 12:15:20 +00:00
Kai Nacke
54c55edb0a [mips] Add Octeon cnMips instructions mtmX and mtpX
Adds the Octeon cnMips instructions "load multiplier register MPLx" and "load product register Px".
Includes tests.

Reviews by: Daniel.Sanders@imgtec.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205343 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 18:35:26 +00:00
Daniel Sanders
f2452c4cec [mips] Extend ParseJumpTarget to support the full symbol expression syntax.
Summary:
This should fix the issues the D3222 caused in lld. Testcase is based on
the one that failed in the buildbot.

Depends on D3233

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3234

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205298 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 10:41:48 +00:00
Daniel Sanders
bd48d31b37 [mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
  Prior to that point, GPR32's/GPR64's are GPR's regardless of register
  size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
  size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
  symbol aliasing)
  - One consequence is that all registers can be specified numerically
    almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
    but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
  standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
  xfailed now work:
    ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
    c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
  by the predicate and renderer.

Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
  MipsOperand::isReg() will return true for a k_RegisterIndex token
  with Index == 0 and getReg() will return ZERO for this case. Note that it
  doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
  Some more of the generic parser could be removed too (integers and relocs
  for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
  was needed to make it parse correctly. The difficulty was that the matcher
  expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205292 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 10:35:28 +00:00
David Blaikie
a07c1ab4e6 DebugInfo: Avoid creating unnecessary/empty line tables and remove the special case of '0' in DwarfCompileUnit::initStmtList by just always using a label difference
This moves one case of raw text checking down into the MCStreamer
interfaces in the form of a virtual function, even if we ultimately end
up consolidating on the one-or-many line tables issue one day, this is
nicer in the interim. This just generally streamlines a bunch of use
cases into a common code path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205287 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 08:07:52 +00:00
David Blaikie
5b2de5dd3d DebugInfo: Emit relocation to debug_line section when emitting asm for asm
I don't think this is reachable by any frontend (why would you transform
asm to asm+debug info?) but it helps tidy up some of this code, avoid
the weird special case of "emit the first CU, store the label, then emit
the rest" in MCDwarfLineTable::Emit by instead having the
DWARF-for-assembly case use the same codepath as DwarfDebug.cpp, by
registering the label of the debug_line section, thus causing it to be
emitted. (with a special case in asm output to just emit the label since
asm output uses the .loc directives, etc, rather than the debug_loc
directly)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205286 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 07:35:52 +00:00
Rafael Espindola
c298307ae6 Don't relocate with sections if there might be a paired relocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205240 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 19:00:23 +00:00
Daniel Sanders
1c056d8be9 Revert: [mips] Rewrite MipsAsmParser and MipsOperand.' due to buildbot errors in lld tests.
It's currently unable to parse 'sym + imm' without surrounding parenthesis.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205237 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 18:51:43 +00:00
Rafael Espindola
524b776505 Now that this test is assembly, make the checks a bit stronger.
This will be used for a followup patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205232 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 18:01:50 +00:00
Daniel Sanders
8f7dc89e21 [mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
  Prior to that point, GPR32's/GPR64's are GPR's regardless of register
  size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
  size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
  symbol aliasing)
  - One consequence is that all registers can be specified numerically
    almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
    but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
  standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
  xfailed now work:
    ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
    c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
  by the predicate and renderer.

Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
  MipsOperand::isReg() will return true for a k_RegisterIndex token
  with Index == 0 and getReg() will return ZERO for this case. Note that it
  doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
  Some more of the generic parser could be removed too (integers and relocs
  for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
  was needed to make it parse correctly. The difficulty was that the matcher
  expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205229 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 17:43:46 +00:00
Daniel Sanders
e7c7ba0782 [mips] Implement missing relocations in the integrated assembler.
%got_hi, %got_lo, %call_hi, %call_lo, %higher, and %highest are now recognised
by MipsAsmParser::getVariantKind().

To prevent future issues with missing entries in this StringSwitch, I've added
an assertion to the default case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205200 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:15:02 +00:00
Daniel Sanders
857d651ba4 [mips] Remove R_MIPS_GOT which isn't used and shares the same number as R_MIPS_GOT16
Unlike my previous commit, don't try to remove the corresponding VK_Mips_GOT yet
even though it shares the same assembly text since that is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205196 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:47:41 +00:00
Daniel Sanders
1df2ed27dd Revert r205194 - [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16.
There's a couple additional bits I missed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205195 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:34:36 +00:00
Daniel Sanders
1200528f17 [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:30:05 +00:00
NAKAMURA Takumi
6889086ba1 llvm/test/MC/Mips/mips64r2/valid-xfail.s: This REQUIRES asserts. Seems it doesn't fail with -Asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205182 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 13:30:02 +00:00
Daniel Sanders
5900e1db41 [mips] Added a full set of instruction test cases for all ISA's (but not ASE's).
Summary:
Where those ISA's are not currently supported, the test is run with the smallest
superset of that ISA.

Some instructions are valid but don't pass yet. These have been placed in the
valid-xfail.s's which will XPASS if _any_ instruction starts working.

The valid.s's do not verify the encoding yet. There are also no tests checking that instructions from neighbouring ISA's are not accepted.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3214

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205180 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 12:13:12 +00:00
Stepan Dyatkovskiy
b173d9ee35 PR18929:
According to ARM assembler language hash symbol is optional before immediates.
For example, see here for more details:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0473j/dom1359731154529.html



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205157 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 17:09:54 +00:00
NAKAMURA Takumi
2afefa27b3 llvm/test/MC/ELF/nocompression.s: Loosen an expression to match "llvm-mc.EXE".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205148 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 14:04:00 +00:00
Logan Chien
a68f166d60 llvm-mc: Fix build breakage caused by r205050.
When LLVM is not built with zlib, nocompression.s will test
for the error message.  But this test case will cause breakage
because the exit code is non-zero.  This commit fix this issue
by adding "not" to the command.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205102 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 15:10:22 +00:00
Stepan Dyatkovskiy
3fed2f133c Recommitted fix for PR18931, with extended tests set.
Issue subject: Crash using integrated assembler with immediate arithmetic

Fix description:
Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage,
since it is impossible to resolve labels on this stage. In the end of stage we still have
expression (MCExpr).
Then, when we want to encode it, we expect it to be an immediate, but it still an expression.
Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205094 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 13:12:40 +00:00
Tim Northover
7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
Rafael Espindola
224dbf4aec Completely rewrite ELFObjectWriter::RecordRelocation.
I started trying to fix a small issue, but this code has seen a small fix too
many.

The old code was fairly convoluted. Some of the issues it had:

* It failed to check if a symbol difference was in the some section when
  converting a relocation to pcrel.
* It failed to check if the relocation was already pcrel.
* The pcrel value computation was wrong in some cases (relocation-pc.s)
* It was missing quiet a few cases where it should not convert symbol
  relocations to section relocations, leaving the backends to patch it up.
* It would not propagate the fact that it had changed a relocation to pcrel,
  requiring a quiet nasty work around in ARM.
* It was missing comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205076 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 06:26:49 +00:00
David Blaikie
1fc0d63775 Debug Compression: Avoid compression debug_frame for now
Turns out debug_frame does use multiple fragments, so it doesn't
compress correctly with the current approach. Disable compressing it for
now while I figure out what's the best solution for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205059 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 21:48:31 +00:00
David Blaikie
4a9c2585ab llvm-mc: error when -compress-debug-sections is requested and zlib is not linked
This is a bit of a stab in the dark, since I have zlib on my machine.
Just going to bounce it off the bots & see if it sticks.

Do we have some convention for negative REQUIRES: checks? Or do I just
need to add a feature like I've done here?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205050 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 20:45:24 +00:00
Rafael Espindola
efd95481bd Convert one last llc -filetype=obj test.
Unfortunately this one fails deep inside the mips backend, so xfail it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205042 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:58:24 +00:00
Rafael Espindola
5811e45fb2 Convert llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205040 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:41:33 +00:00
Rafael Espindola
24845fbabb Convert llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205039 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:38:20 +00:00
Rafael Espindola
830ce8a06e Remove bogus test.
It was using "lc  -filetype=obj" just to pass the result to
"llvm-objdupm -disassemble" and then filecheck assembly.

The CHECK-NOT would never match anyway since it was missing $.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205036 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:26:05 +00:00
Rafael Espindola
e3b7d0228d Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205033 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:19:28 +00:00
Rafael Espindola
a53735bcf1 Map ELf flags back to more specific section kinds.
With that, convert another llc -filetype=obj test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205031 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:14:08 +00:00
Rafael Espindola
be560a3fb7 Parse .gpdword and convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205028 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 18:50:26 +00:00
Rafael Espindola
904658f8d4 convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205027 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 18:34:31 +00:00
Rafael Espindola
6b63578aab Convert "llc -filetype=obj" test into llvm-mc tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205026 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 18:30:07 +00:00
David Blaikie
b91f51161f Only test compression when linked with zlib.
I'll implement error handling and a negative test in both llvm-mc and
Clang soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205016 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 17:04:53 +00:00
Christian Pirker
1f072c36d0 Add ARM big endian Target (armeb, thumbeb)
Reviewed at http://llvm-reviews.chandlerc.com/D3095



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205007 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 14:35:30 +00:00
David Blaikie
0a0c4cc56f DebugInfo: Support for compressed debug info sections
1) When creating a .debug_* section and instead create a .zdebug_
   section.
2) When creating a fragment in a .zdebug_* section, make it a compressed
   fragment.
3) When computing the size of a compressed section, compress the data
   and use the size of the compressed data.
4) Emit the compressed bytes.

Also, check that only if a section has a compressed fragment, then that
is the only fragment in the section.

Assert-fail if the fragment's data is modified after it is compressed.

Initial review on llvm-commits by Eric Christopher and Rafael Espindola.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204958 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 20:45:58 +00:00
Daniel Sanders
16dc6ed33f [mips] Attempting to use register $32 should be an error instead of an assertion.
Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3201

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204932 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 15:00:44 +00:00
Daniel Sanders
743cf74530 [mips] Add support for .cpsetup
Summary:
Patch by Robert N. M. Watson
His work was sponsored by: DARPA, AFRL

Small corrections by myself.

CC: theraven, matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3199

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204924 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 13:52:53 +00:00
Elena Demikhovsky
61785a0c3d AVX-512: Implemented masking for integer arithmetic & logic instructions.
By Robert Khasanov rob.khasanov@gmail.com


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204906 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 09:45:08 +00:00
Stepan Dyatkovskiy
fee5d23404 Rejected r204899 and r204900 due to remaining test failures on cmake-llvm-x86_64-linux buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204901 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 08:38:18 +00:00
Stepan Dyatkovskiy
a36286cb49 Fixed test for r204899 (pr18931 fix)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204900 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 08:20:26 +00:00
Stepan Dyatkovskiy
fccc6901d6 Fix for pr18931: Crash using integrated assembler with immediate arithmetic
Fix description:
Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage,
since it is impossible to resolve labels on this stage. In the end of stage we still have
expression (MCExpr).
Then, when we want to encode it, we expect it to be an immediate, but it still an expression.
Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204899 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 07:49:39 +00:00
Jiangning Liu
09b4588309 ARM: raise error message when complex SO expressions can't really be
solved as a constant at compilation time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204898 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 07:42:58 +00:00
Rafael Espindola
e459f72ee0 Correctly propagates st_size.
This also finally removes a bogus call to AliasedSymbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204883 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 00:28:24 +00:00
Kevin Enderby
9efa4ff901 Fix the ARM VST4 (single 4-element structure from one lane)
size 16 double-spaced registers instruction printing.

This:
	vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!

was being printed as:

	vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]!

rdar://16435096


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204847 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 19:35:40 +00:00
Matheus Almeida
8e7aa4be58 [mips] Use TwoOperandAliasConstraint for ArithLogicR instructions.
This enables TableGen to generate an additional two operand matcher
for our ArithLogicR class of instructions (constituted by 3 register operands).
E.g.: and $1, $2 <=> and $1, $1, $2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204826 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 16:09:43 +00:00
Matheus Almeida
75203b6d11 [mips] Add support to the '.dword' directive.
The '.dword' directive accepts a list of expressions and emits
them in 8-byte chunks in successive locations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204822 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 15:44:18 +00:00
Matheus Almeida
5957d10b41 [mips] Add support to '.set mips64'.
The '.set mips64' directive enables the feature Mips:FeatureMips64
from assembly. Note that it doesn't modify the ELF header as opposed
to the use of -mips64 from the command-line. The reason for this
is that we want to be as compatible as possible with existing assemblers
like GAS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204817 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 15:14:32 +00:00
Matheus Almeida
53ccc093bf [mips] Add support to '.set mips64r2'.
The '.set mips64r2' directive enables the feature Mips:FeatureMips64r2
from assembly. Note that it doesn't modify the ELF header as opposed
to the use of -mips64r2 from the command-line. The reason for this
is that we want to be as compatible as possible with existing assemblers
like GAS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204815 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 14:52:22 +00:00
Matheus Almeida
0de31d52d5 [mips] Add support for '.option pic2'.
The directive '.option pic2' enables PIC from assembly source.
At the moment none of the macros/directives check the PIC bit
but that's going to be fixed relatively soon. For example, the
expansion of macros like 'la' depend on the relocation model.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204803 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 13:40:29 +00:00
Daniel Sanders
23f0634162 [mips] Add tests for t0-t3 for N32/N64
These are aliases of t4-t7 and are provided for compatibility with both the
original ABI documentation (using t4-t7) and GNU As (using t0-t3)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204797 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 11:46:34 +00:00
Daniel Sanders
968ea7b82c [mips] The register names depend on the ABI being N32/N64 rather than the arch being mips64
Summary: Added test cases for O32 and N32 on MIPS64.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3175

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204796 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 11:39:07 +00:00
Daniel Sanders
95f4d65d4f [mips] $s8 is an alias for $fp in all ABI's, not just N32/N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204793 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 11:05:24 +00:00
Daniel Sanders
d431e0a20a [mips] Move the CHECK lines in mips*-register-names.s to make it more obvious which CHECK matches with which insn
This reveals a small mistake in mips-register-names.s ($sp is tested twice and
$s8 is not tested) which will be fixed in a follow-up commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204792 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 10:54:30 +00:00
Rafael Espindola
3008f80562 Correctly detect if a symbol uses a reserved section index or not.
The logic was incorrect for variables, causing them to end up in the wrong
section if the section had an index >= 0xff00.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204771 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 00:16:43 +00:00
Rafael Espindola
81c66bcc13 Create .symtab_shndxr only when needed.
We need .symtab_shndxr if and only if a symbol references a section with an
index >= 0xff00.

The old code was trying to figure out if the section was needed ahead of time,
making it a fairly dependent on the code actually writing the table. It was
also somewhat conservative and would create the section in cases where it was
not needed.

If I remember correctly, the old structure was there so that the sections were
created in the same order gas creates them. That was valuable when MC's support
for ELF was new and we tested with elf-dump.py.

This patch refactors the symbol table creation to another class and makes it
obvious that .symtab_shndxr is really only created when we are about to output
a reference to a section index >= 0xff00.

While here, also improve the tests to use macros. One file is one section
short of needing .symtab_shndxr, the second one has just the right number.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204769 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-25 23:44:25 +00:00
Daniel Sanders
3527e5fcb3 [mips] '.set at=$0' should be equivalent to '.set noat'
Differential Revision: http://llvm-reviews.chandlerc.com/D3171

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204714 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-25 13:01:06 +00:00
Daniel Sanders
c7e1663c24 [mips] Correct testcase for .set at=$reg and emit the new warnings for numeric registers too.
Summary:
Remove the XFAIL added in my previous commit and correct the test such that
it correctly tests the expansion of the assembler temporary.

Also added a test to check that $at is always $1 when written by the
user.

Corrected the new assembler temporary warnings so that they are emitted for
numeric registers too.

Differential Revision: http://llvm-reviews.chandlerc.com/D3169

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204711 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-25 11:16:03 +00:00
Daniel Sanders
c141b331b9 [mips] Fix assembler temporary expansion and add associated warnings about the use of $at.
Summary:
The assembler temporary is normally $at ($1) but can be reassigned using
'.set at=$reg'. Regardless of which register is nominated as the assembler
temporary, $at remains $1 when written by the user.

Adds warnings under the following conditions:
* The register nominated as the assembler temporary is used by the user.
* '.set noat' is in effect and $at is used by the user.
Both of these only work for named registers. I have a follow up commit that makes it work for numeric registers as well.

XFAIL set-at-directive.s since it incorrectly tests that $at is redefined by
'.set at=$reg'. Testcases will follow in a separate commit.

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

Differential Revision: http://llvm-reviews.chandlerc.com/D3167

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204710 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-25 10:57:07 +00:00
Kevin Enderby
4a88cd08da Fix crashes when assembler directives are used that are not
for Mach-O object files by generating an error instead.

rdar://16335232


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204687 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-25 00:05:50 +00:00
Ulrich Weigand
47eac58333 [PowerPC] Generate little-endian object files
As a first step towards real little-endian code generation, this patch
changes the PowerPC MC layer to actually generate little-endian object
files.  This involves passing the little-endian flag through the various
layers, including down to createELFObjectWriter so we actually get basic
little-endian ELF objects, emitting instructions in little-endian order,
and handling fixups and relocations as appropriate for little-endian.

The bulk of the patch is to update most test cases in test/MC/PowerPC
to verify both big- and little-endian encodings.  (The only test cases
*not* updated are those that create actual big-endian ABI code, like
the TLS tests.)

Note that while the object files are now little-endian, the generated
code itself is not yet updated, in particular, it still does not adhere
to the ELFv2 ABI.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 18:16:09 +00:00