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00c53caa33
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11815 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
00c53caa33 Use MachineInstr::readsWritesVirtualRegister to determine if a register is read. 
This correctly handles partial redefines and undef uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104322 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen
63e6a488cb If the first definition of a virtual register is a partial redef, add an 
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104320 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 16:32:16 +00:00
Matt Fleming
d8a33ddcfe Currently, createMachOStreamer() is invoked directly in llvm-mc which 
isn't ideal if we want to be able to use another object file format.

Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 12:54:43 +00:00
Matt Fleming
924c5e58f2 Add support for parsing the ELF .type assembler directive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104316 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 11:36:59 +00:00
Lang Hames
24cdd2f82c Removed scaleNumbering method declaration from LiveInterval (not defined, not used). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104311 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 03:04:04 +00:00
Evan Cheng
1cc3984148 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 23:26:43 +00:00
Devang Patel
6ed0ce3240 Rename variable. add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104274 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:35:24 +00:00
Daniel Dunbar
4072886a69 tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor 
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:20:32 +00:00
Evan Cheng
15a16def6e Add a hybrid bottom up scheduler that reduce register usage while avoiding 
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104216 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 06:13:19 +00:00
Eric Christopher
51f5d6af8c Fix build by actually declaring the variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 00:59:30 +00:00
Eric Christopher
c1a887d76d Partial code for emitting thread local bss data. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104197 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 00:49:07 +00:00
Jim Grosbach
309d20c89c Fix the post-RA instruction scheduler to handle instructions referenced by 
more than one dbg_value instruction. rdar://7759363


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104174 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 22:57:06 +00:00
Jakob Stoklund Olesen
7ebc4d63db Add MachineInstr::readsVirtualRegister() in preparation for proper handling of 
partial redefines.

We are going to treat a partial redefine of a virtual register as a
read-modify-write:

  %reg1024:6 = OP

Unless the register is fully clobbered:

  %reg1024:6 = OP, %reg1024<imp-def>

MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104149 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 20:36:22 +00:00
Evan Cheng
211ffa1351 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 20:19:50 +00:00
mike-m
eb75870206 Fix enum to address array bounds regression. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104058 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 21:22:12 +00:00
Eric Christopher
4d01cbe93b Make EmitTBSSSymbol take a section argument so that we can find it later. 
Fix up callers and users.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104057 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 21:16:04 +00:00
Kevin Enderby
ebe7fcd041 Added support in MC for Directional Local Labels. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103989 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 23:08:19 +00:00
Eric Christopher
c6177a4531 More data/parsing support for tls directives. Add a few more testcases 
and cleanup comments as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103985 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 22:53:55 +00:00
Daniel Dunbar
9a744e3860 MC: Add dyn_cast support to MCSection. 
- Of questionable utility, since in general anything which wants to do this should probably be within a target specific hook, which can rely on the sections being of the appropriate type. However, it can be useful for short term hacks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103980 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 21:54:26 +00:00
Eric Christopher
423c9e3e58 Add some section and constant support for darwin TLS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103974 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 21:02:07 +00:00
Jakob Stoklund Olesen
b843d9f833 Optimize empty DenseMap iteration. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103962 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 20:01:24 +00:00
Daniel Dunbar
525a3a67c1 llvm-mc: Support reassignment of variables in one special case, when the 
variable has not yet been used in an expression. This allows us to support a few
cases that show up in real code (mostly because gcc generates it for Objective-C
on Darwin), without giving up a reasonable semantic model for assignment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 17:46:23 +00:00
Zhongxing Xu
bae5210321 Remove unused member variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103936 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 09:47:55 +00:00
Anton Korobeynikov
ded05e34b6 Add support for thiscall calling convention. 
Patch by Charles Davis and Steven Watanabe!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103902 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-16 09:08:45 +00:00
Chris Lattner
4c297c9153 improve portability to systems that don't have round, patch by 
Evzen Muller!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103877 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 17:11:55 +00:00
Jakob Stoklund Olesen
c66c78c684 Add reg_nodbg_iterator 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103856 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 02:52:58 +00:00
Evan Cheng
06b666c705 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also 
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 02:18:07 +00:00
Evan Cheng
b990a2f249 Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE 
instructions.

e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12

After REG_SEQUENCE is eliminated, we are left with:

%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5

The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible, 
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 23:21:14 +00:00
Dan Gohman
fd72617688 Add some comments about undef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103834 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 23:01:02 +00:00
Bill Wendling
b92187a410 Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what 
the variable actually tracks.

N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103802 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 21:14:32 +00:00
Devang Patel
98e1cac52c Add support to preserve type info for the variables that are removed by the optimizer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103798 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 21:01:35 +00:00
Dan Gohman
8090e214f7 Use PassManagerBase, to give clients the option of using either 
FunctionPassManager or regular PassManager.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103773 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 15:35:10 +00:00
Dan Gohman
89938ce0ad Add an isNodeHidden to the graph traits, to support definition of 
subgraph views.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103772 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 15:29:31 +00:00
Evan Cheng
0ebf356ddf Get rid of the bit twiddling to read / set OpActions and ValueTypeActions. The small saving in memory isn't worth the increase in runtime and code complexity in my opinion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103768 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 07:37:40 +00:00
Eric Christopher
482eba054a Add AsmParser support for darwin tbss directive. 
Nothing uses this yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103757 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 01:50:28 +00:00
Nick Lewycky
3fa0c8ca96 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103755 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 01:02:48 +00:00
Daniel Dunbar
47b3ec4daa MC: Switch to completely lazy layout. 
- The eliminates the last major algorithmic problem with MC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103754 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 00:51:14 +00:00
Daniel Dunbar
9005d45a99 MC: Extend MCAsmLayout to explicitly track which fragments have been layed out, and enforce several invariants to LayoutFragment to ensure we only do layout in a sensible order. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103753 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 00:37:21 +00:00
Daniel Dunbar
337718e09c MC: Switch MCFragment to storing the layout order index, not its index in the file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103751 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 00:37:14 +00:00
Daniel Dunbar
afc6acdab7 MC: Change LayoutSection() to only do the section initializiation. 
Also, elimminate MCAsmLayout::set*, which are no longer needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103750 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 00:37:11 +00:00
Evan Cheng
dbf67fefea Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 23:55:47 +00:00
Evan Cheng
b9c0e332b3 Eliminate use of magic numbers to access OpActions. It also has the effect of allowing more than 31 scalar value types. MAX_ALLOWED_VALUETYPE had already been updated to 64 a while back. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103743 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 23:25:21 +00:00
Evan Cheng
b21f5a5511 Fix up LoadExtActions, TruncStoreActions, and IndexedModeActions representation and setter and getter's so they will continue to work if the number of scalar ValueType's exceeds 31. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103742 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 23:01:26 +00:00
Daniel Dunbar
b69fc044db MC: Move Layout{Fragment,Section} into MCAsmLayout, and add LayoutFile(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103738 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 20:40:12 +00:00
Dan Gohman
e6cd757e68 Teach MachineLICM and MachineSink how to clear kill flags conservatively 
when they move instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103737 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 20:34:42 +00:00
Evan Cheng
1e5a6c46b8 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103733 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 20:14:58 +00:00
Dan Gohman
49b4589978 Add a utility function for conservatively clearing kill flags, and make 
use of it in MachineCSE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103726 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 19:24:00 +00:00
Daniel Dunbar
2c18d3b0fe MC: Factor out MCAssembler::ComputeFragmentSize. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103724 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 18:35:06 +00:00
Daniel Dunbar
f1fd2288f3 Fix const ilist_node::get{Prev,Next}Node() to actually compile. Picky, picky. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103723 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 18:35:02 +00:00
Daniel Dunbar
f60c736c64 MC: Add section layout order indices to MCSectionData. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103715 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 15:17:26 +00:00