Bruno Cardoso Lopes
01f0847ce8
Fix comment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 01:28:51 +00:00
Bruno Cardoso Lopes
5e5342b0a8
- Use specific nodes to match unpckl masks.
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- Teach getShuffleScalarElt how to handle more target
specific nodes, so the DAGCombine can make use of it.
- Add another hack to avoid the node update problem
during legalization. More description on the comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 01:24:00 +00:00
Eric Christopher
e5734105da
Simple branch instruction support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112923 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 00:35:47 +00:00
Jakob Stoklund Olesen
3061c4442e
Don't call Predicate_* from X86 target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112921 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 00:35:18 +00:00
Jakob Stoklund Olesen
7853cd0bea
Remove Predicate_* calls from MBlaze and XCore
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112920 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 00:35:16 +00:00
Jakob Stoklund Olesen
7fa846f7d9
Remove Predicate_* calls from Mips
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 00:35:13 +00:00
Eric Christopher
56d2b72884
Add basic support for materializing constants (including fp) and
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stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 23:43:26 +00:00
Anton Korobeynikov
ace53f2fbc
Properly emit __chkstk call instead of __alloca on non-mingw windows targets.
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Patch by Cameron Esfahani!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 23:03:46 +00:00
Bruno Cardoso Lopes
ed5c711a6e
Move insertps mask decoding to header file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 22:43:39 +00:00
Anton Korobeynikov
c7c62bb3ca
Revert win64 changes. They seem to be incomplete
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112885 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 22:31:32 +00:00
Jim Grosbach
1755b3964f
For ARM stack frames that utilize variable sized objects and have either
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large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs.
rdar://7352504
rdar://8374540
rdar://8355680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 22:29:01 +00:00
Anton Korobeynikov
2f4fad99ea
Properly allocate win64 shadow reg area.
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Patch by Jan Sjodin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 22:16:28 +00:00
Bruno Cardoso Lopes
5594560766
Move decoding of insertps back to avoid unused warnings in x86 isel lowering, and fix movlhps/movhlps to decode 4 elements shuffles
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 21:51:11 +00:00
Dan Gohman
24bde5bce1
Don't narrow the load and store in a load+twiddle+store sequence unless
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there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.
This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 21:18:42 +00:00
Jim Grosbach
5c33f5bf67
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 19:52:39 +00:00
Jim Grosbach
3e234e7579
remove trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112847 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 18:44:51 +00:00
Bruno Cardoso Lopes
6b1d0a3b36
Move x86 specific shuffle mask decoding to its own header, it's also going to be used elsewhere. Also trim trailing whitespaces
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112846 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 18:40:13 +00:00
Jim Grosbach
bb5a039b76
handle case where a register class is specified
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 18:18:52 +00:00
Jim Grosbach
e7c1416263
Now that register allocation properly considers reserved regs, simplify the
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ARM register class allocation order functions to take advantage of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 18:14:29 +00:00
Jim Grosbach
5a0fabae5a
Mask out reserved registers when constructing the set of allocatable regs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112828 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 16:31:21 +00:00
Bob Wilson
82a9c8480e
Fill in a missing comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112826 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 16:17:29 +00:00
Bob Wilson
ffde080ae6
Convert VLD1 and VLD2 instructions to use pseudo-instructions until
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after regalloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 16:00:54 +00:00
Bruno Cardoso Lopes
3722f007b6
Replace unpckl_undef and unpckh_undef matching with target specific opcodes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112806 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 05:23:12 +00:00
Bruno Cardoso Lopes
dd69db858c
Move condition out to prepare for more matching
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112805 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 04:20:26 +00:00
Bruno Cardoso Lopes
ad10fb2b56
Remove checking for isUNPCKL_v_undef_Mask, the specific node is already emitted for it
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112804 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 03:57:58 +00:00
Bruno Cardoso Lopes
d00bfe1f8d
become more strict about when it's safe to use X86ISD::MOVLPS
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 02:35:51 +00:00
Eric Christopher
1f58741aab
Clang's -ccc-host-triple was ignoring the arch specifier on my triple,
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I don't need to implement this quite yet - and not for ConstantInt anyhow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 02:30:46 +00:00
Eric Christopher
1b61ef4b22
This should be TargetMaterializeConstant instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112795 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 01:48:11 +00:00
Eric Christopher
eaa204b2f8
One definition of isThumb is plenty, thanks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112793 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 01:39:14 +00:00
Jim Grosbach
b0739b7833
Remove trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 01:02:06 +00:00
Eric Christopher
318b6eec8d
Rework arm fast-isel load and store handling. Move offset computation
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into the "address selection" routine and handle constant materialization
for stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 00:53:56 +00:00
Jim Grosbach
7af3a345a9
trivial cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112779 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 00:02:26 +00:00
Jim Grosbach
352f23529c
Simplify the tGPR register class now that the register allocators know not
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to try to allocate reserved registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112774 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 23:50:23 +00:00
Bob Wilson
d0b69cf119
Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,
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add, and subtract operations with zero-extended or sign-extended vectors.
Update tests. Add auto-upgrade support for the old intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 23:50:19 +00:00
Bruno Cardoso Lopes
4783a3ee13
Revert r112689, avoid those kind of checks cause they mess up with mmx
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 22:59:03 +00:00
Bruno Cardoso Lopes
29c353b9c3
Using target specific nodes for shuffle nodes makes the mask
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check more strict, breaking some cases not checked in the
testsuite, but also exposes some foldings not done before,
as this example:
movaps (%rdi), %xmm0
movaps (%rax), %xmm1
movaps %xmm0, %xmm2
movss %xmm1, %xmm2
shufps $36, %xmm2, %xmm0
now is generated as:
movaps (%rdi), %xmm0
movaps %xmm0, %xmm1
movlps (%rax), %xmm1
shufps $36, %xmm1, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 22:33:20 +00:00
Eric Christopher
543cf05b9c
Some basic store support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112752 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 22:16:27 +00:00
Eric Christopher
4e68c7cca4
Add some more load types in.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112721 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 18:01:32 +00:00
Chris Lattner
14ab39e43f
zap dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 16:04:34 +00:00
Chris Lattner
5bcb8a6112
temporarily revert r112664, it is causing a decoding conflict, and
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the testcases should be merged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 16:00:50 +00:00
Bruno Cardoso Lopes
56098f5d26
Use movlps, movlpd, movss and movsd specific nodes instead of pattern matching with movlp pattern fragment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 05:08:25 +00:00
Bruno Cardoso Lopes
9cfad89a68
minor change, simplify some logic
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112689 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:57:08 +00:00
Bruno Cardoso Lopes
e654b56eb1
Move some functions around so they can be used for some other to come function
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:51:36 +00:00
Bill Wendling
43a6c5e2fc
We have a chance for an optimization. Consider this code:
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int x(int t) {
if (t & 256)
return -26;
return 0;
}
We generate this:
tst.w r0, #256
mvn r0, #25
it eq
moveq r0, #0
while gcc generates this:
ands r0, r0, #256
it ne
mvnne r0, #25
bx lr
Scandalous really!
During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):
%r0 = ISD::AND ...
ARMISD::CMPZ %r0, 0 @ sets [CPSR]
%r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR]
All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112664 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 22:41:22 +00:00
Bruno Cardoso Lopes
013bb3dee9
Use x86 specific MOVSLDUP node, add more patterns to match it and remove useless load nodes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 22:35:05 +00:00
Bruno Cardoso Lopes
5023ef281c
Use x86 specific MOVSHDUP node and add more patterns to match it
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112657 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 22:22:11 +00:00
Bill Wendling
2d811d38d4
And ANDS pattern to match the t2ANDS pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 22:05:37 +00:00
Jakob Stoklund Olesen
63b1dbaadd
Make %EFLAGS unallocatable.
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No CCR virtual registers should exist, and %EFLAGS is used in ways that can
surprise RegAllocFast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112650 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 21:51:07 +00:00
Bruno Cardoso Lopes
7ff30bb1a5
Use MOVHLPS node instead of matching using movhlps and movhlps_undef pattern fragments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112644 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 21:38:49 +00:00
Bruno Cardoso Lopes
f2db5b48d0
Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some useless nodes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 21:15:21 +00:00