Commit Graph

265 Commits

Author SHA1 Message Date
Craig Topper
420761a0f1 Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 07:30:17 +00:00
Jakob Stoklund Olesen
f16936e592 Deduplicate ARM call-related instructions.
We had special instructions for iOS because r9 is call-clobbered, but
that is represented dynamically by the register mask operands now, so
there is no need for the pseudo-instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154144 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-06 00:04:58 +00:00
Craig Topper
acf2077ca4 Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153421 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-25 23:49:58 +00:00
Jim Grosbach
7b25ecf6ad ARM BL/BLX instruction fixups should use relocations.
We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.

To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.

rdar://10927209

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 21:36:23 +00:00
Owen Anderson
4f8dc7b17a Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 18:37:29 +00:00
David Blaikie
4d6ccb5f68 More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:51:11 +00:00
Evan Cheng
7c2a4a30e0 First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:12:01 +00:00
Bill Wendling
fe31e67350 Use the new ARMConstantPoolSymbol class to handle external symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 08:58:29 +00:00
Bill Wendling
5bb779976a Switch over to using ARMConstantPoolConstant for global variables, functions,
and block addresses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 08:00:54 +00:00
Eli Friedman
885f1a0c04 Zap some junk from the ARM instruction descriptions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 02:29:58 +00:00
Jim Grosbach
b6aed508e3 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 18:37:27 +00:00
Jim Grosbach
a77295db19 Thumb2 assembly parsing and encoding for LDRD(immediate).
Refactor operand handling for STRD as well. Tests for that forthcoming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:07:06 +00:00
Jim Grosbach
8e0c7697fd Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:46:15 +00:00
Owen Anderson
f1eab597b2 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 23:32:08 +00:00
Jim Grosbach
70939ee141 ARM clean up the imm_sr operand class representation.
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 21:51:27 +00:00
Owen Anderson
6d74631062 Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 20:42:17 +00:00
Jim Grosbach
7ce057983e ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03 23:50:40 +00:00
Jim Grosbach
fb8989e640 ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 21:09:25 +00:00
Jim Grosbach
85bfd3b023 ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 21:28:43 +00:00
Owen Anderson
152d4a4bb6 Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 23:38:37 +00:00
Evan Cheng
ee04a6d3a4 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 23:34:39 +00:00
Evan Cheng
e837dead3c - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 19:10:37 +00:00
Bruno Cardoso Lopes
895c1e2dee Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 03:33:27 +00:00
Mon P Wang
183c627d89 Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131085 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-09 17:47:27 +00:00
Eric Christopher
33c110e602 Fix the non-MC encoding of pkhbt and pkhtb.
Patch by Stephen Hines.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131045 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-07 04:37:27 +00:00
Bill Wendling
3116dce338 Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
expand the testing of the narrowing shift right instructions.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07 23:38:41 +00:00
Bob Wilson
58f04fd22a PR8053: Fix encoding of S bit in some ARM instructions.
Patch by Zonr Chang!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126967 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03 23:07:15 +00:00
Bill Wendling
a656b63ee4 Narrow right shifts need to encode their immediates differently from a normal
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01 01:00:59 +00:00
Jason W Kim
685c350ae7 Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.
(yes, this is different from R_ARM_CALL)

- Adds a new method getARMBranchTargetOpValue() which handles the
  necessary distinction between the conditional and unconditional br/bl
  needed for ARM/ELF

At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...

Added a few FIXME's for future naming fixups in ARMInstrInfo.td




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-04 19:47:15 +00:00
Bruno Cardoso Lopes
a461d42228 Add support for parsing and encoding ARM's official syntax for the BFI instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123770 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18 20:45:56 +00:00
Evan Cheng
7597212abc Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123369 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-13 07:58:56 +00:00
Jim Grosbach
d40963c406 Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 22:28:03 +00:00
Bill Wendling
f4caf69720 The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 03:36:38 +00:00
Owen Anderson
a838a25d59 Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
process cleaner.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 00:36:49 +00:00
Owen Anderson
6b8719fd7d Revert r121721, which broke buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 22:51:08 +00:00
Owen Anderson
e8d02539d7 Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121721 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 22:29:52 +00:00
Owen Anderson
c266600bec In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
as a "long" direct branch.  While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches.  Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 19:31:11 +00:00
Owen Anderson
0f4b60d43a Fix encoding of Thumb1 LDRB and STRB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121581 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:11:13 +00:00
Jim Grosbach
e246717c3a Thumb unconditional branch binary encoding. rdar://8754994
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 18:21:33 +00:00
Jim Grosbach
0108645139 Thumb conditional branch binary encodings. rdar://8745367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 17:13:40 +00:00
Bill Wendling
272df516d7 Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the
t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121417 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 21:49:07 +00:00
Jim Grosbach
027d6e8d1c Rename the encoder method for t_cbtarget to match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 19:04:53 +00:00
Bill Wendling
09aa3f0ef3 The BLX instruction is encoded differently than the BL, because why not? In
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.

Attempt to get the encoding at slightly more correct with this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121336 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 00:39:08 +00:00
Bill Wendling
dff2f7151f Support the "target" encodings for the CB[N]Z instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121308 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 23:01:43 +00:00
Bill Wendling
b8958b031e Add support for loading from a constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 01:57:09 +00:00
Jim Grosbach
d967cd096a Binary encoding for ARM tLDRspi and tSTRspi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121186 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 21:50:47 +00:00
Jim Grosbach
662a816e89 Add fixup for Thumb1 BL/BLX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 23:57:07 +00:00
Bill Wendling
cf590263cd Add a post encoder method to the VFP instructions to convert them to the Thumb2
encoding if we're in that mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 21:54:50 +00:00
Jim Grosbach
5d14f9be7b Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120594 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 19:47:31 +00:00
Owen Anderson
9d63d90de5 Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 19:18:46 +00:00