Bill Wendling
1fd374e9c1
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
...
t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 22:57:21 +00:00
Owen Anderson
0e1bcdf4f7
Add encoding support for Thumb2 PLD and PLI instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120449 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 19:19:31 +00:00
Bill Wendling
ef4a68badb
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
...
certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120408 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 07:44:32 +00:00
Jim Grosbach
532c2f1d50
Rename BX/BRIND/etc patterns to clarify which is actually the BX instruction
...
and which are pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:24:05 +00:00
Owen Anderson
6af50f7dd1
Correct Thumb2 encodings for a much wider range of loads and stores.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:14:31 +00:00
Bob Wilson
8e0c7b5287
Fix the encoding of VLD4-dup alignment.
...
The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function. Use it
for all the VLD-dup instructions for the sake of consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:00:42 +00:00
Owen Anderson
75579f739f
Provide Thumb2 encodings for basic loads and stores.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120340 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 22:44:32 +00:00
Bill Wendling
20272a7c5a
Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the same
...
value that the one in ARMMCCodeEmitter.cpp does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 00:26:37 +00:00
Jim Grosbach
817c1a6ddd
Minor cleanups to a few llvm_unreachable() calls.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 00:27:09 +00:00
Jason W Kim
837caa9313
Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
...
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18 23:37:15 +00:00
Jim Grosbach
85eb54cf0c
Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark
...
it as such. Add some encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17 23:33:14 +00:00
Jim Grosbach
0129be281e
Fix comment typo.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17 21:57:51 +00:00
Bill Wendling
2567eec423
The machine instruction no longer encodes the submode as a separate operand. We
...
should get the submode from the load/store multiple instruction's opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17 05:31:09 +00:00
Jim Grosbach
99f53d13ef
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119180 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 20:47:07 +00:00
Evan Cheng
893d7fe209
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:03:38 +00:00
Owen Anderson
5de6d841a5
First stab at providing correct Thumb2 encodings, start with adc.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118924 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 21:12:40 +00:00
Owen Anderson
8f14391314
Fill out support for Thumb2 encodings of NEON instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 23:12:55 +00:00
Owen Anderson
57dac88f77
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 21:36:43 +00:00
Owen Anderson
c7139a6f0d
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
...
More tests to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 19:07:48 +00:00
Jim Grosbach
c466b937db
Encoding of destination fixup for ARM branch and conditional branch
...
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118801 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 18:04:49 +00:00
Jim Grosbach
7eab97f260
Encoding for ARM LDRSH_POST.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 16:55:29 +00:00
Jim Grosbach
570a922691
ARM STRH encoding information.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 01:09:40 +00:00
Jim Grosbach
5d5eb9e381
ARM LDM encoding for the mode (ia, ib, da, db) operand.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:38:36 +00:00
Jim Grosbach
54fea632b1
Add encoder method for ARM load/store shifted register offset operands.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 17:20:53 +00:00
Bill Wendling
92b5a2eb16
The MC code couldn't handle ARM LDR instructions with negative offsets:
...
vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:49:29 +00:00
Bill Wendling
5df0e0a61d
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
...
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:31:46 +00:00
Owen Anderson
a2b50b300e
Rename encoder methods to match naming convention.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118093 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:28:01 +00:00
Owen Anderson
cf667be17b
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 01:24:55 +00:00
Owen Anderson
d9aa7d30aa
Add correct NEON encodings for the "multiple single elements" form of vld.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 00:05:05 +00:00
Jim Grosbach
6b5252db2d
Encode the register list operands for ARM mode LDM/STM instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 00:37:59 +00:00
Jim Grosbach
c4bc2111a7
80 column fix.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117741 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:21:57 +00:00
Jim Grosbach
0d2d2e9246
s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
...
encoder functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117738 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:19:55 +00:00
Jim Grosbach
7e3383c007
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
...
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 23:12:14 +00:00
Owen Anderson
498ec20703
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
...
for specifying fractional bits for fixed point conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 22:49:00 +00:00
Jim Grosbach
ccf72caa92
JIT imm12 encoding for constant pool entry references.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117483 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 20:39:40 +00:00
Jim Grosbach
f31430f6ec
ARM JIT fix for LDRi12 and company.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117478 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 19:55:59 +00:00
Jim Grosbach
093177d5cd
The new LDR* instruction patterns should handle the necessary encoding of
...
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 17:52:51 +00:00
Jim Grosbach
3e55612472
First part of refactoring ARM addrmode2 (load/store) instructions to be more
...
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 22:37:02 +00:00
Gabor Greif
41f31ef28e
fix memory-layout assumption which only holds on little-endian systems
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 23:16:11 +00:00
Jim Grosbach
3fea19105d
ARM Binary encoding information for BFC/BFI instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 22:03:21 +00:00
Bill Wendling
7d31a169af
Add encodings for movement between ARM core registers and single-precision
...
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116961 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 22:44:54 +00:00
Bill Wendling
07fda9f9b6
ARMCodeEmitter::emitMiscInstruction is dead. Long live
...
ARMCodeEmitter::emitMiscInstruction!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116644 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 23:35:12 +00:00
Jim Grosbach
8abe32af38
ARM mode encoding information for UBFX and SBFX instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 17:15:16 +00:00
Jim Grosbach
792e9796b3
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
...
pseudonym.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116512 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 20:43:44 +00:00
Bill Wendling
946a2740a5
Add encoding for 'fmstat'.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 01:19:34 +00:00
Bill Wendling
88cf038436
- Add encodings for multiply add/subtract instructions in all their glory.
...
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116464 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 01:02:08 +00:00
Jim Grosbach
b35ad41fef
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 19:56:10 +00:00
Jim Grosbach
ef324d7044
Add the rest of the ARM so_reg encoding options (register shifted register)
...
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:53:58 +00:00
Jim Grosbach
2a6a93d542
Move the ARM so_imm encoding into a custom operand encoder and remove the
...
explicit handling of the instructions referencing it from the MC code
emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116367 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:18:08 +00:00
Jim Grosbach
08bd54987f
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
...
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:00:24 +00:00
Jim Grosbach
3e09413c2c
Reapply 116059, this time without the fatfingered pasto at the top.
...
''const'ify getMachineOpValue() and associated helpers.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 17:45:54 +00:00
Jim Grosbach
2cee75a254
Reverting 116059. Bots are unhappy with it.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 17:28:40 +00:00
Jim Grosbach
461caba214
'const'ify getMachineOpValue() and associated helpers.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 16:52:44 +00:00
Jim Grosbach
bade37bb8b
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:21:28 +00:00
Jim Grosbach
a4c3c8f28d
move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
...
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114016 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 20:26:25 +00:00
Jim Grosbach
7e2c04fd05
Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. Check
...
if the register is a member of the SPR register class directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:44:57 +00:00
Chris Lattner
17aa68055b
zap dead code.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113073 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-04 18:12:00 +00:00
Bob Wilson
d4bfd54ec2
Change ARM VFP VLDM/VSTM instructions to use addressing mode #4 , just like
...
all the other LDM/STM instructions. This fixes asm printer crashes when
compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.
Prior to this change VLDM/VSTM used addressing mode #5 , but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier. Much of the backend
was not aware of these special cases. The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode. I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON. Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 23:18:17 +00:00
Bob Wilson
f955f290c9
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
...
printing "lsl #0 ". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 17:23:19 +00:00
Bob Wilson
eaf1c98a7c
Move the ARM SSAT and USAT optional shift amount operand out of the
...
instruction opcode. This also fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 23:10:46 +00:00
Bob Wilson
9a1c189d9e
Add a separate ARM instruction format for Saturate instructions.
...
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!! Two of them were already out of sync. I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.) Add support for encoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 00:01:18 +00:00
Owen Anderson
90c579de5a
Reapply r110396, with fixes to appease the Linux buildbot gods.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06 18:33:48 +00:00
Owen Anderson
1f74590e9d
Revert r110396 to fix buildbots.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06 00:23:35 +00:00
Owen Anderson
9ccaf53ada
Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
...
ID member as the sole unique type identifier. Clean up APIs related to this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 23:42:04 +00:00
Xerxes Ranby
99ccffe87e
ARMv4 JIT forgets to set the lr register when making a indirect function call. Fixes PR7608
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109125 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 17:28:34 +00:00
Bill Wendling
7431beaba2
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
...
thus is a much more meaningful name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 22:20:36 +00:00
Bob Wilson
21773e716f
Add support for encoding VDUP (ARM core register) instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 20:13:29 +00:00
Bob Wilson
d5a563de07
Add support for encoding NEON VMOV (from core register to scalar) instructions.
...
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 17:34:07 +00:00
Bob Wilson
5cdede43e9
Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is
...
the same as ARM except that the condition code field is always set to ARMCC::AL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107107 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 00:26:13 +00:00
Bob Wilson
62d24a4b92
Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead
...
of the Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107086 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 22:23:17 +00:00
Bob Wilson
08baddbc07
Refactor encoding function for NEON 1-register with modified immediate format.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107070 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 21:16:30 +00:00
Bob Wilson
d896a97dc7
Support Thumb mode encoding of NEON instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 21:12:19 +00:00
Bob Wilson
52e4a0a074
Add support for encoding NEON VMOV (from scalar to core register) instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 04:07:15 +00:00
Bob Wilson
5e7b607f72
Add support for encoding 3-register NEON instructions, and fix
...
emitNEON2RegInstruction's handling of 2-address operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106900 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 22:40:46 +00:00
Bob Wilson
583a2a0615
Add support for encoding 2-register NEON instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106891 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 21:17:19 +00:00
Dan Gohman
fe60104ac9
Use pre-increment instead of post-increment when the result is not used.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106542 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 15:08:57 +00:00
Bob Wilson
1a913ed178
Add instruction encoding for the Neon VMOV immediate instruction. This changes
...
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction. This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed. Testcase for the encoding will follow later when MC has
more support for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11 21:34:50 +00:00
Jim Grosbach
18f30e6f5e
Clean up 80 column violations. No functional change.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 21:53:11 +00:00
Shih-wei Liao
9f3b6a381a
Coding style change (Adding 1 missing space.)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104670 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 04:46:50 +00:00
Shih-wei Liao
45469f38b6
Adding the missing implementation for ARM::SBFX and ARM::UBFX.
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7225 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 03:21:39 +00:00
Shih-wei Liao
6d37a29588
Adding the missing implementation of Bitfield's "clear" and "insert".
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:25:05 +00:00
Shih-wei Liao
5170b71143
To handle s* registers in emitVFPLoadStoreMultipleInstruction().
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:02:28 +00:00
Zonr Chang
f3c770a2cb
Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 10:23:52 +00:00
Zonr Chang
f86399be0c
Add support to MOVimm32 using movt/movw for ARM JIT
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104587 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 08:42:45 +00:00
Dan Gohman
3fb150a902
Fix -Wcast-qual warnings.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 17:42:52 +00:00
Dan Gohman
46510a73e9
Add const qualifiers to CodeGen's use of LLVM IR constructs.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 01:51:59 +00:00
Chris Lattner
75361b69f3
rename llvm::llvm_report_error -> llvm::report_fatal_error
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 22:58:41 +00:00
Bob Wilson
87949d4d5a
Clean up whitespace.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-17 21:16:45 +00:00
Bob Wilson
2d357f6b44
Remove redundant writeback flag in ARM addressing mode 5.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16 18:38:09 +00:00
Bob Wilson
ab3460519e
Remove the writeback flag from ARM's address mode 4. Now that we have separate
...
instructions for ld/st with writeback, the flag is completely redundant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98643 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16 17:46:45 +00:00
Chris Lattner
6ffcccab51
change the DBG_LABEL MachineInstr to always be created
...
with an MCSymbol instead of an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 07:56:48 +00:00
Chris Lattner
7561d48095
change the LabelSDNode to be EHLabelSDNode and make it hold
...
an MCSymbol. Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID. Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98463 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 02:33:54 +00:00
Chris Lattner
1611273351
change EH related stuff (other than EH_LABEL) to use MCSymbol
...
instead of label ID's. This cleans up and regularizes a bunch
of code and makes way for future progress.
Unfortunately, this pointed out to me that JITDwarfEmitter.cpp
is largely copy and paste from DwarfException/MachineModuleInfo
and other places. This is very sad and disturbing. :(
One major change here is that TidyLandingPads moved from being
called in DwarfException::BeginFunction to being called in
DwarfException::EndFunction. There should not be any
functionality change from doing this, but I'm not an EH expert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 01:41:15 +00:00
Bob Wilson
bffb5b39be
Attempt to appease the arm-linux buildbot by fixing the JIT encodings for new
...
base register updating load/store-multiple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 07:34:35 +00:00
Bob Wilson
5265a12f53
Fix ARM buildbot breakage.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98215 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-11 00:46:22 +00:00
Bob Wilson
fbacc888ee
Fix an obvious typo in an assert.
...
Patch by Sean Callanan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98200 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 22:38:45 +00:00
Anton Korobeynikov
ce7bf1c55f
Initial bits of ARMv4-only support.
...
Patch by John Tytgat!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-06 19:39:36 +00:00
Chris Lattner
518bb53485
move target-independent opcodes out of TargetInstrInfo
...
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09 19:54:29 +00:00
Chris Lattner
55fed86353
tidy some targets.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95146 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-02 22:13:21 +00:00
Chris Lattner
33fabd7cc1
detemplatize ARM code emitter.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95138 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-02 21:48:51 +00:00