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121 Commits

Author SHA1 Message Date
Anitha Boyapati
9418f17652 Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162012 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-16 04:04:02 +00:00
Anitha Boyapati
2e7a01cb42 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162010 91177308-0d34-0410-b5e6-96231b3b80d8 2012-08-16 03:50:04 +00:00
Andrew Trick
2661b411cc I'm introducing a new machine model to simultaneously allow simple 
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-07 04:00:00 +00:00
Craig Topper
a15f9d5311 Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157903 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-03 18:58:46 +00:00
Benjamin Kramer
c8e340da82 X86: Rename the CLMUL target feature to PCLMUL. 
It was renamed in gcc/gas a while ago and causes all kinds of
confusion because it was named differently in llvm and clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157745 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-31 14:34:17 +00:00
Craig Topper
e499cdf10c Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify Bulldozer feature list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155897 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-01 06:54:48 +00:00
Craig Topper
e106d2e2ac Make XOP imply AVX as its needed to legalize the registers types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155891 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-01 05:41:41 +00:00
Craig Topper
da1a984159 Make CLMUL and AES imply SSE2 since its needed to legalize the type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155888 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-01 05:28:32 +00:00
Craig Topper
ed39ac5026 Enable AVX and FMA4 for AMD Bulldozer processors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155885 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-01 05:18:13 +00:00
Craig Topper
1203f2f138 Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to corei7-avx, core-avx-i, and core-avx2 cpu names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155618 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-26 06:40:15 +00:00
Jia Liu
31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-18 12:03:15 +00:00
Evan Cheng
de1df103b9 Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150008 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-07 22:50:41 +00:00
Andrew Trick
922d314e8f Instruction scheduling itinerary for Intel Atom. 
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 23:20:51 +00:00
Devang Patel
dd929fc704 Rename X86ATTAsmParser -> X86AsmParser 
We are using one parser to parse att as well as intel style syntax.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148032 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 18:03:40 +00:00
Devang Patel
4ba0e75e4b Add definition for intel asm variant. 
Right now, this just adds additional entries in match table. The parser does not use them yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147859 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 17:51:54 +00:00
Benjamin Kramer
66a7fd78ee Add definitions for AMD's bobcat (aka btver1) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147846 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 11:50:02 +00:00
Devang Patel
0dbcadaa2f Split AsmParser into two components - AsmParser and AsmParserVariant 
AsmParser holds info specific to target parser.
AsmParserVariant holds info specific to asm variants supported by the target.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147787 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 19:13:28 +00:00
Craig Topper
16de4632bb Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. Predicate functions have been altered to maintain previous names and behavior. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147770 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 09:02:13 +00:00
Craig Topper
7ba2725f5d Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147369 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 07:16:00 +00:00
Craig Topper
c38fff4277 Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147349 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 19:46:19 +00:00
Craig Topper
8493e39014 Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147347 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 18:47:31 +00:00
Craig Topper
d4d3513d37 Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 15:51:45 +00:00
Jan Sjödin
ce25d26b40 Add XOP feature flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 15:14:37 +00:00
Benjamin Kramer
5f794df76e X86: Turns out bulldozer also supports sse42 and lzcnt. 
While at it remove the barcelona/instanbul/shanghai subtargets, they're
unsupported by GCC and look pretty broken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145494 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 15:48:16 +00:00
Benjamin Kramer
2a6cf70650 X86: Add subtargets for AMD's bulldozer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145493 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 15:27:46 +00:00
Craig Topper
e7b05504fa Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143319 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 19:57:21 +00:00
David Meyer
928698b14e Remove NaClMode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142338 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 05:29:23 +00:00
Craig Topper
b53fa8bf19 Add X86 BZHI instruction as well as BMI2 feature detection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 07:55:05 +00:00
Craig Topper
909652f687 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 03:21:46 +00:00
Bill Wendling
1203fe7fc8 Revert r141854 because it was causing failures: 
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 07:48:07 +00:00
Craig Topper
8ab1d1e900 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 07:09:14 +00:00
Craig Topper
37f2167f15 Add X86 LZCNT instruction. Including instruction selection support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 06:44:02 +00:00
Benjamin Kramer
717073c237 X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141571 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 19:35:07 +00:00
Benjamin Kramer
a86a58695d X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141563 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:34:56 +00:00
Craig Topper
da394041c4 Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-09 07:31:39 +00:00
Craig Topper
581fe82c84 Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 17:28:23 +00:00
Nick Lewycky
1fac6b50ea Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain 
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-05 21:51:43 +00:00
Eli Friedman
43f51aeca8 Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138660 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 21:21:21 +00:00
Evan Cheng
18fb1d35db Add Mode64Bit feature and sink it down to MC layer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134641 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 21:06:52 +00:00
Benjamin Kramer
eb274e6bdd Rename the "sandybridge" subtarget to "corei7-avx", for GCC compatibility. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131730 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 15:11:26 +00:00
Michael J. Spencer
34868ee4de Add pentium{3,4}m cpus. Patch by Alexander Best! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130749 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 03:42:50 +00:00
Chris Lattner
7a2bdde0a0 Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 05:18:47 +00:00
Michael J. Spencer
4babeeeeed Add 3DNow! intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129551 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 00:32:41 +00:00
Michael J. Spencer
9a0bac41b3 Fix whitespace and tabs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-14 14:33:36 +00:00
Evan Cheng
de7f920835 Disable auto-detection of AVX support since AVX codegen support is not ready. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121677 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 04:23:53 +00:00
Nate Begeman
2ea8ee7c76 Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121439 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 00:26:57 +00:00
Benjamin Kramer
1292c22645 Add patterns for the x86 popcnt instruction. 
- Also adds a new POPCNT subtarget feature that is currently enabled if the target
  supports SSE4.2 (nehalem) or SSE4A (barcelona).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120917 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 20:32:23 +00:00
Jim Grosbach
604cdf6ea7 Clean up comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117785 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 13:48:28 +00:00
Jim Grosbach
ddcf859851 Clean up asm writer usage for x86 and msp430 to flag that the writer should 
use MC instructions in the printInstruction() method via the tablegen flag
for it rather than a #define prior to including the autogenerated bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115238 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 23:40:25 +00:00
Daniel Dunbar
4f98f83459 tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl', 
target specific parsers can adapt the TargetAsmParser to this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110888 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 00:55:32 +00:00