Evan Cheng
0de588fd89
Factor out code that emits load and store instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55854 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05 21:00:03 +00:00
Owen Anderson
9c7216f984
Rename method.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55853 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05 20:49:33 +00:00
Dan Gohman
c39f4dba1c
X86FastISel support for shifts and conditional moves.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55844 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05 18:30:08 +00:00
Evan Cheng
e2471a9169
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55840 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05 17:24:07 +00:00
Dan Gohman
4f22bb0676
Check a comparion's operand type for legality before
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expanding its operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55820 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05 01:33:56 +00:00
Dan Gohman
f52550b50e
Fix X86FastISel code for comparisons and conditional branches
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to check the result of getRegForValue before using it, and
to check for illegal operand types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55819 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05 01:15:35 +00:00
Dan Gohman
d89ae99ec8
X86FastISel support for conditional branches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55816 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05 01:06:14 +00:00
Owen Anderson
95267a1e67
Add initial support for selecting constant materializations that require constant
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pool loads on X86 in fast isel. This isn't actually used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55814 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05 00:06:23 +00:00
Dan Gohman
6e3f05f5ce
X86FastISel support for ICmpInst and FCmpInst.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55811 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04 23:26:51 +00:00
Evan Cheng
4a03775777
For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55807 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04 22:59:58 +00:00
Devang Patel
db10033d7c
If function notes say optimize for size, then adjust alignment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55794 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04 21:03:41 +00:00
Dan Gohman
ae73dc1448
Tidy up several unbeseeming casts from pointer to intptr_t.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55779 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04 17:05:41 +00:00
Owen Anderson
79924eb6f5
Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55777 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04 16:48:33 +00:00
Dan Gohman
6448d91ad1
Clean up uses of TargetLowering::getTargetMachine.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55769 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04 15:39:15 +00:00
Owen Anderson
a3971dfbfe
Add a first attempt at implementing stores for X86 fast isel using target hooks.
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Dan or Evan, please review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55764 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04 07:08:58 +00:00
Evan Cheng
373d50af1d
Load from GV stub should be locally CSE'd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55763 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04 06:18:33 +00:00
Evan Cheng
c2feb5c262
Remove code that pad number of bytes to pop for X86_FastCall CC. The code doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55756 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04 01:04:15 +00:00
Dale Johannesen
7794f2a3a7
Add intrinsics for log, log2, log10, exp, exp2.
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No functional change (and no FE change to generate them).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55753 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04 00:47:13 +00:00
Dan Gohman
3df24e667f
Create HandlePHINodesInSuccessorBlocksFast, a version of
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HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.
This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55746 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 23:12:08 +00:00
Evan Cheng
8b19e56051
Add X86 target hook to implement load (even from GlobalAddress).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55693 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 06:44:39 +00:00
Ted Kremenek
b388eb82fb
Fix capitalization in #include of FastISel.h. This unbreaks the build on case-sensitive filesystems.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55687 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 02:54:11 +00:00
Evan Cheng
88e3041ca6
Unbreak fast isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55685 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 01:04:47 +00:00
Evan Cheng
c3f44b0d63
Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55679 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 00:03:49 +00:00
Dale Johannesen
a619d012c1
Fix some bugs in the code sequences for atomics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55643 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02 20:30:23 +00:00
Evan Cheng
95ce1178e4
Add Mac OS X compatible JIT callback routine.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55625 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02 07:49:03 +00:00
Evan Cheng
7602e11c32
Revamp ARM JIT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55624 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02 06:52:38 +00:00
Evan Cheng
acff339e39
Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55623 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02 06:51:36 +00:00
Evan Cheng
3aac788365
Control flow instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 08:25:56 +00:00
Evan Cheng
3c2ee4939b
ldm / stm instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55599 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 07:48:18 +00:00
Evan Cheng
5d2c1cf74d
AXI2 and AXI3 instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55598 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 07:34:13 +00:00
Evan Cheng
4bbd5f8a9c
Reorganize instruction formats again; AXI1 encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55597 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 07:19:00 +00:00
Evan Cheng
840917be2c
addrmode3 instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55596 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 07:00:14 +00:00
Evan Cheng
0d14fc8cd5
Reorganize some instruction format definitions. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55594 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 01:51:14 +00:00
Evan Cheng
93912739c9
Rest of addrmode2 instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55593 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 01:27:33 +00:00
Evan Cheng
17222df0ec
Addr2 word / byte load encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55591 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 19:02:21 +00:00
Evan Cheng
b7880ac470
Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55590 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 18:32:16 +00:00
Gabor Greif
93c53e5583
fix a bunch of 80-col violations
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55588 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 15:37:04 +00:00
Bill Wendling
9440e35b98
Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR
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instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55582 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 02:59:23 +00:00
Bill Wendling
3156b62855
Expand for ROTR with MVT::i64.
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Dale, Could you please review this?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55581 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 02:53:19 +00:00
Gabor Greif
92362680c1
fix some 80-col violations
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55565 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30 10:09:02 +00:00
Evan Cheng
b18ae3cb63
For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30 08:54:22 +00:00
Evan Cheng
eb9f89287e
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55558 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30 02:03:58 +00:00
Dale Johannesen
ea9eedb787
Add ppc partial-word ATOMIC_CMP_SWAP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55554 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30 00:08:53 +00:00
Evan Cheng
456704476f
Swap fp comparison operands and change predicate to allow load folding (safely this time).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55553 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 23:22:12 +00:00
Evan Cheng
97af60b3ae
Use static_cast instead of C style cast.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55552 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 23:21:31 +00:00
Evan Cheng
94a50da93c
Backing out 55521. Not safe.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55548 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 22:13:21 +00:00
Dale Johannesen
0e55f0678c
Add partial word version of ATOMIC_SWAP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55546 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 18:29:46 +00:00
Owen Anderson
667d8f7607
Add initial support for fast isel of instructions that have inputs pinned to physical registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55545 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 17:45:56 +00:00
Evan Cheng
ba705f62b1
TableGen'ing instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55533 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 07:42:03 +00:00
Evan Cheng
612b79edc9
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55531 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 07:40:52 +00:00