Commit Graph

661 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
b8ac3b035b Revert "Replace a big gob of old coalescer logic with the new CoalescerPair class."
Whiny buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 00:52:22 +00:00
Jakob Stoklund Olesen
e9c59711d3 Replace a big gob of old coalescer logic with the new CoalescerPair class.
CoalescerPair can determine if a copy can be coalesced, and which register gets
merged away. The old logic in SimpleRegisterCoalescing had evolved into
something a bit too convoluted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106701 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 00:12:39 +00:00
Bill Wendling
4b722108e2 We are missing opportunites to use ldm. Take code like this:
void t(int *cp0, int *cp1, int *dp, int fmd) {
  int c0, c1, d0, d1, d2, d3;
  c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  /* ... */
}

It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106693 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 23:00:16 +00:00
Dale Johannesen
9b0d0a42a6 Reinstate correct test, remove the real invalidated test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106664 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 18:56:06 +00:00
Dale Johannesen
2d513dfb6f Remove tests invalidated by previous checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106663 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 18:53:12 +00:00
Bob Wilson
a3a204664d Thumb1 functions using @llvm.returnaddress were not saving the incoming LR.
Radar 8031193.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 22:04:24 +00:00
Evan Cheng
d95ea2da28 Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:21:14 +00:00
Dale Johannesen
b1e51f6910 Add missing FileCheck call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106443 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:46:08 +00:00
Dale Johannesen
b0ccb757b3 Fix PR 7433. Silly typo in non-Darwin ARM tail call
handling, plus correct R9 handling in that mode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:21:49 +00:00
Evan Cheng
0110ac66eb Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:01:32 +00:00
Evan Cheng
86050dc8cc Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:09:54 +00:00
Evan Cheng
6a5e2832d0 Fix an inverted condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106330 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 22:17:13 +00:00
Jakob Stoklund Olesen
52c61ec164 When using ADDri to get the address of a stack object, 255 is a conservative
limit on the offset that can be materialized without using the register
scavenger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106312 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 20:59:25 +00:00
Dale Johannesen
c66cdf74a9 Enable tail calls on ARM by default, with some
basic tests.

This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
  B.W  <label in other function>
which it has not seen before, at least from llvm-based
compilers.  I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106299 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 19:00:18 +00:00
Jakob Stoklund Olesen
0d8ba3303b Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 16:49:33 +00:00
Rafael Espindola
1e81966626 Remove arm_apcscc from the test files. It is the default and doing this
matches what llvm-gcc and clang now produce.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 15:18:27 +00:00
Jakob Stoklund Olesen
8a3eab9b20 Remove the local register allocator.
Please use the fast allocator instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106051 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 21:58:33 +00:00
Rafael Espindola
2bbaf4d06e Set the mtriple in some tests so that they use AAPCS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106041 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 20:42:00 +00:00
Rafael Espindola
2ebb4f81f7 Remove the arm_aapcscc marker from the tests. It is the default
for the linux targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 19:04:29 +00:00
Bob Wilson
852a7e362e Generalize the pre-coalescing of extract_subregs feeding reg_sequences,
replacing the overly conservative checks that I had introduced recently to
deal with correctness issues.  This makes a pretty noticable difference
in our testcases where reg_sequences are used.  I've updated one test to
check that we no longer emit the unnecessary subreg moves.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 05:56:31 +00:00
Bob Wilson
1114f568bc Add a missing bitcast. This code used to only handle conversions between
i64 and f64 types, but now it also handle Neon vector types, so the f64 result
of VMOVDRR may need to be converted to a Neon type.  Radar 8084742.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11 22:45:25 +00:00
Evan Cheng
2b4e727c6f Re-apply 105308 with fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105502 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 23:28:13 +00:00
Dale Johannesen
73c943fb43 More tail call removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 21:14:24 +00:00
Dale Johannesen
4314426fc0 Remove more tail calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105450 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 01:01:24 +00:00
Dale Johannesen
522a181d69 Remove a tail call, and move some CHECKs to the
functions where they belong.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105449 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 01:01:04 +00:00
Bob Wilson
3844173f6e Revert 105308.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 18:28:31 +00:00
Evan Cheng
9d709a8edb Enable machine cse of instructions which define physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105308 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 01:08:27 +00:00
Evan Cheng
046fa3f90a Fix some latency computation bugs: if the use is not a machine opcode do not just return zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105061 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 23:26:21 +00:00
Jakob Stoklund Olesen
700bfada63 Add a -regalloc=default option that chooses a register allocator based on the -O
optimization level.

This only really affects llc for now because both the llvm-gcc and clang front
ends override the default register allocator. I intend to remove that code later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 23:57:25 +00:00
Evan Cheng
84f60b7359 llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 22:08:38 +00:00
Evan Cheng
c7cf10c97e LR is in GPR, not tGPR even in Thumb1 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:00:18 +00:00
Evan Cheng
2457f2c661 Implement @llvm.returnaddress. rdar://8015977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 01:47:14 +00:00
Bob Wilson
be751cfe9c Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:23:12 +00:00
Bob Wilson
78f006acdf Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104380 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 21:05:32 +00:00
Jakob Stoklund Olesen
2afb7505c5 Teach VirtRegRewriter to handle spilling in instructions that have multiple
definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 16:36:13 +00:00
Evan Cheng
f7d87ee158 Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 00:43:17 +00:00
Dan Gohman
f182b23f8f When canonicalizing icmp operand order to put the loop invariant
operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.

Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104262 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 19:26:52 +00:00
Bob Wilson
63b8845e78 Handle Neon v2f64 and v2i64 vector shuffles as register copies.
This fixes the remaining issue with pr7167.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104257 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 18:39:53 +00:00
Dan Gohman
a2086b3483 Teach LSR how to cope better with unrolled loops on targets where
the addressing modes don't make this trivially easy. This allows
it to avoid falling into the less precise heuristics in more
cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104186 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 23:43:12 +00:00
Jakob Stoklund Olesen
3437352887 TwoAddressInstructionPass doesn't really know how to merge live intervals when
lowering REG_SEQUENCE instructions.

Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104146 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:08:00 +00:00
Bob Wilson
29e7e32e08 Testcase to go with 104141.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104142 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 18:58:37 +00:00
Evan Cheng
0a942dbb1e Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 01:08:17 +00:00
Jakob Stoklund Olesen
dcf7708ad9 Remember to update VirtRegLastUse when spilling without killing before a call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 22:20:09 +00:00
Evan Cheng
28dad2a5ca Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:31:17 +00:00
Evan Cheng
27e4840e03 Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 20:03:28 +00:00
Evan Cheng
a083988c8a FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104004 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 00:03:40 +00:00
Evan Cheng
c6dcce3ba5 Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 23:24:12 +00:00
Evan Cheng
44bfdd3d78 Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 22:09:49 +00:00
Evan Cheng
53c779bb3a Careful with reg_sequence coalescing to not to overwrite sub-register indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103971 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 20:57:12 +00:00
Evan Cheng
6206124250 Turn on -neon-reg-sequence by default.
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103960 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 19:51:20 +00:00