Commit Graph

7174 Commits

Author SHA1 Message Date
Evan Cheng
d27c9fc403 Add thumb2 sign / zero extend with rotate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74755 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 01:43:10 +00:00
Evan Cheng
6d94f11196 Added indexed stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74740 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 00:06:39 +00:00
Evan Cheng
4fbb9960ad Sign extending pre/post indexed loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74736 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-02 23:16:11 +00:00
Chris Lattner
0dabb0b177 do not try to analyze bitcasts from i64 to <2 x i32> in ComputedMaskedBits. While
we could do this, doing so requires adjusting the demanded mask and the code isn't 
doing that yet.  This fixes PR4495


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74699 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-02 16:04:08 +00:00
Evan Cheng
e88d5cee9d Thumb2 pre/post indexed loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74696 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-02 07:28:31 +00:00
Chris Lattner
cd714b12fc @GOTPCREL is also rip-relative. Fix fast-isel to do the right thing.
This fixes an llvm-gcc bootstrap problem I introduced.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74691 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-02 04:22:01 +00:00
Chris Lattner
27598ec1e2 Fix yet-another bug I introduced into fastisel, this time handling
constant pool references that weren't getting properly rip-relative.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74689 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-02 03:14:25 +00:00
Daniel Dunbar
0a93771e4c llvm-mc/x86: Test case for x86 operand parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74688 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-02 02:28:23 +00:00
Dan Gohman
6cc18fedf8 Fix an instcombine abort on a scalar-to-vector bitcast. This fixes PR4487.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74646 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 21:38:46 +00:00
Devang Patel
8a15602119 new test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74633 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 19:40:59 +00:00
Devang Patel
923078c65d Support stand alone metadata syntax.
!0 = constant metadata !{i32 21, i32 22}
@llvm.blah = constant metadata !{i32 1000, i16 200, metadata !0}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74630 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 19:21:12 +00:00
Chris Lattner
4fb75e5425 Fix codegen for references to available_externally symbols. This fixes
PR4482.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74613 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 16:53:44 +00:00
Stuart Hastings
75657ab707 Insure that __block_holder_tmp is allocated on the stack when a byref
variable is present.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 15:40:10 +00:00
Evan Cheng
498c2903e2 CommuteChangesDestination() should check if to-be-commuted instruction defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74602 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 08:29:08 +00:00
Evan Cheng
459a7c6b6a Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def.
Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74601 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 08:19:36 +00:00
Chris Lattner
35c28eca62 Fix some fast-isel problems selecting global variable addressing in
pic mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74582 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 03:27:19 +00:00
Evan Cheng
2578ba26e7 Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 01:59:31 +00:00
David Goodwin
d1fa120aee Add PIC load and store patterns for Thumb-2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74577 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 00:01:13 +00:00
Daniel Dunbar
374d8bddac llvm-mc: Symbols in a relocatable expression of the (a - b + cst) form are
allowed to be undefined when the expression is seen, we cannot enforce the
same-section requirement until the entire assembly file has been seen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74565 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 22:49:27 +00:00
David Goodwin
73b8f16b36 Add thumb-2 store word, halfword, and byte.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74555 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 22:11:34 +00:00
David Goodwin
c9a59b5960 Improve Thumb-2 jump table support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74549 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 19:50:22 +00:00
Rafael Espindola
af5f6ba32d Fix PR4485.
Avoid unnecessary duplication of operand 0 of X86::FpSET_ST0_80. This duplication would
cause one register to remain on the stack at the function return.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74534 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 16:40:03 +00:00
Rafael Espindola
f55715c5c7 Fix PR4484.
This was caused by me confounding FP0 and ST(0).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74523 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 12:18:16 +00:00
Evan Cheng
50564ebc9e Temporarily restore the scavenger implicit_def checking code. MachineOperand isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74519 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 09:19:42 +00:00
Evan Cheng
4784f1fc73 Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74518 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 08:49:04 +00:00
Evan Cheng
f3c21b857b A few more load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74500 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 02:15:48 +00:00
Andreas Bolka
e9722fc850 Array accesses are independent if the underlying arrays differ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74499 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 02:12:10 +00:00
Daniel Dunbar
f4b830f03f llvm-mc: Accept relocatable expressions for .org, assignments, .byte, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74498 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 02:10:03 +00:00
David Goodwin
4ff863c257 Enhance tests to include shifted-register operand testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74490 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 01:02:20 +00:00
Daniel Dunbar
d7b267bd90 llvm-mc: Parse symbol attribute directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74487 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 00:33:19 +00:00
Daniel Dunbar
c29dfa786a llvm-mc: Parse .{,b,p2}align{,w,l} directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74478 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 23:46:59 +00:00
David Goodwin
baeb911d60 Add Thumb-2 support for TEQ amd TST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74468 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 22:49:42 +00:00
David Goodwin
8ba221d5c5 Thumb-2 tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74464 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 22:25:22 +00:00
Daniel Dunbar
1ad7edc212 llvm-mc: Recognize C++ style comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74463 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 22:00:57 +00:00
Daniel Dunbar
475839e9a9 MC: Improve expression parsing and implement evaluation of absolute expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74448 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 20:37:27 +00:00
Dan Gohman
cffddcd726 Don't cache PHI exit values from exhaustive evaluations, because
an individual exhaustive evaluation reflects only the exit value
implied by an individual exit, which may differ from the actual
exit value of the loop if there are other exits. This fixes PR4477.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74447 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 20:34:13 +00:00
Rafael Espindola
63de5c3b7e FIX PR 4459.
Not sure I understand how the temp register gets used,
but this fixes a bug and introduces no regressions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74446 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 20:29:59 +00:00
David Greene
cf048d4e59 Add some tests of advanced TableGen list functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74445 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 20:07:17 +00:00
David Goodwin
c0309b48b5 Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74423 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 15:33:01 +00:00
Evan Cheng
055b0310f8 Implement Thumb2 ldr.
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 07:51:04 +00:00
Andreas Bolka
c6a303052b Print pairwise dependence results, add testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74402 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-28 00:35:22 +00:00
Dan Gohman
f7ca1611e2 Don't try to split a loop when the controlling icmp instruction
doesn't have an IV-based operand. This fixes PR4471.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74399 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 22:58:27 +00:00
Dan Gohman
4b35f83b91 Teach LoopSimplify how to merge multiple loop exits into a single exit,
when one of them can be converted to a trivial icmp and conditional
branch.

This addresses what is essentially a phase ordering problem.
SimplifyCFG knows how to do this transformation, but it doesn't do so
if the primary block has any instructions in it other than an icmp and
a branch. In the given testcase, the block contains other instructions,
however they are loop-invariant and can be hoisted. SimplifyCFG doesn't
have LoopInfo though, so it can't hoist them. And, it's important that
the blocks be merged before LoopRotation, as it doesn't support
multiple-exit loops.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74396 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 21:30:38 +00:00
Dan Gohman
de53dc03f5 When a value is used multiple times within a single PHI, instructions
inserted to replace that value must dominate all of of the basic
blocks associated with the uses of the value in the PHI, not just
one of them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74376 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 05:16:57 +00:00
Chris Lattner
74d3f50a80 factor some logic out into a helper function, allow remat of loads from constant
globals.  This implements remat-constant.ll even without aggressive-remat.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74373 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:38:55 +00:00
Chris Lattner
18c5987fa3 Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not.  Instead, those decisions are made by isel lowering
and propagated through to the asm printer.  To achieve this, we:

1. Represent RIP relative addresses by setting the base of the X86 addr
   mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
   X86ISD::WrapperRIP.  When it is unsafe to use RIP, it lowers to
   X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
   a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
   passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
   when to emit (%rip), they just print the symbol.

I think this is a big improvement over the previous situation.  It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier.  This is a short term hack, there is
a much better, but more involved, solution.  2. I had to xfail an 
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction.  This specific test is easy to fix without
-aggressive-remat, which I intend to do next.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
Chris Lattner
600d006cc7 remove some unneeded eh info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74371 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:07:31 +00:00
Chris Lattner
18eed20051 testcase for PR4466
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74367 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 01:33:35 +00:00
David Goodwin
dcdaebc592 When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74355 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 23:13:13 +00:00
Dan Gohman
16bdfdb178 Add some testcases for some of the recent ScalarEvolution bug fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74353 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 22:54:11 +00:00