Nate Begeman
1449f29100
Per chris's request, add some comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 22:19:06 +00:00
Johnny Chen
69631b1327
Trivial formating change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99428 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 21:25:07 +00:00
Nate Begeman
fdea31a463
BUILD_VECTOR was missing out on some prime opportunities to use SSE 4.1 inserts.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99423 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 20:49:50 +00:00
Johnny Chen
2fadd6b221
Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.
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NVCVTFrm will later be used to describe "vcvt with fractional bits".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 19:47:14 +00:00
Johnny Chen
7d85ac09f8
Reverted r99376. The disassembler will deal with the 2-reg format of these two
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N3VX instructions using special case code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99409 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 18:46:34 +00:00
Jim Grosbach
35075a7e81
tweak the arm if conversion heuristic
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99402 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 16:15:14 +00:00
Johnny Chen
b7ba5781e6
Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99376 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 01:29:25 +00:00
Chris Lattner
c54a2f150d
Switch INC8r to defining its pattern in terms of X86inc_flag
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and defining the add pattern with Pat<>, eliminating a use of
parallel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 01:02:12 +00:00
Johnny Chen
c5f413a74c
Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,
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respectively, and add some more comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:57:50 +00:00
Chris Lattner
1aec4d7596
switch SDTBinaryArithWithFlags to be a multiple-result node as well.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99370 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:49:29 +00:00
Chris Lattner
74c8d67af8
Switch SDTUnaryArithWithFlags to being modeled as a two-result
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ISD node. The only change in the generated isel code are comments
like:
< // Src: (X86dec_flag:i16 GR16:i16:$src)
---
> // Src: (X86dec_flag:i16:i32 GR16:i16:$src)
because now it knows that X86dec_flag returns both an i16 (for the result)
and an i32 (for EFLAGS) in this case. Wewt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99369 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:47:47 +00:00
Chris Lattner
7e504141e0
remove 64-bit or_is_add parallels.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:16:52 +00:00
Chris Lattner
a0f7017752
remove useless or_is_add parallel's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99359 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:15:23 +00:00
Chris Lattner
fdac0b66f0
reduce nesting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:12:57 +00:00
Jim Grosbach
fceabef52c
try being more permissive for if-conversion on ARM V7. see what the nightly
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test run permformance numbers say as to whether it helps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:03:13 +00:00
Jakob Stoklund Olesen
fe4b92baf1
Revert "Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings."
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This reverts commit 99345. It was breaking buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99352 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:48:51 +00:00
Chris Lattner
ae8f4c4f86
[llvm_void_ty] is no longer needed for result types,
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just use an empty result list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:46:07 +00:00
Jakob Stoklund Olesen
c75c5fa125
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.
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This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99345 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:14:44 +00:00
Johnny Chen
a271174771
Renamed NVdImmFrm to N1RegModImmFrm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:09:14 +00:00
Johnny Chen
841e828702
Fix typo in the comment for N3VX class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99328 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 21:35:03 +00:00
Johnny Chen
be7849ee73
Add comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99327 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 21:30:12 +00:00
Johnny Chen
3ae9a57c74
Add New NEON Format NVdVmVCVTFrm.
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Converted some of the NEON vcvt instructions to this format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99326 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 21:25:38 +00:00
Johnny Chen
927b88f771
Add New NEON Format NVdVmImmFrm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 20:40:44 +00:00
Evan Cheng
8d1f0dd983
Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically?
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99320 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 20:35:45 +00:00
Bob Wilson
df9a4f0591
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
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These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99309 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 18:54:46 +00:00
Bob Wilson
011355944b
Fix bad indentation, 80-column violations, and trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99295 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 17:23:59 +00:00
Johnny Chen
785516adc5
Add New NEON Format NVdImmFrm.
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Ref: A7.4.6 One register and a modified immediate value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99288 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 16:43:47 +00:00
Bob Wilson
c289a0252b
Rename some instructions to match the corresponding NEON opcode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99266 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 06:26:18 +00:00
Bob Wilson
11d9899759
Change VST1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99265 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 06:20:33 +00:00
Bob Wilson
621f195243
Change VLD1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99261 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 05:25:43 +00:00
Daniel Dunbar
337055e62f
MC: Add TargetAsmBackend::MayNeedRelaxation, for checking whether a particular instruction + fixups might need relaxation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99249 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 03:13:05 +00:00
Daniel Dunbar
8f9b80e5df
MC: Add TargetAsmBackend::WriteNopData and use to eliminate some target dependencies in MCMachOStreamer and MCAssembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99248 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 02:36:58 +00:00
Daniel Dunbar
829680048c
MC: Add TargetAsmBackend::RelaxInstruction callback, and custom X86 implementation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99245 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 01:39:09 +00:00
Bob Wilson
62ef3c8910
Rename one more NEON instruction that I missed earlier.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 20:31:39 +00:00
Bob Wilson
052ba45bf8
Regroup some instructions. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99192 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 18:22:06 +00:00
Bob Wilson
a6979754da
Rename some VLD1/VST1 instructions to match the implementation, i.e., the
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corresponding NEON instructions, instead of operation they are currently
used for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99189 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 18:13:18 +00:00
Bob Wilson
58393bc3fd
Remove some redundant instruction classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99187 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 18:02:38 +00:00
Bob Wilson
39842553e8
Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to
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specify encoding bits in arguments instead of "let" expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99185 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 16:43:10 +00:00
Jakob Stoklund Olesen
e5b8bfa0c5
Completely remove Blackfin patterns that thought JustCC was i1.
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Thanks, Chris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 16:30:04 +00:00
Jeffrey Yasskin
fa72340ba0
Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99182 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 16:13:21 +00:00
Daniel Dunbar
f2de13f8d7
MC/X86: Fix an MCOperand link, when we parsing shrld $1,%eax and friends; I believe this fixes the last memory leaks under test/MC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 22:36:38 +00:00
Daniel Dunbar
5d067fe158
TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 22:36:22 +00:00
Bob Wilson
c88d072293
pr6652: Use LDM to restore PC to the return address on ARMv4.
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Patch by John Tytgat!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99096 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 22:20:40 +00:00
Bob Wilson
226036ee73
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
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with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 22:13:40 +00:00
Bob Wilson
d5fadaf56e
Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with
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address register writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 21:57:36 +00:00
Bob Wilson
4f4f93f9d6
Add variants of VST2, VST3 and VST4 with address register writeback, and
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rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99093 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 21:45:18 +00:00
Bob Wilson
068b18be0d
Add instructions for double-spaced VST3 and VST4 without address register
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writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99090 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 21:15:48 +00:00
Bob Wilson
25eb5013d0
Add VST1 instructions with address register writeback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99083 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 20:54:36 +00:00
Bob Wilson
a1023645f8
Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with
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address register writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 20:47:18 +00:00
Bob Wilson
41315282f9
Tidy some more comments and whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99081 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 20:39:53 +00:00