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138 Commits

Author SHA1 Message Date
Andrew Lenharth
15b7823006 Use this nifty Constraints thing and fix the inverted conditional moves 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36191 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 04:07:59 +00:00
Andrew Lenharth
3553d86731 FTOIT and ITOFT are bit converts, and if we drop 21264s, are always available 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33492 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-24 21:09:16 +00:00
Andrew Lenharth
913ab0574d Be sure to grab weak functions too, and make implicit defs comments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32308 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-07 17:39:14 +00:00
Chris Lattner
1331dec131 silence warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31394 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 01:18:29 +00:00
Andrew Lenharth
d079cdb6d3 fix 2006-11-01-vastart.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31371 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 03:05:26 +00:00
Andrew Lenharth
6bbf6b0b65 more shotenning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31331 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 23:46:56 +00:00
Andrew Lenharth
956a431930 Let us play simplify the td file (and fix a few missed sub and mul patterns). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31322 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 19:52:12 +00:00
Andrew Lenharth
f81173f70e Add all that branch mangling niftiness 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31313 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 16:49:55 +00:00
Evan Cheng
8b2794aeff Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-13 21:14:26 +00:00
Chris Lattner
93b8e490c4 adjcallstack up/down clobbers the sp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30910 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-12 18:00:14 +00:00
Chris Lattner
d615ded96e Use cute tblgen tricks to make zap handling more powerful. Specifically, 
when the dag combiner simplifies an and mask, notice this and allow those bits
to be missing from the zap mask.

This compiles Alpha/zapnot4.ll into:

        sll $16,3,$0
        zapnot $0,3,$0
        ret $31,($26),1

instead of:

        ldah $0,1($31)
        lda $0,-8($0)
        sll $16,3,$1
        and $1,$0,$0
        ret $31,($26),1

It would be *really* nice to replace the hunk of code in the
AlphaISelDAGToDAG.cpp file that matches (and (srl (x, C), c2) into
(SRL (ZAPNOTi)) with a similar pattern, but I've spent enough time poking
at alpha.  Make andrew will do this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30875 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-11 05:13:56 +00:00
Chris Lattner
78feeb0460 Remove dead/redundant instructions. These are handled by ZAPNOTi 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30872 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-11 04:12:39 +00:00
Evan Cheng
466685d41a Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-09 20:57:25 +00:00
Andrew Lenharth
6b634037b3 catch constants more often 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30534 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 15:05:49 +00:00
Andrew Lenharth
ea4f9d5801 Jump tables on Alpha 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30463 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-18 18:01:03 +00:00
Evan Cheng
bb7b844bec CALLSEQ_* produces chain even if that's not needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29603 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-11 09:03:33 +00:00
Evan Cheng
043eb829cc Remove a duplicate pattern/ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29413 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-31 18:42:49 +00:00
Andrew Lenharth
f2b806a1aa Let the alpha breakage begin. First Formals and RET. next Calls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28753 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-12 18:09:24 +00:00
Andrew Lenharth
a5cc38bcbd ignore ordered/unordered for now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28679 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-04 00:25:51 +00:00
Andrew Lenharth
f87e7931fd support x * (c1 + c2) where c1 and c2 are pow2s. special case for c2 == 4 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27370 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-03 04:19:17 +00:00
Andrew Lenharth
afe3f49815 mul by const conversion sequences. more coming soon 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27368 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-03 03:18:59 +00:00
Andrew Lenharth
e5b71d0715 fcopysign for mixed mode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26651 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 17:56:33 +00:00
Andrew Lenharth
283f22275a alpha and llvm have different oppinions on which arg is the sign bit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26647 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 17:41:50 +00:00
Andrew Lenharth
017c556efc Alpha Scheduling classes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26643 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 17:16:45 +00:00
Andrew Lenharth
13beebb25b fcopysign and get rid of dsnode cruft. custom PA runtimes make this better in some senses 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26641 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 14:58:25 +00:00
Andrew Lenharth
133d3100ea isStoreToStackSlot 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25925 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-03 03:07:37 +00:00
Andrew Lenharth
77f0885fa3 Add immediate forms of cmov and remove some cruft 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25882 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-01 19:37:33 +00:00
Chris Lattner
c7e1852d63 cmovle != cmovlt 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25761 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-29 03:47:30 +00:00
Chris Lattner
cedc6f4b30 PHI and INLINEASM are now built-in instructions provided by Target.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-27 01:46:15 +00:00
Andrew Lenharth
9e234856fe minor renaming 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25640 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-26 03:24:15 +00:00
Andrew Lenharth
cd1544eede allow R28 to be used for frame calculations without entirely removing it from circulation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25639 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-26 03:22:07 +00:00
Andrew Lenharth
66e495820a added stores to lsmark 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25552 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-23 21:51:33 +00:00
Andrew Lenharth
87076054e6 fix up more lsmark stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25550 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-23 21:23:26 +00:00
Andrew Lenharth
167bc6ee7a yea, lowering this stuff will basically work 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25549 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-23 20:59:50 +00:00
Andrew Lenharth
394244717a typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25464 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-19 21:10:38 +00:00
Andrew Lenharth
c6a335b72a nasty nasty patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25463 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-19 20:49:37 +00:00
Andrew Lenharth
6e707fb39c fix short immediate loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25371 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-16 21:41:39 +00:00
Andrew Lenharth
3b628f8388 this pattern was bogus 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25197 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-11 03:33:06 +00:00
Andrew Lenharth
29418a862c Int immediate loading fix 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25182 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-10 19:12:47 +00:00
Andrew Lenharth
f7c4bd65c0 proper branch not equal sequence 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25159 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-09 19:49:58 +00:00
Chris Lattner
bfc89d3876 unbreak the build, these are now in TargetSelectionDAG.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25109 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-05 04:48:15 +00:00
Andrew Lenharth
feab2f837c Move brcond over and fix some imm patterns. This may be the last change before changing the default alpha isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25057 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-01 22:16:14 +00:00
Andrew Lenharth
dcbaf8a072 improve constant loading. Still sucks, but oh well 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25047 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-30 02:30:02 +00:00
Andrew Lenharth
a117b187f7 let us get some do what I meant not what I said stuff checked in. You would think the alpha backend would be 64bit clean 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25040 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-29 01:06:12 +00:00
Andrew Lenharth
aa6ed8c7cc Fix up immediate handling 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25039 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-29 00:50:08 +00:00
Andrew Lenharth
713b0b59fc Restore some happiness to the JIT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25026 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-27 06:25:50 +00:00
Andrew Lenharth
424ba780dc Fix alpha regressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25025 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-27 03:53:58 +00:00
Evan Cheng
2b4ea795a2 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-26 09:11:45 +00:00
Andrew Lenharth
eececbab32 add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25011 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-25 17:36:48 +00:00
Andrew Lenharth
53d8970625 All that just to lower div and rem 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25008 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-25 01:34:27 +00:00