6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-18 10:31:57 +00:00
Code Issues Projects Releases Wiki Activity
22,925 Commits 39 Branches 0 Tags 277 MiB
15045b6973
Commit Graph

71 Commits

Author SHA1 Message Date
Evan Cheng
404cb4f9fa Added an offset field to ConstantPoolSDNode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26371 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-25 09:54:52 +00:00
Chris Lattner
daf6bc6347 Pass all the flags to the asm printer, not just the # operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26362 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 19:50:58 +00:00
Chris Lattner
fd6d282a71 rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope. 
Add support for addressing modes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26361 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 19:18:20 +00:00
Chris Lattner
ed18b6896e Refactor operand adding out to a new AddOperand method 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26358 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 18:54:03 +00:00
Chris Lattner
c3a9f8d31c Record all of the expanded registers in the DAG and machine instr, fixing 
several bugs in inline asm expanded operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26332 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 19:21:04 +00:00
Chris Lattner
948d9668a7 Make MachineConstantPool entries alignments explicit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26071 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-09 02:23:13 +00:00
Jeff Cohen
f3afef3b3a Fix VC++ warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25975 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-04 16:20:31 +00:00
Evan Cheng
cccf1232a6 Get rid of some memory leaks identified by Valgrind 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25960 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-04 06:49:00 +00:00
Chris Lattner
dc19b70d24 Add initial support for immediates. This allows us to compile this: 
int %rlwnm(int %A, int %B) {
  %C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
  ret int %C
}

into:

_rlwnm:
        or r2, r3, r3
        or r3, r4, r4
        rlwnm r2, r2, r3, 4, 17    ;; note the immediates :)
        or r3, r2, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25955 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-04 02:26:14 +00:00
Evan Cheng
b8973bd8f5 Allow the specification of explicit alignments for constant pool entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25855 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 22:23:14 +00:00
Chris Lattner
6656dd1a78 Handle physreg input/outputs. We now compile this: 
int %test_cpuid(int %op) {
        %B = alloca int
        %C = alloca int
        %D = alloca int
        %A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
        %Bv = load int* %B
        %Cv = load int* %C
        %Dv = load int* %D
        %x = add int %A, %Bv
        %y = add int %x, %Cv
        %z = add int %y, %Dv
        ret int %z
}

to this:

_test_cpuid:
        sub %ESP, 16
        mov DWORD PTR [%ESP], %EBX
        mov %EAX, DWORD PTR [%ESP + 20]
        cpuid
        mov DWORD PTR [%ESP + 8], %ECX
        mov DWORD PTR [%ESP + 12], %EBX
        mov DWORD PTR [%ESP + 4], %EDX
        mov %ECX, DWORD PTR [%ESP + 12]
        add %EAX, %ECX
        mov %ECX, DWORD PTR [%ESP + 8]
        add %EAX, %ECX
        mov %ECX, DWORD PTR [%ESP + 4]
        add %EAX, %ECX
        mov %EBX, DWORD PTR [%ESP]
        add %ESP, 16
        ret

... note the proper register allocation.  :)

it is unclear to me why the loads aren't folded into the adds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 02:03:41 +00:00
Chris Lattner
acc43bf4ab Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an 
ISD::INLINEASM node.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25668 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-26 23:28:04 +00:00
Evan Cheng
46c01cfe9f No need to keep track of top and bottom nodes in a group since the vector is 
already in order. Thanks Jim for pointing it out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25608 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-25 18:54:24 +00:00
Evan Cheng
e0a5832374 Keep track of bottom / top element of a set of flagged nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25600 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-25 09:13:41 +00:00
Evan Cheng
4ef1086749 Factor out more instruction scheduler code to the base class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25532 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-23 07:01:07 +00:00
Evan Cheng
a9c2091cd3 Do some code refactoring on Jim's scheduler in preparation of the new list 
scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25493 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-21 02:32:06 +00:00
Duraid Madina
f65d917f71 purity++ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25041 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-29 05:59:19 +00:00
Jim Laskey
e81aecbae6 Disengage DEBUG_LOC from non-PPC targets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24919 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-21 20:51:37 +00:00
Jim Laskey
d845582d4a Amend comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24861 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-19 16:32:26 +00:00
Jim Laskey
de48ee28a3 Create a strong dependency for loads following stores. This will leave a 
latency period between the two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24860 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-19 16:30:13 +00:00
Jeff Cohen
18840db533 Keep VC++ happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24835 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 22:20:05 +00:00
Jim Laskey
bd2b621486 Fix a bug Sabre was having where the DAG root was a group. The group dominator 
needed to be added to the ordering list, not the first member of the group.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24816 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 04:40:52 +00:00
Jim Laskey
9022ed955a Groups were not emitted if the dominator node and the node in the ordering list 
were not the same node.  Ultimately the test was bogus.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24815 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 03:59:21 +00:00
Chris Lattner
a5282d8df2 Simplify code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24806 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 01:03:46 +00:00
Nate Begeman
6510b22cec Support multiple ValueTypes per RegisterClass, needed for upcoming vector 
work.  This change has no effect on generated code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-01 04:51:06 +00:00
Evan Cheng
61ca74bc3a Added an index field to GlobalAddressSDNode so it can represent X+12, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24523 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-30 02:04:11 +00:00
Chris Lattner
de202b3cda Switch the allnodes list from a vector of pointers to an ilist of nodes.This eliminates the vector, allows constant time removal of a node froma graph, and makes iteration over the all nodes list stable when adding 
nodes to the graph.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24263 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-09 23:47:37 +00:00
Chris Lattner
4012eb2137 Explicitly initialize some instance vars 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24247 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-08 21:54:57 +00:00
Jim Laskey
26b91ebb63 Let's try ignoring resource utilization on the backward pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24231 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-07 19:08:53 +00:00
Jim Laskey
a5e5bff8b8 Fix logic bug in finding retry slot in tally. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24188 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-05 00:01:25 +00:00
Jim Laskey
54f997d23f Fix a warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24187 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-04 18:26:02 +00:00
Jim Laskey
7d090f3485 Scheduling now uses itinerary data. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24180 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-04 04:05:35 +00:00
Jim Laskey
5a608ddada 1. Embed and not inherit vector for NodeGroup. 
2. Iterate operands and not uses (performance.)

3. Some long pending comment changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24119 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-31 12:49:09 +00:00
Chris Lattner
a4176525cc Reduce the number of copies emitted as machine instructions by 
generating results in vregs that will need them.  In the case of something
like this:  CopyToReg((add X, Y), reg1024), we no longer emit code like
this:

   reg1025 = add X, Y
   reg1024 = reg 1025

Instead, we emit:

   reg1024 = add X, Y

Whoa! :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24111 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-30 18:54:27 +00:00
Jim Laskey
53c523c00e Inhibit instructions from being pushed before function calls. This will 
minimize unnecessary spilling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23710 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-13 16:44:00 +00:00
Jim Laskey
fab66f6900 Finally committing to the new scheduler. Still -sched=none by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23702 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-12 18:29:35 +00:00
Chris Lattner
089c25ccb3 When emiting a CopyFromReg and the source is already a vreg, do not bother 
creating a new vreg and inserting a copy: just use the input vreg directly.

This speeds up the compile (e.g. about 5% on mesa with a debug build of llc)
by not adding a bunch of copies and vregs to be coallesced away.  On mesa,
for example, this reduces the number of intervals from 168601 to 129040
going into the coallescer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23671 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-09 05:58:56 +00:00
Jim Laskey
9d528dc2b4 Reverting to version - until problem isolated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23622 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-04 16:41:51 +00:00
Jim Laskey
8ba732bb1c Refactor gathering node info and emission. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23610 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-03 12:30:32 +00:00
Chris Lattner
dcd5abc70c silence a bogus warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23595 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 16:30:51 +00:00
Chris Lattner
a3638c0f1f Add assertions to the trivial scheduler to check that the value types match 
up between defs and uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23590 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 07:10:55 +00:00
Chris Lattner
14765be0bc Codegen CopyFromReg using the regclass that matches the valuetype of the 
destination vreg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23586 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 06:34:16 +00:00
Chris Lattner
505277a7f5 Add some very paranoid checking for operand/result reg class matchup 
For instructions that define multiple results, use the right regclass
to define the result, not always the rc of result #0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23580 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 07:45:09 +00:00
Jim Laskey
22f6212e9f typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23574 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 00:08:23 +00:00
Jim Laskey
41755e2c7e 1. Simplify the gathering of node groups. 
2. Printing node groups when displaying nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23573 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 00:03:07 +00:00
Jim Laskey
b6d4c2cf2d 1. Made things node-centric (from operand). 
2. Added node groups to handle flagged nodes.

3. Started weaning simple scheduling off existing emitter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23566 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 19:15:27 +00:00
Jeff Cohen
fef80f43e0 Silence VC++ redeclaration warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23516 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 01:59:49 +00:00
Jim Laskey
5324fec644 Remove some redundancies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23469 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-27 17:32:45 +00:00
Jim Laskey
e6b90fba4a Addition of a simple two pass scheduler. This version is currently hacked up 
for testing and will require target machine info to do a proper scheduling.
The simple scheduler can be turned on using -sched=simple (defaults
to -sched=none)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23455 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-26 21:57:04 +00:00
Chris Lattner
a639a43602 Fix the release build, noticed by Eric van Riet Paap 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23215 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-02 07:09:28 +00:00