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2887 Commits

Author SHA1 Message Date
Ana Pazos
6345249972 Implemented Neon scalar vdup_lane intrinsics. 
Fixed scalar dup alias and added test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195330 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-21 08:16:15 +00:00
Jack Carter
0233715d74 reverts 195057 per request 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195152 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 20:53:28 +00:00
Rafael Espindola
72935dd909 Support multiple COFF sections with the same name but different COMDAT. 
This is the first step to fix pr17918.

It extends the .section directive a bit, inspired by what the ELF one looks
like. The problem with using linkonce is that given

.section foo
.linkonce....

.section foo
.linkonce

we would already have switched sections when getting to .linkonce. The cleanest
solution seems to be to add the comdat information in the .section itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195148 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 19:52:52 +00:00
Hao Liu
36c7806f4e Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 02:17:05 +00:00
Kevin Qin
282a979ddd implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 01:40:25 +00:00
Jiangning Liu
01dd5728cc Add predicate for AArch64 crypto instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 01:38:31 +00:00
Jack Carter
e53969b475 [Mips] Support for MicroMips STO refactoring. 
No true functional changes.

Change the "hack" name of emitMipsHackSTOCG to emitSymSTO.

Remove demonstration code in AsmParser for emitMipsHackSTOCG and
emitMipsHackELFFlags. The STO field is in an ELF symbol and is not
an explicit directive. That said, we are missing the compliment call
in AsmParser and that will need to be addressed soon.

XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags.
These will built out with following patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195067 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 01:25:18 +00:00
Reid Kleckner
a7b7a7d629 Revert "COFF: Emit all MCSymbols rather than filtering out some of them" 
This reverts commit r190888, to fix PR17967.  The original change wasn't
the right way to get @feat.00 into the object file.  The right fix is to
make @feat.00 be a global symbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195053 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-18 23:08:12 +00:00
Matheus Almeida
26651c7a66 [mips][msa] Update encoding of bnz.v (typo). 
Note that there's no hardware yet that relies on that encoding.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195006 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-18 13:09:54 +00:00
Matheus Almeida
95adf91f29 [mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded. 
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-18 12:32:49 +00:00
Kevin Qin
69b2447b6a [AArch64 NEON]Add mov alias for simd copy instructions. 
Set some unspecified bits of INS/DUP to zero as ARMARM requested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194996 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-18 09:20:32 +00:00
Zoran Jovanovic
42cb3abadd Use instr mapping for microMIPS in llvm-mc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194792 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-15 08:07:34 +00:00
Kevin Qin
27df434c5e Add test case for AArch64 NEON instruction set misc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194673 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-14 06:45:17 +00:00
Kevin Qin
a08063a000 Implement aarch64 neon instruction class SIMD misc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-14 02:44:13 +00:00
Jiangning Liu
082ac99cc8 Implement AArch64 NEON instruction set AdvSIMD (table). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-14 01:57:32 +00:00
Richard Sandiford
541c5de2fb [SystemZ] Add the general form of BCR 
At the moment this is just the MC support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194585 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-13 16:57:53 +00:00
Vladimir Medic
c0fad4d9fd Fix bug in .gpword directive parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194570 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-13 13:18:04 +00:00
Zoran Jovanovic
1206f1968b Support for microMIPS trap instruction with immediate operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194569 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-13 13:15:03 +00:00
Vladimir Medic
c7ebe50276 This patch fixes a bug in floating point operands parsing, when instruction alias uses default register operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194562 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-13 09:48:53 +00:00
Tim Northover
59e648e3c8 ARM: diagnose invalid system LDM/STM 
The system LDM and STM instructions can't usually writeback to the base
register. The one exception is when an LDM is actually an exception-return
(i.e. contains PC in the register list).

(There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there
is no positive test).

rdar://problem/15223374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194512 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-12 21:32:41 +00:00
Chad Rosier
13c83a2a09 [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar 
copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-12 19:13:08 +00:00
Artyom Skrobov
ef572e31e2 [ARM] Add support for MVFR2 which is new in ARMv8 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-11 19:56:13 +00:00
Chad Rosier
30b2a19f3b [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-11 18:04:07 +00:00
Jim Grosbach
dc7eb3e023 X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable() 
On darwin, when trying to create compact unwind info, a .cfi_cfa_def
directive would case an llvm_unreachable() to be hit. Back off when we
see this directive and generate the regular DWARF style eh_frame.

rdar://15406518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194285 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-08 22:33:06 +00:00
Artyom Skrobov
2b01682aa7 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194263 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-08 16:25:50 +00:00
Artyom Skrobov
c5c991bf31 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194262 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-08 16:17:14 +00:00
Artyom Skrobov
fa840ba402 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-08 16:16:30 +00:00
Zoran Jovanovic
c9af1add85 Test for microMIPS trap instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194258 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-08 14:55:31 +00:00
Matheus Almeida
de712386cd [mips][msa] Update encoding of LDI instruction. 
The encoding was updated in MSA r1.07.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194255 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-08 10:43:11 +00:00
Artyom Skrobov
1b91231347 [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-08 09:16:31 +00:00
Zoran Jovanovic
9f471750fa Support for microMIPS trap instructions 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-07 14:35:24 +00:00
Vladimir Medic
2263a2ca72 Implement gpword directive for mips, test case added. Stype changes using clang-format are also included. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194145 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-06 11:27:05 +00:00
Jiangning Liu
8458f371b8 Implement AArch64 Neon instruction set Perm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-06 03:35:27 +00:00
Jiangning Liu
258115258f Implement AArch64 Neon instruction set Bitwise Extract. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-06 02:25:49 +00:00
Tim Northover
f635ab8eab ARM: permit bare dmb/dsb/isb aliases on Cortex-M0 
Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194094 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-05 21:36:02 +00:00
Jiangning Liu
3ff3a8aa75 Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-05 17:42:05 +00:00
Hao Liu
591c2f738a Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post). 
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-05 03:39:32 +00:00
Zoran Jovanovic
5c042162be Support for microMIPS branch instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-04 14:53:22 +00:00
Chad Rosier
1a035dd6df [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193816 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 22:36:59 +00:00
Chad Rosier
f7ba489730 [AArch64] Add diagnostic tests for NEON scalar shift immediate instructions (see: r193790). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193798 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 20:11:32 +00:00
Chad Rosier
1d28917dc3 [AArch64] Add support for NEON scalar shift immediate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193790 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 19:28:44 +00:00
Amara Emerson
c2884320fe [AArch64] Make the use of FP instructions optional, but enabled by default. 
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 09:32:11 +00:00
Tom Roeder
4ca9a2a0ad This commit adds some (but not all) of the x86-64 relocations that are not 
currently supported in the ELF object writer, along with a simple test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193709 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-30 18:47:25 +00:00
Artyom Skrobov
3f04b50686 [ARM] NEON instructions were erroneously decoded from certain invalid encodings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193705 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-30 18:10:09 +00:00
Chad Rosier
f853a034a1 [AArch64] Add support for NEON scalar floating-point compare instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193691 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-30 15:19:37 +00:00
Zoran Jovanovic
1aaf43c2a2 Support for microMIPS jump instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193623 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-29 16:38:59 +00:00
Bernard Ogden
c777b2e58c Test cleanup for v8 instructions 
Add some missing tests, factor out a test not specific to v8 into
its own file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193611 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-29 14:16:09 +00:00
Bernard Ogden
47c6d17b1c ARM: Add subtarget feature for CRC 
Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend.

Differential Revision: http://llvm-reviews.chandlerc.com/D2036

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193599 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-29 09:47:35 +00:00
Joerg Sonnenberger
72580780a9 Move the STT_FILE symbols out of the normal symbol table processing for 
ELF. They can overlap with the other symbols, e.g. if a source file
"foo.c" contains a function "foo" with a static variable "c".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193569 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-29 01:06:17 +00:00
Rafael Espindola
136660484d Convert another llc -filetype=obj test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193548 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-28 22:17:19 +00:00