Commit Graph

2902 Commits

Author SHA1 Message Date
Rafael Espindola
dfb31b6cac Output .eh_frames on COFF too now that the integrated as is used on mingw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196104 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02 14:59:34 +00:00
Zoran Jovanovic
082ac1ffdb Test case for issue with microMIPS long branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195976 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-30 19:13:15 +00:00
Zoran Jovanovic
eb47ca4561 Revert revision 195965.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195967 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-29 22:10:02 +00:00
Zoran Jovanovic
ee7f913c98 Fixed issue with microMIPS long branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195965 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-29 21:41:24 +00:00
Kevin Qin
9224192321 [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195936 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-29 01:29:16 +00:00
Hao Liu
cdd732cdd3 AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195903 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-28 01:07:45 +00:00
Rafael Espindola
0de6255877 Use the same tls section name as msvc.
We currently error in clang with:
"error: thread-local storage is unsupported for the current target", but we
can start to get the llvm level ready.

When compiling

template<typename T>
struct foo {
  static __declspec(thread) int bar;
};
template<typename T>
__declspec(therad) int foo<T>::bar;
template struct foo<int>;

msvc produces

SECTION HEADER #3
   .tls$ name
       0 physical address
       0 virtual address
       4 size of raw data
     12F file pointer to raw data (0000012F to 00000132)
       0 file pointer to relocation table
       0 file pointer to line numbers
       0 number of relocations
       0 number of line numbers
C0301040 flags
         Initialized Data
         COMDAT; sym= "public: static int foo<int>::bar" (?bar@?$foo@H@@2HA)
         4 byte align
         Read Write

gcc produces a ".data$__emutls_v.<symbol>" for the testcase with
__declspec(thread) replaced with thread_local.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195849 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 15:52:11 +00:00
Chad Rosier
9fef0370c5 [AArch64] Add support for NEON scalar floating-point absolute difference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195803 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 01:45:58 +00:00
Rafael Espindola
823c9c725d Use simple section names for COMDAT sections on COFF.
With this patch we use simple names for COMDAT sections (like .text or .bss).
This matches the MSVC behavior.

When merging it is the COMDAT symbol that is used to decide if two sections
should be merged, so there is no point in building a fancy name.

This survived a bootstrap on mingw32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 01:18:37 +00:00
Chad Rosier
48f115aabf [AArch64] Add support for NEON scalar floating-point to integer convert
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195788 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-26 22:17:37 +00:00
Rafael Espindola
854e601471 Use -triple to fix the test on non-ELF hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195682 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-25 20:46:18 +00:00
Rafael Espindola
8f6631cdb6 Don't use nopl in cpus that don't support it.
Patch by Mikulas Patocka. I added the test. I checked that for cpu names that
gas knows about, it also doesn't generate nopl.

The modified cpus:
i686 - there are i686-class CPUs that don't have nopl: Via c3, Transmeta
        Crusoe, Microsoft VirtualBox - see
        https://bbs.archlinux.org/viewtopic.php?pid=775414
k6, k6-2, k6-3, winchip-c6, winchip2 - these are 586-class CPUs
via c3 c3-2 - see https://bugs.archlinux.org/task/19733 as a proof that
        Via c3 and c3-Nehemiah don't have nopl

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195679 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-25 20:15:14 +00:00
David Peixotto
1edc33b924 ARM integrated assembler generates incorrect nop opcode
This patch fixes a bug in the assembler that was causing bad code to
be emitted.  When switching modes in an assembly file (e.g. arm to
thumb mode) we would always emit the opcode from the original mode.

Consider this small example:

$ cat align.s
.code 16
foo:
  add r0, r0
.align 3
  add r0, r0

$ llvm-mc -triple armv7-none-linux align.s -filetype=obj -o t.o
$ llvm-objdump -triple thumbv7 -d t.o
Disassembly of section .text:
foo:
       0:       00 44         add     r0, r0
       2:       00 f0 20 e3   blx #4195904
       6:       00 00         movs    r0, r0
       8:       00 44         add     r0, r0

This shows that we have actually emitted an arm nop (e320f000)
instead of a thumb nop. Unfortunately, this encodes to a thumb
branch which causes bad things to happen when compiling assembly
code with align directives.

The fix is to notify the ARMAsmBackend when we switch mode. The
MCMachOStreamer was already doing this correctly. This patch makes
the same change for the MCElfStreamer.

There is still a bug in the way nops are emitted for alignment
because the MCAlignment fragment does not store the correct mode.
The ARMAsmBackend will emit nops for the last mode it knew about. In
the example above, we still generate an arm nop if we add a `.code
32` to the end of the file.

PR18019


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195677 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-25 19:11:13 +00:00
Rafael Espindola
c7daeb3098 Fix .comm and .lcomm on COFF.
These should not use COMDATs. GNU as uses .bss for .lcomm and section 0 for
.comm.

Given

static int a;
int b;

MSVC puts both in .bss. This patch then puts both .comm and .lcomm on .bss. With
this change we agree with gas on .lcomm, are much closer on .comm and clang-cl
matches msvc on the above example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195654 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-25 16:06:04 +00:00
Hao Liu
e04ed6b8b1 Fixed a bug about disassembling AArch64 post-index load/store single element instructions.
ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
    echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195591 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-25 01:53:26 +00:00
Ana Pazos
6345249972 Implemented Neon scalar vdup_lane intrinsics.
Fixed scalar dup alias and added test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 08:16:15 +00:00
Jack Carter
0233715d74 reverts 195057 per request
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 20:53:28 +00:00
Rafael Espindola
72935dd909 Support multiple COFF sections with the same name but different COMDAT.
This is the first step to fix pr17918.

It extends the .section directive a bit, inspired by what the ELF one looks
like. The problem with using linkonce is that given

.section foo
.linkonce....

.section foo
.linkonce

we would already have switched sections when getting to .linkonce. The cleanest
solution seems to be to add the comdat information in the .section itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195148 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 19:52:52 +00:00
Hao Liu
36c7806f4e Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 02:17:05 +00:00
Kevin Qin
282a979ddd implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:40:25 +00:00
Jiangning Liu
01dd5728cc Add predicate for AArch64 crypto instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:38:31 +00:00
Jack Carter
e53969b475 [Mips] Support for MicroMips STO refactoring.
No true functional changes.

Change the "hack" name of emitMipsHackSTOCG to emitSymSTO.

Remove demonstration code in AsmParser for emitMipsHackSTOCG and
emitMipsHackELFFlags. The STO field is in an ELF symbol and is not
an explicit directive. That said, we are missing the compliment call
in AsmParser and that will need to be addressed soon.

XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags.
These will built out with following patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:25:18 +00:00
Reid Kleckner
a7b7a7d629 Revert "COFF: Emit all MCSymbols rather than filtering out some of them"
This reverts commit r190888, to fix PR17967.  The original change wasn't
the right way to get @feat.00 into the object file.  The right fix is to
make @feat.00 be a global symbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 23:08:12 +00:00
Matheus Almeida
26651c7a66 [mips][msa] Update encoding of bnz.v (typo).
Note that there's no hardware yet that relies on that encoding.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 13:09:54 +00:00
Matheus Almeida
95adf91f29 [mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded.
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 12:32:49 +00:00
Kevin Qin
69b2447b6a [AArch64 NEON]Add mov alias for simd copy instructions.
Set some unspecified bits of INS/DUP to zero as ARMARM requested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194996 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 09:20:32 +00:00
Zoran Jovanovic
42cb3abadd Use instr mapping for microMIPS in llvm-mc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194792 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 08:07:34 +00:00
Kevin Qin
27df434c5e Add test case for AArch64 NEON instruction set misc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194673 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 06:45:17 +00:00
Kevin Qin
a08063a000 Implement aarch64 neon instruction class SIMD misc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 02:44:13 +00:00
Jiangning Liu
082ac99cc8 Implement AArch64 NEON instruction set AdvSIMD (table).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 01:57:32 +00:00
Richard Sandiford
541c5de2fb [SystemZ] Add the general form of BCR
At the moment this is just the MC support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194585 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 16:57:53 +00:00
Vladimir Medic
c0fad4d9fd Fix bug in .gpword directive parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194570 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 13:18:04 +00:00
Zoran Jovanovic
1206f1968b Support for microMIPS trap instruction with immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 13:15:03 +00:00
Vladimir Medic
c7ebe50276 This patch fixes a bug in floating point operands parsing, when instruction alias uses default register operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194562 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 09:48:53 +00:00
Tim Northover
59e648e3c8 ARM: diagnose invalid system LDM/STM
The system LDM and STM instructions can't usually writeback to the base
register. The one exception is when an LDM is actually an exception-return
(i.e. contains PC in the register list).

(There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there
is no positive test).

rdar://problem/15223374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194512 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 21:32:41 +00:00
Chad Rosier
13c83a2a09 [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar
copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 19:13:08 +00:00
Artyom Skrobov
ef572e31e2 [ARM] Add support for MVFR2 which is new in ARMv8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 19:56:13 +00:00
Chad Rosier
30b2a19f3b [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 18:04:07 +00:00
Jim Grosbach
dc7eb3e023 X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable()
On darwin, when trying to create compact unwind info, a .cfi_cfa_def
directive would case an llvm_unreachable() to be hit. Back off when we
see this directive and generate the regular DWARF style eh_frame.

rdar://15406518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194285 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 22:33:06 +00:00
Artyom Skrobov
2b01682aa7 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 16:25:50 +00:00
Artyom Skrobov
c5c991bf31 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194262 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 16:17:14 +00:00
Artyom Skrobov
fa840ba402 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 16:16:30 +00:00
Zoran Jovanovic
c9af1add85 Test for microMIPS trap instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 14:55:31 +00:00
Matheus Almeida
de712386cd [mips][msa] Update encoding of LDI instruction.
The encoding was updated in MSA r1.07.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194255 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 10:43:11 +00:00
Artyom Skrobov
1b91231347 [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 09:16:31 +00:00
Zoran Jovanovic
9f471750fa Support for microMIPS trap instructions 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-07 14:35:24 +00:00
Vladimir Medic
2263a2ca72 Implement gpword directive for mips, test case added. Stype changes using clang-format are also included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 11:27:05 +00:00
Jiangning Liu
8458f371b8 Implement AArch64 Neon instruction set Perm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 03:35:27 +00:00
Jiangning Liu
258115258f Implement AArch64 Neon instruction set Bitwise Extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 02:25:49 +00:00
Tim Northover
f635ab8eab ARM: permit bare dmb/dsb/isb aliases on Cortex-M0
Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 21:36:02 +00:00