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7953 Commits

Author SHA1 Message Date
Craig Topper
8f35c13842 Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148537 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 09:29:03 +00:00
Craig Topper
0e2037ba2b Add support for selecting 256-bit PALIGNR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148532 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 05:53:00 +00:00
Eli Friedman
9a2478ac1a Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148513 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 00:05:46 +00:00
Devang Patel
a951f77ca3 Post process 'and', 'sub' instructions and select better encoding, if available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148489 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 18:40:55 +00:00
Devang Patel
e60540f380 Intel syntax: There is no need to create unary expr for simple negative displacement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148486 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 18:15:51 +00:00
Devang Patel
ac0f048602 Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 17:53:25 +00:00
Craig Topper
40385c8104 Folding table additions and fixes for AVX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148467 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 08:50:38 +00:00
Craig Topper
1a7700a3fa Merge 128-bit and 256-bit SHUFPS/SHUFPD handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148466 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 08:19:12 +00:00
Nick Lewycky
22de16dc75 Add a TargetOption for disabling tail calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148442 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 00:34:10 +00:00
Jakob Stoklund Olesen
c38c4561cd Add experimental -x86-use-regmask command line option. 
It adds register mask operands to x86 call instructions.  Once all the
backend passes support register mask operands, this will be permanently
enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148438 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 23:52:22 +00:00
Jakob Stoklund Olesen
71f0fc1ca8 Ignore register mask operands when lowering instructions to MC. 
This is similar to implicit register operands.  MC doesn't understand
register liveness and call clobbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148437 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 23:52:19 +00:00
Devang Patel
b8ba13f009 Process instructions after match to select alternative encoding which may be more desirable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 22:42:29 +00:00
Jim Grosbach
ec3433852d Tidy up. MCAsmBackend naming conventions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148400 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 18:52:16 +00:00
Jakob Stoklund Olesen
31867660cb Add a CoveredBySubRegs property to Register descriptions. 
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 00:16:39 +00:00
Jakob Stoklund Olesen
0bd2ae92b0 Move X86 callee saved register lists to the X86CallConv .td file. 
Add a trivial implementation of the getCallPreservedMask() hook.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148347 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 22:47:01 +00:00
Devang Patel
2f8af1d643 Intel syntax: Fix parser match class to check memory operand size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148338 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 21:48:03 +00:00
Devang Patel
6220fea2a8 Intel syntax: Parse "BYTE PTR [RDX + RCX]" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148334 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 21:25:10 +00:00
Devang Patel
bc51e501a0 Untabify. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148322 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 19:09:22 +00:00
Devang Patel
9a3d293cf3 Intel syntax: Do not unncessarily create plus expression for memory operand displacement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148321 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 19:08:07 +00:00
Devang Patel
d37ad247cc Intel syntax: Robustify memory operand parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148312 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 18:00:18 +00:00
Nadav Rotem
a16d441430 Fix warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148301 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 09:31:09 +00:00
Nadav Rotem
0b94b5f52b Fix 11769. 
In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner.
However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which
currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148298 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 09:13:19 +00:00
Craig Topper
8b5a6b63dd Remove unnecessary AVX check from an assert. hasSSE2 is enough. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148295 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 08:23:44 +00:00
Craig Topper
37c2677fbc Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. Probably could use better handling in DAG combine or getNode. Fixes PR11772. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148285 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 04:44:50 +00:00
Eli Friedman
1857b51ef5 Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148240 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-16 16:42:21 +00:00
Eli Friedman
a20b71518a Get rid of unused codegen-only instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148239 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-16 16:29:35 +00:00
Craig Topper
b7ab7fe053 Give priority to AVX over SSE for 128-bit floating point unpck instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148233 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-16 09:56:42 +00:00
Nadav Rotem
cc6165695f [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits. 
We know that the blend instructions only use the MSB, so if the mask is
sign-extended then we can convert it into a SHL instruction. This is a
common pattern because the type-legalizer sign-extends the i1 type which
is used by the LLVM-IR for the condition.

Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148225 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-15 19:27:55 +00:00
Benjamin Kramer
ed4c8c633c Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through CodeGen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148218 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-15 13:16:05 +00:00
Craig Topper
d07ef50ca1 Fix the memop type on a couple 256-bit AVX instructions that were using f128mem instead of f256mem. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148196 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 18:29:57 +00:00
Craig Topper
446626d236 Add a bunch of AVX instructions to the folding tables. Also fixed the alignment on 256-bit AVX2 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148194 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 18:14:53 +00:00
Chad Rosier
d32d3b758f Fix pasto from r146196. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148167 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 01:50:21 +00:00
Devang Patel
85d5aaecd0 Revert r148131, it was committed before it was ready. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148134 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 19:28:58 +00:00
Devang Patel
c798cc4283 Refactor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148131 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 19:12:18 +00:00
Craig Topper
0518970dc8 Convert SHUFPD with the same register for both sources to PSHUFD if it would prevent a register copy. Similar to SHUFPS, but requires the mask to be converted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148112 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 09:21:41 +00:00
Craig Topper
562659ff6b use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 vs SSE1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148109 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 08:32:21 +00:00
Craig Topper
12216172c0 Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148108 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 08:12:35 +00:00
Craig Topper
c30432ab57 Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match v4i64 and v8i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148106 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 06:59:47 +00:00
Craig Topper
b9c7f652d7 Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes PR11750. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148101 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 06:12:41 +00:00
Craig Topper
e6cf4a070d Fix typo in PerformAddCombine that caused any vector type to be checked for horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148096 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 05:04:25 +00:00
Bill Wendling
b4ee5168ab Fix off-by-one error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148077 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 00:41:53 +00:00
Bill Wendling
86b1a7d614 Fix the code that was WRONG. 
The registers are placed into the saved registers list in the reverse order,
which is why the original loop was written to loop backwards.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148064 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 23:05:03 +00:00
Elena Demikhovsky
16db710898 Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure 
lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&&  "Op 1 of shuffle should not be undef"' failed.
Added a test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148044 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 20:33:10 +00:00
Rafael Espindola
85b9d43d4c Support segmented stacks on 64-bit FreeBSD. 
This patch uses tcb_spare field in the tcb structure to store info.
Patch by Jyun-Yan You.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148041 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 20:24:30 +00:00
Rafael Espindola
e4d18de5d1 Support segmented stacks on win32. 
Uses the pvArbitrary slot of the TIB, which is reserved for applications. We
only support frames with a static size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148040 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 20:22:08 +00:00
Devang Patel
dd929fc704 Rename X86ATTAsmParser -> X86AsmParser 
We are using one parser to parse att as well as intel style syntax.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148032 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 18:03:40 +00:00
Benjamin Kramer
e2eb92578a After Jakob's r147938 exception handling on i386 was completely broken. 
Restore the (obviously wrong) behavior from before r147938 without relying on
undefined behavior. Add a fat FIXME note.

This should fix nightly tester failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148030 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 17:37:18 +00:00
Nadav Rotem
d2070b00ef Fix a bug in the AVX 256-bit shuffle code in cases where the splat element is on the boundary of two 128-bit vectors. 
The attached testcase was stuck in an endless loop.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148027 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 15:31:55 +00:00
Benjamin Kramer
fb418bab97 X86: Generalize the x << (y & const) optimization to also catch masks with more set bits set than 31 or 63. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148024 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 12:41:34 +00:00
Devang Patel
c59d9df248 Add predicate method check match memory operand size, if available. 
In att style asm syntax memory operand size is derived from suffix attached with mnemonic.  In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148006 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 01:51:42 +00:00