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17989 Commits

Author SHA1 Message Date
Reid Spencer
727992c30a Implement isMinValuePlusOne using facilities of APInt instead of uint64_t 
Patch by Zhou Sheng.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35187 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 21:08:07 +00:00
Reid Spencer
44e33e674a Implement isOneBitSet in terms of APInt::countPopulation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35186 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 21:04:43 +00:00
Reid Spencer
5a1e3e1a7d 1. Use APInt::getSignBit to reduce clutter (patch by Sheng Zhou) 
2. Replace uses of the "isPositive" utility function with APInt::isPositive


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35185 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 20:58:18 +00:00
Reid Spencer
8439bc8d69 Remove a redundant clause in an if statement. 
Patch by Sheng Zhou.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35184 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 20:47:50 +00:00
Reid Spencer
49d273e168 Regenerate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35183 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 20:40:51 +00:00
Reid Spencer
eac65746d7 Fix test/Assembler/2007-03-19-NegValue.ll by using the new "isSigned" 
parameter on ConstantInt::get to indicate the signedness of the intended
value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35182 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 20:40:22 +00:00
Reid Spencer
7fc44c8c5f Allow ConstantInt::get(Ty, uint64_t) to interpret the 64-bit values as a 
negative number. This is needed to fix test/Assembler/2007-03-19-NegValue.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35181 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 20:39:08 +00:00
Reid Spencer
3a34137548 Implement extension of sign bits for negative values in the uint64_t 
constructor. This helps to fix test/Assembler/2007-03-19-NegValue.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35180 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 20:37:47 +00:00
Anton Korobeynikov
d437db1b7b Fix mingw32 build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35177 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 20:19:08 +00:00
Reid Spencer
93c40036c8 Regenerate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35174 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 18:40:50 +00:00
Reid Spencer
186a43f1ad For PR1248: 
Eliminate support for type planes in numbered values. This simplifies the
data structures involved in managing forward definitions, etc. Instead of
requiring maps from type to value, we can now just use a vector of values.
These changes also required rewrites of some support functions such as
InsertValue, getBBVal, and ResolveDefinitions. Some other cosmetic changes
were made as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35173 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 18:39:36 +00:00
Reid Spencer
4e0422c7e6 Add and Operator== method to ValID so equality can be done properly for 
named or numbered ValIDs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35172 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 18:34:28 +00:00
Reid Spencer
590b3c559f For PR1258: 
Radically simplify the SlotMachine. There is no need to keep Value planes
around any more. This change causes slot numbering to number all un-named,
non-void values starting at 0 and incrementing monotonically through the
function, regardless of type (including BasicBlocks). Getting slot numbers
is now a single lookup operation instead of a double lookup.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35171 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 18:32:53 +00:00
Chris Lattner
a9d1a843fc fix ScalarRepl/2007-03-19-CanonicalizeMemcpy.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35169 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 18:25:57 +00:00
Evan Cheng
757072d954 Remove -reduce-joining-phys-regs options. Make it on by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35165 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 18:08:26 +00:00
Evan Cheng
9f6636ff0c Fix naming inconsistencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35163 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 07:48:02 +00:00
Evan Cheng
fa775d09c6 Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35162 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 07:20:03 +00:00
Evan Cheng
a251570417 Constant generation instructions are re-materializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35161 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 07:09:02 +00:00
Evan Cheng
e2e9e44d8f Added isReMaterializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35160 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 06:22:07 +00:00
Evan Cheng
79b098445b Minor bug fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35153 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 04:22:35 +00:00
Chris Lattner
d435dbcbf9 fix a warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35152 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 00:39:32 +00:00
Chris Lattner
8bf9911932 implement the next chunk of SROA with memset/memcpy's of aggregates. This 
implements Transforms/ScalarRepl/memset-aggregate-byte-leader.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35150 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 00:16:43 +00:00
Nick Lewycky
3f64b1ab1d Clean up this code and fix subtract miscompile. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35146 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-18 22:58:46 +00:00
Chris Lattner
318bf7963a Implement InstCombine/and-xor-merge.ll:test[12]. 
Rearrange some code to simplify it now that shifts are binops


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35145 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-18 22:51:34 +00:00
Chris Lattner
11a3a9d27d minor updates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35143 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-18 22:41:33 +00:00
Nick Lewycky
7f4ba44f37 This is implemented. We now generate: 
entry:
        icmp ugt i32 %x, 4              ; <i1>:0 [#uses=1]
        br i1 %0, label %cond_true, label %cond_false

cond_true:              ; preds = %entry
        %tmp1 = tail call i32 (...)* @bar( i32 12 )             ; <i32> [#uses=0]
        ret void

cond_false:             ; preds = %entry
        switch i32 %x, label %cond_true15 [
                 i32 4, label %cond_true3
                 i32 3, label %cond_true7
                 i32 2, label %cond_true11
                 i32 0, label %cond_false17
        ]

...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35142 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-18 14:37:20 +00:00
Evan Cheng
cf596c54d4 - Merge UsedBlocks info after two virtual registers are coalesced. 
- Use distance to closest use to determine whether to abort coalescing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35141 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-18 09:05:55 +00:00
Evan Cheng
e951cd1647 Keep UsedBlocks info accurate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35140 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-18 09:02:31 +00:00
Nick Lewycky
1eda0f60d7 Propagate ValueRanges across equality. 
Add some more micro-optimizations: x * 0 = 0, a - x = a --> x = 0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35138 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-18 01:09:32 +00:00
Anton Korobeynikov
1cc6452181 Silence warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35137 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-17 14:48:06 +00:00
Evan Cheng
c6a2410d58 Track the BB's where each virtual register is used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35135 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-17 09:29:54 +00:00
Evan Cheng
ba1a3df608 Joining a live interval of a physical register with a virtual one can turn out 
to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!

Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35134 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-17 09:27:35 +00:00
Evan Cheng
db264ae07f Use SmallSet instead of std::set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35133 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-17 08:53:30 +00:00
Evan Cheng
2edd563825 If sdisel has decided to sink GEP index expression into any BB. Replace all uses 
in that BB.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35132 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-17 08:22:49 +00:00
Devang Patel
84f7fd2483 Support 'I' inline asm constraint. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35129 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-17 00:13:28 +00:00
Lauro Ramos Venancio
368f20fda4 Only ARMv6 has BSWAP. 
Fix MultiSource/Applications/aha test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35128 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 22:54:16 +00:00
Evan Cheng
9e2d86add8 Turn on GEP index sinking by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35127 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 18:32:30 +00:00
Evan Cheng
9f5ead9601 Stupid bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35126 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 17:50:20 +00:00
Bill Wendling
1b7a81d3ae And now support for MMX logical operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35125 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 09:44:46 +00:00
Evan Cheng
3cd4e5095b Sink a binary expression into its use blocks if it is a loop invariant 
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35123 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 08:46:27 +00:00
Evan Cheng
2770747216 Added isLegalAddressExpression(). Only allows X +/- C for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35122 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 08:43:56 +00:00
Evan Cheng
14245a9d62 Added isLegalAddressExpression hook to test if the given expression can be 
folded into target addressing mode for the given type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35121 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 08:42:32 +00:00
Nick Lewycky
4c70875774 Add more comments and update to new asm syntax. 
Add new micro-optimizations.

Add icmp predicate snuggling. Given %x ULT 4, "icmp ugt %x, 2" becomes
"icmp eq %x, 3". This doesn't apply in any non-trivial cases yet due to missing
support for NE values in ValueRanges.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35119 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 02:37:39 +00:00
Bill Wendling
74027e98f1 Multiplication support for MMX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35118 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-15 21:24:36 +00:00
Evan Cheng
56fdd7af88 Debugging output stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35117 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-15 21:19:28 +00:00
Evan Cheng
c6deb3d447 Estimate a cost using the possible number of scratch registers required and use 
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35109 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-14 22:43:40 +00:00
Evan Cheng
ba693005e9 Under X86-64 large code model, do not emit 32-bit pc relative calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35108 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-14 22:11:11 +00:00
Evan Cheng
4485d3897b Notes about codegen issues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35107 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-14 21:03:53 +00:00
Evan Cheng
e70ef98043 Clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35105 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-14 20:20:19 +00:00
Evan Cheng
774be29769 Oops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35104 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-14 19:44:58 +00:00
Evan Cheng
a19ac52863 X86-64 JIT is in large code model. Need stubs for direct calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35097 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-14 10:51:55 +00:00
Evan Cheng
8510dc086e x86-64 JIT stub codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35096 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-14 10:48:08 +00:00
Evan Cheng
5c0b61a64b Preliminary support for X86-64 JIT stub codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35095 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-14 10:44:30 +00:00
Zhou Sheng
adc149549d ShiftAmt might equal to zero. Handle this situation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35094 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-14 09:07:33 +00:00
Zhou Sheng
9670445cd4 Enable KnownZero/One.clear(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35093 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-14 03:21:24 +00:00
Evan Cheng
61230d18d2 Try schedule def + use closer whne Sethi-Ullman numbers are the same. 
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4

Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2

This creates more short live intervals which work better with the register
allocator.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35089 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-13 23:25:11 +00:00
Evan Cheng
a13fd108f2 AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35088 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-13 21:05:54 +00:00
Evan Cheng
961f879ed8 Zero is always a legal AM immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35087 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-13 20:37:59 +00:00
Evan Cheng
1d95816db5 Correct type info for isLegalAddressImmediate() check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35086 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-13 20:34:37 +00:00
Nicolas Geoffray
b2ec1cc6cb Stack and register alignment of call arguments in the ELF ABI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35083 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-13 15:02:46 +00:00
Chris Lattner
bc1dbfce62 ifdef out some dead code. 
Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35082 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-13 14:27:42 +00:00
Zhou Sheng
b277b16593 For expression like 
"APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth)",
to handle ShiftAmt == BitWidth situation, use zextOrCopy() instead of
zext().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35080 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-13 06:40:59 +00:00
Zhou Sheng
771dbf7677 In APInt version ComputeMaskedBits(): 
1. Ensure VTy, KnownOne and KnownZero have same bitwidth.
  2. Make code more efficient.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35078 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-13 02:23:10 +00:00
Evan Cheng
e8308df0b9 Implement getTargetLowering() or else LSR won't be using ARM specific hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35077 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-13 01:20:42 +00:00
Evan Cheng
c289faf015 More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35076 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 23:37:10 +00:00
Evan Cheng
b01fad6d19 Updated TargetLowering LSR addressing mode hooks for ARM and Thumb. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35075 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 23:30:29 +00:00
Evan Cheng
861939152d More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35074 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 23:29:01 +00:00
Evan Cheng
a8a155e77f More flexible TargetLowering LSR hooks for testing whether an immediate is 
a legal target address immediate or scale.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35073 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 23:28:50 +00:00
Evan Cheng
5eef2d21a0 Use new TargetLowering addressing modes hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35072 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 23:27:37 +00:00
Evan Cheng
37e8856f74 Stupid bug: SSE2 supports v2i64 add / sub. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35070 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 22:58:52 +00:00
Reid Spencer
4fd8606791 Revert the last patch as it violates the conditions of sext/zext. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35068 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 18:37:25 +00:00
Jeff Cohen
2b7d7b57ae Unbreak C++ build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35067 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 17:57:00 +00:00
Jeff Cohen
c4558fde76 Unbreak VC++ build. Do not use identifiers starting with _ as they are reserved and 
can collide with system defined names.  Windows defines _BB, for example.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35066 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 17:56:27 +00:00
Zhou Sheng
7d820f57e2 For APInt::z/sext(width), if width == BitWidth, just return *this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35065 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 17:47:45 +00:00
Reid Spencer
8cb6834ccf Add an APInt version of SimplifyDemandedBits. 
Patch by Zhou Sheng.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35064 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 17:25:59 +00:00
Reid Spencer
6b79e2d202 Add an APInt version of ShrinkDemandedConstant. 
Patch by Zhou Sheng.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35063 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 17:15:10 +00:00
Zhou Sheng
edd089c86a Avoid to assert on "(KnownZero & KnownOne) == 0". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35062 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 16:54:56 +00:00
Zhou Sheng
430f626937 In function ComputeMaskedBits(): 
1. Replace getSignedMinValue() with getSignBit() for better code readability.
  2. Replace APIntOps::shl() with operator<<= for convenience.
  3. Make APInt construction more effective.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35060 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 05:44:52 +00:00
Nick Lewycky
e677a0b099 Add value ranges. Currently inefficient in both execution time and 
optimization power.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35058 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-10 18:12:48 +00:00
Anton Korobeynikov
e2ff29c17c Use range tests in LowerSwitch, where possible 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35057 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-10 16:46:28 +00:00
Nick Lewycky
3400e6af6b Add getter methods for the extremes of a ConstantRange. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35056 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-10 15:54:12 +00:00
Bill Wendling
c1fb0473ed Adding more arithmetic operators to MMX. This is an almost exact copy of 
the addition. Please let me know if you have suggestions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35055 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-10 09:57:05 +00:00
Devang Patel
f7543fe35a Remove dead comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35053 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 23:41:03 +00:00
Devang Patel
a5b7dc5ef8 Avoid recursion. Use iterative algorithm for RenamePass(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35052 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 23:39:14 +00:00
Devang Patel
4fe26582c0 Increment iterator now because IVUseShouldUsePostIncValue may remove 
User from the list of I users.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35051 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 21:19:53 +00:00
Reid Spencer
afc378201d Regenerate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35050 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 21:19:09 +00:00
Evan Cheng
1a9da0d66c Minor stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35049 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 19:46:06 +00:00
Evan Cheng
44f4fca3c0 Add comments about LSR / ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35048 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 19:35:33 +00:00
Evan Cheng
2265b49193 Unfinished work and ideas related to register scavenger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35047 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 19:34:51 +00:00
Reid Spencer
87707b90b1 For PR1245: 
Account for the sign bit when computing the number of bits required for
a negative integer literal constant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35046 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 19:26:52 +00:00
Dale Johannesen
818c085232 apply comments from review of last patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35045 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 19:18:59 +00:00
Dale Johannesen
a6bc6fc170 Add some observations from CoreGraphics benchmark. Remove register 
scavenging todo item, since it is now implemented.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35044 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 17:58:17 +00:00
Anton Korobeynikov
349ec1c11b Unbreak mingw32 build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35042 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 11:53:34 +00:00
Evan Cheng
e2ee99620f If a virtual register is already marked alive in this block, that means it is 
alive in one of the successor block. Do not add it to the kill list.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35041 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 09:48:56 +00:00
Evan Cheng
219705131d Print preds / succs BB numbers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35040 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 08:29:08 +00:00
Evan Cheng
f0e3bb1333 Avoid variable shadowing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35039 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 06:02:17 +00:00
Bill Wendling
47992ea4be Don't use std::hex. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35038 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-08 23:37:24 +00:00
Bill Wendling
3bae2e97d9 Don't use a cast. It causes an error on some platforms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35037 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-08 23:26:50 +00:00
Evan Cheng
23a9570494 Implement inline asm modifier c. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35035 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-08 22:42:46 +00:00
Chris Lattner
6dfc6806bf implement support for floating point constants used as inline asm memory operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35033 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-08 22:29:47 +00:00