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49021 Commits

Author SHA1 Message Date
Jim Grosbach
857e1a7b3f ARM vector compare to zero instruction assembly parsing support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 23:51:13 +00:00
Andrew Trick
b1831c6640 Allow loop unrolling to get known trip counts from ScalarEvolution. 
SCEV unrolling can unroll loops with arbitrary induction variables. It
is a prerequisite for -disable-iv-rewrite performance. It is also
easily handles loops of arbitrary structure including multiple exits
and is generally more robust.

This is under a temporary option to avoid affecting default
behavior for the next couple of weeks. It is needed so that I can
checkin unit tests for updateUnloop.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137384 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 23:36:16 +00:00
Jakob Stoklund Olesen
8facc7def8 Remove the InterferenceResult class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137381 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:46:06 +00:00
Jakob Stoklund Olesen
fe026e1829 Eliminate the last use of InterferenceResult. 
The Query class now holds two iterators instead of an InterferenceResult
instance. The iterators are used as bookmarks for repeated
collectInterferingVRegs calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137380 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:46:04 +00:00
Akira Hatanaka
9029cf20e1 Enclose directive .cprestore with .set macro and nomacro to silence assembler 
warning. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:42:31 +00:00
Jim Grosbach
d30970fb6c Remove no-longer-true comments. These are for the assembler, also. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137375 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:30:30 +00:00
Jim Grosbach
342ebd5f38 ARM STRT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:18:00 +00:00
Owen Anderson
41ff834e91 Make the USAT16 operand decoder auto-generate-able. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137371 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:10:11 +00:00
Owen Anderson
adf2b094cb Add another accidentally omitted predicate operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137370 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:08:38 +00:00
Owen Anderson
1fb6673bc2 Add missing predicate operand on SMLA and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137368 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:05:38 +00:00
Jim Grosbach
dd32ba337a ARM load shifted register pre-index fix shift value asm parser encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:05:09 +00:00
Owen Anderson
796d6b7602 Handle new register classes in Thumb2 mode. Should fix the ARM buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137364 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:52:38 +00:00
Owen Anderson
05b0c9f41e Making SEL decodings auto-generate-able. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137363 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:50:56 +00:00
Bruno Cardoso Lopes
ef8d6999f3 Add a dag combine to xform 256-bit shuffles into simple vector 
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137362 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:50:44 +00:00
Jim Grosbach
89958d50c3 Tidy up comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137359 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:41:59 +00:00
Owen Anderson
cbfc044acd Fix decoding support for STREXD and LDREXD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:34:58 +00:00
Jakob Stoklund Olesen
9942ba9c0e Remove more dead code. 
collectInterferingVRegs will be the primary function for interference
checks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:18:34 +00:00
Jim Grosbach
7b8f46cf9e ARM STRH assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:17:22 +00:00
Dan Gohman
fa7eed1f8e Fix typos in comments, and delete an unused function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137352 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:06:32 +00:00
Akira Hatanaka
1f8d822023 Add isIndirectBranch flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137351 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:05:37 +00:00
Jakob Stoklund Olesen
98985f959c Privatize an unused part of the LiveIntervalUnion::Query interface. 
No clients are iterating over interference overlaps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137350 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:00:42 +00:00
Owen Anderson
508e1d3db5 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:47:56 +00:00
Jakob Stoklund Olesen
bb688cec09 Remove some dead code. 
The InterferenceResult iterator turned out to be less important than we
thought it would be.  LiveIntervalUnion clients want higher level
information, like the list of interfering virtual registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137346 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:41:41 +00:00
Jim Grosbach
45251b3707 Tidy up. Remove unused template parameter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137345 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:41:13 +00:00
Owen Anderson
9fe72bcd37 Improve operand validation for Thumb2 addressing modes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:40:40 +00:00
Jim Grosbach
14605d1a67 ARM STRD assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:28:23 +00:00
Andrew Trick
c12d9b9dfb Fix for LoopInfo::updateUnloop. Remove subloop blocks from former 
ancestor loops.

I have a unit test that depends on scev-unroll, which unfortunately
isn't checked in. But I will check it in when I can.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137341 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:27:32 +00:00
Owen Anderson
26d2f0ac91 Continue to tighten decoding by performing more operand validation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:21:46 +00:00
Jim Grosbach
ade7d00f5a Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:13:35 +00:00
Jim Grosbach
10348e70d5 ARM STRBT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:04:56 +00:00
Jim Grosbach
548340c4bf ARM STR(immediate) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:22:40 +00:00
Owen Anderson
71156a6e00 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:00:18 +00:00
Bruno Cardoso Lopes
59353b436a Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137324 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:59:13 +00:00
Owen Anderson
2b7b238e84 Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:55:42 +00:00
Owen Anderson
3dac0bec7e Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:41:59 +00:00
Benjamin Kramer
0fa5e053a9 Plug a memory leak. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:39:28 +00:00
Owen Anderson
ae0bc5deaa Improve error checking in the new ARM disassembler. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:24:51 +00:00
Jim Grosbach
f6713916fb ARM push of a single register encodes as pre-indexed STR. 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:07:11 +00:00
Andrew Trick
5c1ff1f2f2 Cleanup. Another thorough review by Nick! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137317 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 17:54:58 +00:00
Jim Grosbach
f8fce711e8 ARM pop of a single register encodes as post-indexed LDR. 
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 17:35:48 +00:00
Nadav Rotem
6236f7f2b6 Add a comment, per Bruno's CR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137313 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 17:05:47 +00:00
Nadav Rotem
f80a894bf0 [AVX] When joining two XMM registers into a YMM register, make sure that the 
lower XMM register gets in first. This will allow the SUBREG pattern to
elliminate the first vector insertion. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137310 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 16:49:36 +00:00
Nadav Rotem
5e742a3e1b [AVX] If the data which is going to be saved is already in two XMM registers 
(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.

Before:
                vinsertf128         $1, %xmm3, %ymm0, %ymm3
                vinsertf128         $0, %xmm1, %ymm3, %ymm1
                vmovaps              %ymm1, 416(%rsp)

After:
                vmovaps              %xmm3, 416+16(%rsp)
                vmovaps              %xmm1, 416(%rsp)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137308 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 16:41:21 +00:00
Chris Lattner
f4ea68fa5a fix PR10605 / rdar://9930964 by adding a pretty scary missed check. 
It's somewhat surprising anything works without this.  Before we would
compile the testcase into:

test:                                   # @test
	movl	$4, 8(%rdi)
	movl	8(%rdi), %eax
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2

now we produce:

test:                                   # @test
	movl	8(%rdi), %eax
	movl	$4, 8(%rdi)
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137303 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 06:26:54 +00:00
Bruno Cardoso Lopes
b02c0ace20 Cleanup: Remove Int_ CVTSS2SI* forms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137297 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 02:52:36 +00:00
Bruno Cardoso Lopes
5f1d8abf75 Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing 
infinite recursive calls in legalize. Fix PR10562

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137296 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 02:49:44 +00:00
Bruno Cardoso Lopes
a5134a0ea3 Use the splat index to generate the desired shuffle. Otherwise we 
could only get undefs and the vector shuffle becomes an undef,
generating wrong code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 02:49:41 +00:00
Eli Friedman
586272d67c Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2). 
Fixes PR9693.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 01:48:05 +00:00
Devang Patel
5bc942cc3c Stay within 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 23:58:09 +00:00
Jim Grosbach
59999264e6 ARM LDRT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137282 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 23:43:54 +00:00