Commit Graph

90994 Commits

Author SHA1 Message Date
Duncan Sands
79f615cbfe There is no longer any need to silence this compiler warning as the warning has
been turned off globally.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178451 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31 17:44:09 +00:00
Hal Finkel
4345e8040f Cleanup ImmToIdxMap and noImmForm in PPCRegisterInfo
ImmToIdxMap should be a DenseMap (not a std::map) because there
is no ordering requirement. Also, we don't need a separate list
of instructions for noImmForm in eliminateFrameIndex, because this
list is essentially the complement of the keys in ImmToIdxMap.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178450 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31 14:43:31 +00:00
Benjamin Kramer
b8f0d89d05 X86: Promote sitofp <8 x i16> to <8 x i32> when AVX is available.
A vector sext + sitofp is a lot cheaper than 8 scalar conversions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178448 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31 12:49:15 +00:00
Hal Finkel
8049ab15e4 Add the PPC lfiwax instruction
This instruction is available on modern PPC64 CPUs, and is now used
to improve the SINT_TO_FP lowering (by eliminating the need for the
separate sign extension instruction and decreasing the amount of
needed stack space).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31 10:12:51 +00:00
Hal Finkel
9ad0f4907b Cleanup PPC(64) i32 -> float/double conversion
The existing SINT_TO_FP code for i32 -> float/double conversion was disabled
because it relied on broken EXTSW_32/STD_32 instruction definitions. The
original intent had been to enable these 64-bit instructions to be used on CPUs
that support them even in 32-bit mode.  Unfortunately, this form of lying to
the infrastructure was buggy (as explained in the FIXME comment) and had
therefore been disabled.

This re-enables this functionality, using regular DAG nodes, but only when
compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead)
are removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178438 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31 01:58:02 +00:00
Benjamin Kramer
0b68b758bb DAGCombine: visitXOR can replace a node without returning it, bail out in that case.
Fixes the crash reported in PR15608.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178429 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 21:28:18 +00:00
Justin Holewinski
531ebc8a3c Add start of user documentation for NVPTX
Summary: This is the beginning of user documentation for the NVPTX back-end.  I want to ensure I am integrating this properly into the rest of the LLVM documentation.

Differential Revision: http://llvm-reviews.chandlerc.com/D600

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178428 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 16:41:14 +00:00
Benjamin Kramer
42734cfb41 Change '@SECREL' suffix to GAS-compatible '@SECREL32'.
'@SECREL' is what is used by the Microsoft assembler, but GNU as expects '@SECREL32'.
With the patch, the MC-generated code works fine in combination with a recent GNU as (2.23.51.20120920 here).

Patch by David Nadlinger!
Differential Revision: http://llvm-reviews.chandlerc.com/D429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178427 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 16:21:50 +00:00
Sean Silva
6ef362a6de [docs] llvmbugs is not the place for patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178426 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 15:33:02 +00:00
Sean Silva
fb7aa39435 [docs] Annotate mailing lists with their "name".
Nobody says "the developer's list" or "commits archive"; they always say
"llvmdev" or "llvm-commits". It makes sense for our documentation to
at least make that association explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178425 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 15:33:01 +00:00
Sean Silva
135856526c [docs] Reorganize mailing lists.
Order them roughly by "which one should a newbie join first".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178424 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 15:32:54 +00:00
Sean Silva
bd1aecbea7 [docs] Pull IRC and Mailing Lists under a new "Community" heading.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 15:32:51 +00:00
Sean Silva
cad9b9cdb4 [docs] The GEP FAQ is not "design and overview"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178422 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 15:32:50 +00:00
Sean Silva
a6a22233a8 [docs] Put DeveloperPolicy under "Development Process Documentation"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178421 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 15:32:47 +00:00
Benjamin Kramer
ddcc82b871 Put private class into an anonmyous namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178420 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 15:23:08 +00:00
Justin Holewinski
b24fc1c7f7 [NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178417 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 14:29:30 +00:00
Justin Holewinski
21fdcb0271 [NVPTX] Add NVVMReflect pass to allow compile-time selection of
specific code paths.

This allows us to write code like:

  if (__nvvm_reflect("FOO"))
    // Do something
  else
    // Do something else

and compile into a library, then give "FOO" a value at kernel
compile-time so the check becomes a no-op.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 14:29:25 +00:00
Justin Holewinski
3639ce2575 [NVPTX] Run clang-format on all NVPTX sources.
Hopefully this resolves any outstanding style issues and gives us
an automated way of ensuring we conform to the style guidelines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178415 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 14:29:21 +00:00
Benjamin Kramer
a9f83517fc Object: Turn a couple of degenerate for loops into while loops.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 13:07:51 +00:00
Shuxin Yang
2d10010649 Implement XOR reassociation. It is based on following rules:
rule 1: (x | c1) ^ c2 => (x & ~c1) ^ (c1^c2),
     only useful when c1=c2
  rule 2: (x & c1) ^ (x & c2) = (x & (c1^c2))
  rule 3: (x | c1) ^ (x | c2) = (x & c3) ^ c3 where c3 = c1 ^ c2
  rule 4: (x | c1) ^ (x & c2) => (x & c3) ^ c1, where c3 = ~c1 ^ c2

 It reduces an application's size (in terms of # of instructions) by 8.9%.
 Reviwed by Pete Cooper. Thanks a lot!

 rdar://13212115  


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178409 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 02:15:01 +00:00
Akira Hatanaka
fd2cd0db97 [mips] Add patterns for DSP indexed load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178408 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 02:14:45 +00:00
Akira Hatanaka
175f0fd99a [mips] Define reg+imm load/store pattern templates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 02:01:48 +00:00
Akira Hatanaka
2c2c33a167 [mips] Fix DSP instructions to have explicit accumulator register operands.
Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:58:00 +00:00
Akira Hatanaka
7e287bfb58 Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178405 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:46:28 +00:00
Akira Hatanaka
d593a77b4c [mips] Move the code which does dag-combine for multiply-add/sub nodes to
derived class MipsSETargetLowering.

We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16
doesn't have support for multipy-add/sub instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178404 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:42:24 +00:00
Akira Hatanaka
f5926fd844 [mips] Fix definitions of multiply, multiply-add/sub and divide instructions.
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.

Mips16's instructions are unaffected by this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:36:35 +00:00
Akira Hatanaka
9cf0724cc3 [mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178396 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:16:38 +00:00
Akira Hatanaka
2459afe697 Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178395 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:15:17 +00:00
Akira Hatanaka
dd958925b0 [mips] Add mips-specific nodes which will be used to select multiply and divide
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:14:04 +00:00
Akira Hatanaka
cbcdcfbda5 [mips] Implement getRepRegClassFor in MipsSETargetLowering. This function is
called in several places in ScheduleDAGRRList.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178393 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:12:05 +00:00
Akira Hatanaka
8f4d3800a7 [mips] Fix MipsSEInstrInfo::copyPhysReg, loadRegFromStack and storeRegToStack
to handle accumulator registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178392 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:08:05 +00:00
Akira Hatanaka
d6a77822a9 [mips] Expand pseudo load, store and copy instructions right before
callee-saved scan.

The code makes use of register's scavenger's capability to spill multiple
registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178391 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:04:11 +00:00
Akira Hatanaka
2cd7d3f9ce [mips] Define pseudo instructions for spilling and copying accumulator
registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 00:54:52 +00:00
Eric Christopher
f7cef7081b Use SmallVectorImpl instead of SmallVector at the uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178386 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 23:34:06 +00:00
Bob Wilson
d696544eac Run the ObjCARCContract pass for LTO. <rdar://problem/13538084>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178385 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 23:28:55 +00:00
Michael Gottesman
2030d5f3e9 Updated test0 of retain-not-declared.ll to reflect the fact that objc-arc-expand runs before objc-arc/objc-arc-contract.
Specifically, objc-arc-expand will make sure that the
objc_retainAutoreleasedReturnValue, objc_autoreleaseReturnValue, and ret
will all have %call as an argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178382 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 22:44:59 +00:00
Jean-Luc Duprat
e1e9366281 SmallVector and SmallPtrSet allocations now power-of-two aligned.
This time tested on both OSX and Linux.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178377 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 22:07:12 +00:00
Sean Silva
4991289b33 [docs] The STL "binary search" has a non-obvious name.
std::lower_bound is the canonical "binary search" in the STL
(std::binary_search generally is not what you want). The name actually
makes a lot of sense (and also has a beautiful symmetry with the
std::upper_bound algorithm). The name is nonetheless non-obvious.

Also, remove mention of "radix search". It's not even clear how that
would work in the context of a sorted vector. AFAIK "radix search" only
makes sense when you have a trie-like data structure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178376 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 21:57:47 +00:00
Timur Iskhodzhanov
7d21a64abf Exclude the X86/complex-fca.ll test at it probably wasn't supposed to work on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178375 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 21:54:00 +00:00
Michael Gottesman
3e9f3a0389 Add clang.arc.used to ModuleHasARC so ARC always runs if said call is present in a module.
clang.arc.used is an interesting call for ARC since ObjCARCContract
needs to run to remove said intrinsic to avoid a linker error (since the
call does not exist).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178369 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 21:15:23 +00:00
Jyotsna Verma
2a88555e0d Hexagon: Add emitFrameIndexDebugValue function to emit debug information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178368 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 21:09:53 +00:00
Eric Christopher
2df938ad71 Use 12 as the magic number for our abbreviation data and our
die values. A lot of DIEs have 10 attributes in C++ code (example
clang), none had more than 12. Seems like a good default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 20:23:06 +00:00
Eric Christopher
c126c3232a Move the construction of the skeleton compile unit after the
entire original compile unit has been constructed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178365 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 20:23:02 +00:00
Adrian Prantl
22313e5c07 move testcase into appropriate X86 subdirectory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 20:14:08 +00:00
Hal Finkel
0882fd6c4f Implement FRINT lowering on PPC using frin
Like nearbyint, rint can be implemented on PPC using the frin instruction. The
complication comes from the fact that rint needs to set the FE_INEXACT flag
when the result does not equal the input value (and frin does not do that). As
a result, we use a custom inserter which, after the rounding, compares the
rounded value with the original, and if they differ, explicitly sets the XX bit
in the FPSCR register (which corresponds to FE_INEXACT).

Once LLVM has better modeling of the floating-point environment we should be
able to (often) eliminate this extra complexity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178362 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 19:41:55 +00:00
Akira Hatanaka
5114226c18 [mips] Define a function which returns the GPR register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178359 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 19:17:42 +00:00
Andrew Trick
bc4de7cec1 Fix TableGen subtarget-emitter to handle A9/Swift.
A9 uses itinerary classes, Swift uses RW lists. This tripped some
verification when we're expanding variants. I had to refine the
verification a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178357 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 19:08:31 +00:00
Matt Arsenault
71246fb830 Build fixes for STLPort + GCC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 18:48:45 +00:00
Matt Arsenault
7d4ff60b55 Fix loop style
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178355 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 18:48:42 +00:00
Adrian Prantl
f24caa4421 Split the llvm/tools/clang/test/CodeGenObjC/debug-info-blocks.m testcase into a CFE and LLVM part.
rdar://problem/12767564

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178353 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 18:08:14 +00:00