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Author SHA1 Message Date
Craig Topper
1415ca1781 Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200624 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-02 07:08:01 +00:00
Craig Topper
f0b161d774 Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200522 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-31 08:47:06 +00:00
Craig Topper
45b8e5fa49 Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200520 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-31 07:00:55 +00:00
Craig Topper
28d965d300 Couple minor formatting fixes to the XXXGenDAGISel.inc files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200459 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-30 06:42:52 +00:00
Craig Topper
01a5c17219 Delete the Matchers stored in the SmallVectors in SwitchOpcodeMatcher/SwitchTypeMatcher. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200377 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-29 07:06:07 +00:00
David Woodhouse
4faa861f19 Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200349 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-28 23:13:18 +00:00
David Woodhouse
4396f5d9d2 Change MCStreamer EmitInstruction interface to take subtarget info 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200345 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-28 23:12:42 +00:00
Craig Topper
90790c3217 Improve handling of EnforceSmallerThan. Remove all types that are smaller from the larger set not just the smallest type from the smaller set. Ensure 'smaller' vectors have the same or fewer total bits. Similar for 'larger' vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200287 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-28 04:49:01 +00:00
Craig Topper
55604d9716 Don't use EnforceSmallerThan for EnforceVectorSubVectorTypeIs. EnforceSmallerThan doesn't handle vectors quite right and should really enforce that vectors have the same number of elements. Add explicit checks for vector element count differing in EnforceVectorSubVectorTypeIs instead. This removes some unnecessary type checks in X86GenDAGISel.inc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200091 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-25 17:40:33 +00:00
Craig Topper
858594edb0 Fix typo in commment tyep->type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200089 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-25 17:34:23 +00:00
Craig Topper
f6deb18968 Use isConcrete and getConcrete instead of using TypeVec directly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200071 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-25 05:33:48 +00:00
Craig Topper
f5f44a149e Fix EnforceSmallerThan to check !hasVectorTypes on the other type instead of this type to force this type to be scalar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200070 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-25 05:17:38 +00:00
Craig Topper
82f50dc0c2 Remove TGValueTypes.cpp from CMakeLists.txt which I forgot to do in r200036. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200037 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-24 20:51:32 +00:00
Craig Topper
f3474549ba Replace tablegen uses of EVT with MVT. Add isOverloaded() to MVT to facilitate. Remove TGValueTypes.cpp since its unused now (and may have been before). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200036 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-24 20:50:47 +00:00
Alp Toker
ae43cab6ba Fix known typos 
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-24 17:20:08 +00:00
David Woodhouse
674140fc3e ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199806 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 15:08:36 +00:00
David Woodhouse
ccbfd5b18a [x86] Allow address-size overrides for STOS[BWLQ] (PR9385) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199804 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 15:08:21 +00:00
David Woodhouse
db9fa461d7 [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199803 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 15:08:08 +00:00
Craig Topper
8f74ea3fa1 Use ArrayRef to simplify some code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199712 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-21 07:20:05 +00:00
David Woodhouse
9334b07527 [x86] Fix disassembly of MOV16ao16 et al. 
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199654 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-20 12:02:53 +00:00
Craig Topper
85026d9375 Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199364 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-16 07:36:58 +00:00
Kostya Serebryany
3846ce9490 replace LeakSanitizerIsTurnedOffForTheCurrentProcess with __lsan_is_turned_off, but this time hide it under __has_feature(address_sanitizer); also include <sanitizer/lsan_interface.h> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199303 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-15 07:59:37 +00:00
Craig Topper
38e6f7301d Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199295 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-15 05:02:02 +00:00
Lang Hames
5f33cbc414 Add FPExt option to CCValAssign::LocInfo. When generating calling-convention 
promotion code, Tablegen will now select FPExt for floating point promotions
(previously it had returned AExt, which is not valid for floating point types).

Any out-of-tree targets that were relying on AExt being returned for FP
promotions will need to update their code check for FPExt instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199252 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-14 19:56:36 +00:00
Craig Topper
8e31bc35ec Remove stray comma in enum to satisfy -Wpedantic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199194 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-14 08:07:10 +00:00
Craig Topper
525ae45240 Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. 
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199193 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-14 07:41:20 +00:00
Elena Demikhovsky
1f044d443d AVX-512: Embedded Rounding Control - encoding and printing 
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199102 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-13 12:55:03 +00:00
Roman Divacky
af43b47c5a Constant propagate MachineInstrClassName. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198969 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-10 22:59:49 +00:00
Rafael Espindola
dd86e54b61 All backends use MC now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198959 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-10 21:49:27 +00:00
Kostya Serebryany
ab39685c77 reapply r198858: Disable LeakSanitizer in TableGen binaries, see PR18325; this time LeakSanitizerIsTurnedOffForTheCurrentProcess is used instead of __lsan_is_turned_off 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198922 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-10 08:05:42 +00:00
Alp Toker
d92ff21d6f Revert "Disable LeakSanitizer in TableGen binaries, see PR18325" 
To declare or define reserved identifers is undefined behaviour in standard
C++. This needs to be addressed in compiler-rt before it can be used in LLVM.

See the list discussion for details.

This reverts commit r198858.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198884 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-09 19:40:55 +00:00
Kostya Serebryany
c50299bab6 Disable LeakSanitizer in TableGen binaries, see PR18325 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198858 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-09 09:26:26 +00:00
David Woodhouse
aab59870a4 [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand 
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.

Hm, perhaps we do need an AdSize16 bit after all?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198759 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-08 12:58:24 +00:00
Craig Topper
c8fd2c57c8 The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198589 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-06 06:57:27 +00:00
Craig Topper
adb7d3b49b Use patterns to remove some duplicate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198550 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 06:55:48 +00:00
Craig Topper
6a69266fed Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198547 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 05:46:38 +00:00
Craig Topper
09104ff9df Remove no longer needed x86 disassembler hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198546 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 05:10:07 +00:00
Craig Topper
01cb7fa977 Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198545 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 04:55:55 +00:00
Craig Topper
2b5dc93948 Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198544 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 04:32:42 +00:00
Craig Topper
527f132627 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198543 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 04:17:28 +00:00
Craig Topper
e43a0f8015 Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198530 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 01:35:51 +00:00
Craig Topper
62fe07a1ac Don't use PrintFatalError(which calls exit) for 'Primary decode conflict'. Just skip emitting the table. This way the main function will delete the output file instead of it remaining empty and confusing dependency checks if build is invoked a second time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198529 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 01:34:12 +00:00
Craig Topper
29d56f68c6 Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198515 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-04 22:29:41 +00:00
Craig Topper
030ceadd69 Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198475 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-04 05:09:27 +00:00
Hal Finkel
6fa9961327 [TableGen] Handle ValueType in CodeGenDAGPatterns GetNumNodeResults 
A ValueType in a pattern dag is a type cast, and GetNumNodeResults should
handle it (the type cast has only one result).

This comes up, for example, during the type checking of pattern fragments, for
example, AArch64's Neon_combine_2d fragment is:
  dag Operands = (ops node:$Rm, node:$Rn);
  dag Fragment = (v2f64 (concat_vectors (v1f64 node:$Rm), (v1f64 node:$Rn)));

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198347 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 20:47:05 +00:00
Craig Topper
d573aba8e1 Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198336 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 19:12:10 +00:00
Craig Topper
163868fec5 Remove unused HasFROperands field from disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198332 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 18:44:21 +00:00
Craig Topper
a7133ee752 Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198327 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 18:20:48 +00:00
Craig Topper
d4e0bc4316 Remove unnecessary stirng comparison from disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198325 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 17:41:40 +00:00
Craig Topper
e625100c6a Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198323 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 17:28:14 +00:00
Craig Topper
e61c70a085 Remove unused function argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198291 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 03:58:45 +00:00
Craig Topper
5cfd40ccd4 Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198284 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 21:52:57 +00:00
Craig Topper
95a3ccdd80 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198278 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 15:29:32 +00:00
Elena Demikhovsky
3062a311ac AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp 
Printing rounding control.
Enncoding for EVEX_RC (rounding control).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198277 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 15:12:34 +00:00
Craig Topper
979b2cd2bc Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198276 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 14:22:37 +00:00
Craig Topper
5cbbd7e1a5 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198265 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-31 17:21:44 +00:00
Craig Topper
e6d2dce7ab Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198238 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-30 19:16:48 +00:00
Craig Topper
d7109840cd Remove EscapeFilter. It's funcionality can be covered by correctly using ExtendedFilter and ExactFilter. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198226 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-30 17:37:10 +00:00
Craig Topper
d2f307195a Simplify filter accepts function to just return 'condition' instead of branching to return true/false. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198221 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-30 17:22:20 +00:00
Elena Demikhovsky
09a63715ce AVX-512: decoder for AVX-512, made by Alexey Bader. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198013 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-25 11:40:51 +00:00
Eric Christopher
75a8b23e10 [x86] Rename In32BitMode predicate to Not64BitMode 
That's what it actually means, and with 16-bit support it's going to be
a little more relevant since in a few corner cases we may actually want
to distinguish between 16-bit and 32-bit mode (for example the bare 'push'
aliases to pushw/pushl etc.)

Patch by David Woodhouse

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197768 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-20 02:04:49 +00:00
Hal Finkel
d715c3e9ac Add support for positionally-encoded operands to FixedLenDecoderEmitter 
Unfortunately, the PowerPC instruction definitions make heavy use of the
positional operand encoding heuristic to map operands onto bitfield variables
in the instruction definitions. Changing this to use name-based mapping is not
trivial, however, because additional infrastructure needs to be designed to
handle mapping of complex operands (with multiple suboperands) onto multiple
bitfield variables.

In the mean time, this adds support for positionally encoded operands to
FixedLenDecoderEmitter, so that we can generate a disassembler for the PowerPC
backend. To prevent an accidental reliance on this feature, and to prevent an
undesirable interaction with existing disassemblers, a backend must opt-in to
this support by setting the new decodePositionallyEncodedOperands
instruction-set bit to true.

When enabled, this iterates the variables that contribute to the instruction
encoding, just as the encoder does, and emulates the procedure the encoder uses
to map "numbered" operands to variables. The bit range for each variable is
also determined as the encoder determines them. This map is then consulted
during the decoder-generator's loop over operands to decode, allowing the
decoder to understand both position-based and name-based operand-to-variable
mappings.

As noted in the comment on the decodePositionallyEncodedOperands definition,
this support should be removed once it is no longer needed. There should be no
change to existing disassemblers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197691 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-19 16:12:53 +00:00
Hal Finkel
e14ad8538f Add support for PointerLikeRegClass to FixedLenDecoderEmitter 
This is more prep for adding the PowerPC disassembler. FixedLenDecoderEmitter
should recognize PointerLikeRegClass operands as register types, and generate
register-like decoding calls instead of treating them like immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197680 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-19 14:58:22 +00:00
Hal Finkel
af73dfe6f1 Support little-endian encodings in the FixedLenDecoderEmitter 
The convention used to specify the PowerPC ISA is that bits are numbered in
reverse order (0 is the index of the high bit). To support this "little endian"
encoding convention, CodeEmitterGen will reverse the bit numberings prior to
generating the encoding tables. In order to generate a disassembler,
FixedLenDecoderEmitter needs to do the same.

This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget
(where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This
is prep work for disassembly support in the PPC backend (which is the only
in-tree user of this little-endian encoding support).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197532 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-17 22:37:50 +00:00
Elena Demikhovsky
376a81d8ce AVX-512: Added legal type MVT::i1 and VK1 register for it. 
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197384 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-16 13:52:35 +00:00
Alp Toker
087ab613f4 Correct word hyphenations 
This patch tries to avoid unrelated changes other than fixing a few
hyphen-related ambiguities and contractions in nearby lines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196471 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-05 05:44:44 +00:00
Rafael Espindola
79a1166b13 Remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196066 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-02 05:10:04 +00:00
Juergen Ributzka
ba0f991a78 [weak vtables] Place class definitions into anonymous namespaces to prevent weak vtables. 
This patch places class definitions in implementation files into anonymous
namespaces to prevent weak vtables. This eliminates the need of providing an
out-of-line definition to pin the vtable explicitly to the file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195092 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 03:08:35 +00:00
Juergen Ributzka
354362524a [weak vtables] Remove a bunch of weak vtables 
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 00:57:56 +00:00
Alexey Samsonov
b21ab43cfc Revert r194865 and r194874. 
This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
  Base *foo = new Child();
  delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-18 09:31:53 +00:00
Ahmed Bougacha
b923d2f5f5 TableGen: Generate an enum for all named Operand types in tblgen'd InstrInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194978 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-17 21:24:41 +00:00
Owen Anderson
e553feab84 Small improvement to InstrinsicEmitter::EmitAttributes. This change removes the “pushing” and “clearing” of the SmallVector and instead uses const arrays to pass the attributeKinds to AttributeSet::get . 
Patch by Aditya Nandakumar.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194899 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-16 00:20:01 +00:00
Juergen Ributzka
5a364c5561 [weak vtables] Remove a bunch of weak vtables 
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-15 22:34:48 +00:00
Elena Demikhovsky
633f98bdfa AVX-512: added VPCONFLICT instruction and intrinsics, 
added EVEX_KZ to tablegen


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193959 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-03 13:46:31 +00:00
Andrew Trick
2343e3b228 Lower stackmap intrinsics directly to their target opcode in the DAG builder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193769 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 17:18:24 +00:00
Andrew Trick
2e50b8a08d Enable variable arguments support for intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193766 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 17:18:11 +00:00
Andrew Trick
cf940ceff7 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193765 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 17:18:07 +00:00
Ahmed Bougacha
1799684671 TableGen: remove unused variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193527 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-28 18:19:04 +00:00
Ahmed Bougacha
2b43ffff32 TableGen: Refactor DAG patterns to enable parsing one pattern at a time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193526 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-28 18:07:21 +00:00
Ahmed Bougacha
254ce94c26 TableGen: Refactor AsmWriterEmitter to keep AsmWriterInsts. 
These used to be referenced by the CGI->AWI map (in AsmWriterEmitter), but
stored in a vector local to EmitPrintInstruction. Move the vector to
AsmWriterEmitter too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193525 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-28 18:07:17 +00:00
Peter Collingbourne
8f70847f98 Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193043 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-20 03:19:25 +00:00
Craig Topper
c6f7c99809 Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 04:55:01 +00:00
Craig Topper
017d8a3e23 Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192525 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-12 05:41:08 +00:00
Craig Topper
c429b5cca1 Mark some more instructions as CodeGenOnly. Remove filters from the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192522 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-12 04:46:18 +00:00
Will Dietz
e3ba15c794 Add missing #include's to cctype when using isdigit/alpha/etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192519 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-12 00:55:57 +00:00
Craig Topper
e799dbc4bd Remove another unnecessary filter from the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192425 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 06:59:57 +00:00
Craig Topper
be5c1fd43f Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192339 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 04:26:52 +00:00
Craig Topper
5747f946ec More x86 disassembler filtering cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192279 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 06:12:53 +00:00
Craig Topper
10c7925d69 Remove some old filters from the x86 disassembler table builder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192275 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 05:02:29 +00:00
Craig Topper
d55fed16a4 Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192175 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 06:30:39 +00:00
Craig Topper
b9bc43852c Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 05:53:50 +00:00
Craig Topper
e778f82a1e Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192090 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 07:19:47 +00:00
Craig Topper
36a9b31b98 Add disassembler support for long encodings for INC/DEC in 32-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192086 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 04:28:06 +00:00
Craig Topper
936910d929 Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192026 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-05 05:38:16 +00:00
Craig Topper
596cfd045f Revert r191940 to see if it fixes the build bots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191941 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-04 05:52:17 +00:00
Craig Topper
d356295678 Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191940 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-04 05:22:20 +00:00
Craig Topper
279d28265d Add XOP disassembler support. Fixes PR13933. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191874 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 05:17:48 +00:00
Pete Cooper
da750239bd Add v4f16 to supported value types. 
This is useful for some ARM intrinsics such as VCVTN which does a <4 x float> <-> <4 x half> conversion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191870 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 03:29:21 +00:00
Rafael Espindola
8819c84aed Remove several unused variables. 
Patch by Alp Toker.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191757 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 13:32:03 +00:00
Richard Sandiford
737ca5f7ab Fix pattern sort in DAGISelEmitter.cpp 
The old code skipped one of the sorting criteria if either pattern had
no types.  This could lead to cycles of the form X < Y, Y < Z, Z < X.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191735 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 09:49:01 +00:00