Jakob Stoklund Olesen
5a0d4fcb8d
Handle composed subreg indices when processing REQ_SEQUENCE instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29 00:14:14 +00:00
Evan Cheng
82e0a1a1a8
Doh. Machine LICM is re-initializing the CSE map over and over. Patch by Anna Zaks. rdar://8037934.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105065 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29 00:06:36 +00:00
Evan Cheng
046fa3f90a
Fix some latency computation bugs: if the use is not a machine opcode do not just return zero.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105061 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 23:26:21 +00:00
Jakob Stoklund Olesen
2da5337024
Add a TargetRegisterInfo::composeSubRegIndices hook with a default
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implementation that is correct for most targets. Tablegen will override where
needed.
Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing
subreg indices when sustituting registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 18:18:53 +00:00
Stuart Hastings
8ffc42f8ea
Revert 104841, 104842, 104876 due to buildbot failures. Radar 7424645.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104953 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 16:41:07 +00:00
Dan Gohman
f75a7d3fbf
Eliminate the restriction that the array size in an alloca must be i32.
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This will help reduce the amount of casting required on 64-bit targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 01:14:11 +00:00
Jakob Stoklund Olesen
700bfada63
Add a -regalloc=default option that chooses a register allocator based on the -O
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optimization level.
This only really affects llc for now because both the llvm-gcc and clang front
ends override the default register allocator. I intend to remove that code later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 23:57:25 +00:00
Jim Grosbach
0798eddd07
Update the saved stack pointer in the sjlj function context following either
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an alloca() or an llvm.stackrestore(). rdar://8031573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 23:49:24 +00:00
Jim Grosbach
a65850230a
back out 104862/104869. Can reuse stacksave after all. Very cool.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 23:11:57 +00:00
Devang Patel
d8720f4ba3
Do not drop location info for inlined function args.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104884 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 20:25:04 +00:00
Jim Grosbach
084fb0ea32
hook ISD::STACKADDR to an intrinsic
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 18:52:11 +00:00
Devang Patel
55e9717e59
inlined function's arguments need a label to mark the start point because they are not directly attached to current function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 16:47:30 +00:00
Stuart Hastings
aa66d2f48a
Support for nested functions/classes in debug output. Radar 7424645.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104841 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 16:16:54 +00:00
Devang Patel
80250686d5
Simplify. Eliminate unneeded debug_loc entry.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 23:55:23 +00:00
Bill Wendling
804a231dd5
Add FIXME comment to remove this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104749 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 21:53:50 +00:00
Daniel Dunbar
cb8326dc09
MC: Add TargetMachine support for setting the value of MCRelaxAll with
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-filetype=obj.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 21:48:55 +00:00
Devang Patel
77051f58e9
There is no need to force an line number entry (using previous location) for a temp label at unknown location.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 21:23:46 +00:00
Bill Wendling
8d717c7d99
Add "setjmp_syscall", "savectx", "qsetjmp", "vfork", "getcontext" to the list of
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usual suspects that could "return twice".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104737 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:39:00 +00:00
Jim Grosbach
23ff7cff52
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
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ISD::. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104734 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:22:18 +00:00
Devang Patel
394427b014
Update debug info when live-in reg is copied into a vreg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104732 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:18:50 +00:00
Bill Wendling
9af7e9a1b5
Move the check for "calls setjmp" to SelectionDAGISel so that it can be used by
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more than just the stack slot coloring algorithm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104722 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 19:46:12 +00:00
Devang Patel
b2b31a6f93
Identify instructions, that needs a label to mark debug info entity, in advance. This simplifies beginScope().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 19:37:24 +00:00
Dan Gohman
93d3433579
Eliminate the use of PriorityQueue and just use a std::vector,
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implementing pop with a linear search for a "best" element. The priority
queue was a neat idea, but in practice the comparison functions depend
on dynamic information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104718 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 18:52:00 +00:00
Dan Gohman
d89c258051
Delete an unused function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104716 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 18:34:12 +00:00
Devang Patel
b21a758bc2
Remove dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104706 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:42:50 +00:00
Devang Patel
e2df84254d
Do not construct location list backword!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104705 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:29:32 +00:00
Eric Christopher
174e597d46
Temporarily revert r104655 as it's breaking the bots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104664 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 01:59:55 +00:00
Dan Gohman
a4e4ffd389
Change push_all to a non-virtual function and implement it in the
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base class, since all the implementations are the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104659 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 01:10:55 +00:00
Dan Gohman
5eabaa2d7c
Trim #include.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104657 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:55:59 +00:00
Bill Wendling
be22683202
Dale and Evan suggested putting the "check for setjmp" much earlier in the
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machine code generation. That's a good idea, so I made it so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:32:40 +00:00
Devang Patel
c3f5f783a2
First cut at supporting .debug_loc section.
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This is used to track variable information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104649 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 23:40:22 +00:00
Bill Wendling
f10bc81b4e
Constify function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104646 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 22:02:22 +00:00
Dan Gohman
eddc114a66
Do one map lookup instead of two.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:59:42 +00:00
Eric Christopher
04386ca726
Move the verbose asm output up a bit so it can be used in the special cases
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as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:49:43 +00:00
Bill Wendling
5edfbdc963
Okay, bear with me here...
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If you have a setjmp/longjmp situation, it's possible for stack slot coloring to
reuse a stack slot before it's really dead. For instance, if we have something
like this:
1: y = g;
x = sigsetjmp(env, 0);
switch (x) {
case 1:
/* ... */
goto run;
case 0:
run:
do_run(); /* marked as "no return" */
break;
case 3:
if (...) {
/* ... */
goto run;
}
/* ... */
break;
}
2: g = y;
"y" may be put onto the stack, so the expression "g = y" is relying upon the
fact that the stack slot containing "y" isn't modified between (1) and (2). But
it can be, because of the "no return" calls in there. A longjmp might come back
with 3, modify the stack slot, and then go to case 0. And it's perfectly
acceptable to reuse the stack slot there because there's no CFG flow from case 3
to (2).
The fix is to disable certain optimizations in these situations. Ideally, we'd
disable them for all "returns twice" functions. But we don't support that
attribute. Check for "setjmp" and "sigsetjmp" instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:44:26 +00:00
Eric Christopher
02b46bc942
Add support for initialized global data for darwin tls. Update comments
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and testcases accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:28:50 +00:00
Jakob Stoklund Olesen
1fc8e759a7
Print symbolic SubRegIndex names on machine operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:38 +00:00
Dale Johannesen
86234c30a7
Fix another variant of PR 7191. Also add a testcase
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Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite. 8023512.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104624 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:47:23 +00:00
Dale Johannesen
61734eb117
Fix PR 7191. I have been unable to create a .ll file that fails, sorry.
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(oye, a word which should be better known to people writing tree
traversals, means grandchild.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104619 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:50:03 +00:00
Jakob Stoklund Olesen
b7a3170917
Disable invalid coalescer assertion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104574 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 00:15:18 +00:00
Bill Wendling
ef473bfc44
Print out the name of the function during SSC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104572 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 23:16:04 +00:00
Evan Cheng
3946043a80
Avoid adding duplicate function live-in's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:33:37 +00:00
Devang Patel
295cdf8b82
Do not emit line number entries for unknown debug values.
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This fixes recent regression in store.exp from gdb testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:26:49 +00:00
Nicolas Geoffray
3816c25fdc
Encode the Caml frametable by following what the comment says: the number of descriptors
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is first emitted, and StackOffsets are emitted in 16 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104488 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 12:24:11 +00:00
Daniel Dunbar
fdb5a86179
MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104463 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-23 17:44:06 +00:00
Evan Cheng
2457f2c661
Implement @llvm.returnaddress. rdar://8015977.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 01:47:14 +00:00
Jim Grosbach
5eb1951539
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
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Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 01:06:18 +00:00
Eric Christopher
8116ca5134
Add full bss data support for darwin tls variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104414 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:10:22 +00:00
Devang Patel
65eb482e8f
Collect variable information during endFunction() instead of beginFunction().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104412 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:04:14 +00:00
Bob Wilson
70fe6643d6
Clean up extra whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 23:53:55 +00:00
Eric Christopher
e81d010589
Make this LookAheadLimit, not the uninitialized LookAheadLeft.
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Evan please verify!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104408 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 23:40:03 +00:00
Evan Cheng
835810bbf8
Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104385 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 21:22:19 +00:00
Bob Wilson
78f006acdf
Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
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so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104380 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 21:05:32 +00:00
Evan Cheng
1015ba7018
- Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
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that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 20:53:24 +00:00
Jakob Stoklund Olesen
18b2c9d3bf
Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction
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reads or writes a register.
This takes partial redefines and undef uses into account.
Don't actually use it yet. That caused miscompiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 20:02:01 +00:00
Devang Patel
379fe83dda
Simplify
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104338 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 18:49:09 +00:00
Chris Lattner
65569b8ddf
constify accessor.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104325 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 17:47:50 +00:00
Jakob Stoklund Olesen
19f5f71bba
Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read."
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This reverts r104322. I think it was causing miscompilations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen
00c53caa33
Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.
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This correctly handles partial redefines and undef uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen
2afb7505c5
Teach VirtRegRewriter to handle spilling in instructions that have multiple
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definitions of the virtual register.
This happens when spilling the registers produced by REG_SEQUENCE:
%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0
The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 16:36:13 +00:00
Jakob Stoklund Olesen
63e6a488cb
If the first definition of a virtual register is a partial redef, add an
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<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104320 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 16:32:16 +00:00
Evan Cheng
b11ac950d6
Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 00:42:32 +00:00
Devang Patel
c0c5a26dea
Simplify.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104302 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 00:10:20 +00:00
Evan Cheng
1cc3984148
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 23:26:43 +00:00
Devang Patel
ee43286ca9
Refactor.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104265 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 19:57:06 +00:00
Jim Grosbach
76526f8863
Remove dbg_value workaround and associated command line option
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104254 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 18:34:01 +00:00
Devang Patel
26c1e56f13
Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 16:36:41 +00:00
Evan Cheng
15a16def6e
Add a hybrid bottom up scheduler that reduce register usage while avoiding
...
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104216 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 06:13:19 +00:00
Nick Lewycky
761fd4c1d9
Fix typo in comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104209 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 03:30:09 +00:00
Eric Christopher
c1a887d76d
Partial code for emitting thread local bss data.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104197 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 00:49:07 +00:00
Bob Wilson
492fd454ca
Optimize away insertelement of an undef value. This shows up in
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test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up. Radar 7998853.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104185 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 23:42:58 +00:00
Jim Grosbach
de70b1f9be
Enable preserving debug information through post-RA scheduling
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104175 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 22:57:47 +00:00
Jim Grosbach
309d20c89c
Fix the post-RA instruction scheduler to handle instructions referenced by
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more than one dbg_value instruction. rdar://7759363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104174 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 22:57:06 +00:00
Evan Cheng
e163168aab
Code clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104173 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 22:42:23 +00:00
Devang Patel
461a646a03
Revert r104165.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:58:28 +00:00
Jakob Stoklund Olesen
d32e735ae6
Add support for partial redefs to the fast register allocator.
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A partial redef now triggers a reload if required. Also don't add
<imp-def,dead> operands for physical superregisters.
Kill flags are still treated as full register kills, and <imp-use,kill> operands
are added for physical superregisters as before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:36:05 +00:00
Devang Patel
f4ccaeaef9
There is no need to maintain InsnsBeginScopeSet separately.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104165 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:26:53 +00:00
Jakob Stoklund Olesen
7ebc4d63db
Add MachineInstr::readsVirtualRegister() in preparation for proper handling of
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partial redefines.
We are going to treat a partial redefine of a virtual register as a
read-modify-write:
%reg1024:6 = OP
Unless the register is fully clobbered:
%reg1024:6 = OP, %reg1024<imp-def>
MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:36:22 +00:00
Evan Cheng
211ffa1351
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:19:50 +00:00
Jakob Stoklund Olesen
3437352887
TwoAddressInstructionPass doesn't really know how to merge live intervals when
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lowering REG_SEQUENCE instructions.
Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104146 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:08:00 +00:00
Bob Wilson
14b2141497
When expanding a vector_shuffle, the element type may not be legal and may
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need to be promoted. The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion. This fixes part of pr7167.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104141 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 18:48:32 +00:00
Evan Cheng
0a942dbb1e
Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
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The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.
Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 01:08:17 +00:00
Bob Wilson
417d1705bb
Fix a crash when debugging the coalescer. DebugValue instructions are not
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in the coalescer's instruction map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104086 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 23:19:42 +00:00
Jakob Stoklund Olesen
dcf7708ad9
Remember to update VirtRegLastUse when spilling without killing before a call.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 22:20:09 +00:00
Evan Cheng
28dad2a5ca
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:31:17 +00:00
Jakob Stoklund Olesen
0eeb05c969
Properly handle multiple definitions of a virtual register in the same
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instruction.
This can happen on ARM:
>> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0
Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031*
Killing last use: %reg1028
Allocating %reg1035 from QPR
Assigning %reg1035 to Q1
<< %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:10:50 +00:00
Evan Cheng
5012f9b825
Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104051 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 20:07:47 +00:00
Evan Cheng
27e4840e03
Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 20:03:28 +00:00
Jakob Stoklund Olesen
6a8d2c6119
Teach the machine code verifier to use getSubRegisterRegClass().
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The old approach was wrong. It had an off-by-one error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104034 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:31:12 +00:00
Daniel Dunbar
3538c808f8
llc (et al): Add support for --show-encoding and --show-inst.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:22:19 +00:00
Evan Cheng
a083988c8a
FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104004 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 00:03:40 +00:00
Evan Cheng
c6dcce3ba5
Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 23:24:12 +00:00
Bill Wendling
53f7602b61
- Set the "HasCalls" flag after instruction selection is finished.
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- Change the logic DisableFramePointerElim() to check for the
-disable-non-leaf-fp-elim before -disable-fp-elim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 23:09:50 +00:00
Eric Christopher
c6177a4531
More data/parsing support for tls directives. Add a few more testcases
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and cleanup comments as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 22:53:55 +00:00
Evan Cheng
44bfdd3d78
Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 22:09:49 +00:00
Jakob Stoklund Olesen
b8acb7be80
Pull the UsedInInstr.test() calls into calcSpillCost() and remember aliases.
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This fixes the miscompilations of MultiSource/Applications/JM/l{en,de}cod.
Clang now successfully self hosts in a debug build with the fast register allocator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103975 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 21:02:08 +00:00
Eric Christopher
423c9e3e58
Add some section and constant support for darwin TLS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 21:02:07 +00:00
Evan Cheng
53c779bb3a
Careful with reg_sequence coalescing to not to overwrite sub-register indices.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103971 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 20:57:12 +00:00
Jakob Stoklund Olesen
2997985b4c
Remove debug option. Add comment on spill order determinism.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103961 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 20:01:22 +00:00
Jakob Stoklund Olesen
aa4b0159da
Avoid allocating the same physreg to multiple virtregs in one instruction.
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While that approach works wonders for register pressure, it tends to break
everything.
This should unbreak the arm-linux builder and fix a number of miscompilations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 17:18:59 +00:00