Daniel Dunbar
32f0cdba30
Revert "reimplement the second half of the or/add optimization. We should now",
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which depends on r116007, which I am about to revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 02:07:26 +00:00
Eric Christopher
7a56f33583
Move to thumb2 loads, fixes a problem with incoming registers
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as thumb1.
Fixes lencod.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116027 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 01:13:17 +00:00
Chris Lattner
cd3167b281
reimplement the second half of the or/add optimization. We should now
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only end up emitting LEA instead of OR. If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.
Add some testcases that we emit "or" in cases where we used to produce
an "add".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 01:05:10 +00:00
Jim Grosbach
58f38bfa24
Enable binary encoding of some simple instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116022 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:39:21 +00:00
Jim Grosbach
bade37bb8b
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:21:28 +00:00
Chris Lattner
05e27c5786
Use the new TB_NOT_REVERSABLE flag instead of special
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casing FsMOVAPDrr/FsMOVAPSrr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116016 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:03:02 +00:00
Chris Lattner
a228376185
simplify some map operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116014 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:57:02 +00:00
Chris Lattner
122e2ea043
Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'
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is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies. However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).
While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA. This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.
This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20
the add r/i cases are coming next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116007 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:36:18 +00:00
Evan Cheng
344d9db970
Code refactoring.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116002 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:12:15 +00:00
Chris Lattner
45a1cb26a3
Reduce casting in various tables by defining the table
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with the right types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:08:41 +00:00
Chris Lattner
afcd543a55
simplify code: don't build up vector only to assert it is empty.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 22:26:19 +00:00
Owen Anderson
ce665bd2e2
Now with fewer extraneous semicolons!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 22:25:06 +00:00
Jim Grosbach
d6d4b42ba4
Trivial MC code emitter shell. No instruction forms actually handled yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115993 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 22:12:50 +00:00
Jim Grosbach
9af82ba42b
Include the auto-generated bits for machine encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 21:57:55 +00:00
Eric Christopher
df1f5a924e
Remember to promote load/store types for stack to register size.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 21:40:18 +00:00
Chris Lattner
9649e9acdd
convert test to use the existing classes that the multipatterns
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use. Since TEST is completely different than all other binops,
don't define a multipattern for it.
This completes factorization of binops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 21:31:03 +00:00
Chris Lattner
00e94baf4e
convert cmp to use a multipattern
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:56:25 +00:00
Evan Cheng
835580fc3a
Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:50:20 +00:00
Jim Grosbach
ae93ed1dd7
ARM instruction don't have instruction prefixes, so remove the helper functions
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for them from the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115975 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:41:30 +00:00
Chris Lattner
9e94000c16
reduce redundancy between pattern copies.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115968 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:14:23 +00:00
Chris Lattner
a2b8b16c7e
the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115967 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:06:24 +00:00
Owen Anderson
154c5c46fc
Improve comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115966 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:05:18 +00:00
Chris Lattner
a3208e122c
convert adc/sbb to a multipattern. Because the adde/sube nodes
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are not defined as returning EFLAGS (like add_flag and friends),
the entire multipattern and several of the subclasses need to be
cloned.
This could be handled through better instantiation support in tblgen,
but it isn't meta enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:01:55 +00:00
Owen Anderson
9966306aa7
Add initialization routines for Target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115957 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 18:50:11 +00:00
Jakob Stoklund Olesen
8456c4f957
Fix obvious mistake pointed out by Michael Spencer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 18:47:10 +00:00
Kalle Raiskila
218c98c284
Add the missing cases to the type->registerclass conversion function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115921 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 16:32:42 +00:00
Kalle Raiskila
8a52fa674b
Implement two virtual functions in SPUTargetLowering.
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Before the implementation of isLegalAddressingMode, some rare cases
of code were miscompiled if optimized with the LoopStrengthReduce pass.
It is unclear (to me) if LSR is "allowed" to produce wrong code with a
bad TargetLowering, or if the bug is elsewhere and this patch just
hides it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 16:24:35 +00:00
Eric Christopher
ee56ea6243
Use the correct register class for load instructions - fixes
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compilation of MultiSource/Benchmarks/Bullet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115907 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:50:44 +00:00
Eric Christopher
5d18d92aad
Use the correct register class here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:39:19 +00:00
Eric Christopher
338c253d7e
Use the thumb2 conditional move instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115905 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:31:49 +00:00
Eric Christopher
1107734e22
Remove in-progress assertion, add TODO.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:14:08 +00:00
Evan Cheng
5a50ceeaea
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:50:48 +00:00
Chris Lattner
b046810fe4
add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,
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allowing us to convert ADD over. deletes 160 lines of .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:37:01 +00:00
Chris Lattner
521ff704a1
Fix a few issues in ArithBinOpEFLAGS that made it specific to and.
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Start using ArithBinOpEFLAGS for OR, XOR, and SUB.
This removes 500 lines from the .td file. Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:26:27 +00:00
Chris Lattner
4b181c87de
Convert 'and' to single instance of a multipattern
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which instantiates the 34 versions of and all in one
swoop. The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.
No change in the generated .inc files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:10:20 +00:00
Jim Grosbach
a4257162be
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:53:56 +00:00
Chris Lattner
511c686f76
add a new BinOpAI class to represent the immediate form that directly acts on EAX.
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This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115885 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:43:39 +00:00
Jim Grosbach
3bbdcea49a
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115884 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:42:42 +00:00
Chris Lattner
1bb9adae4c
add a bunch of classes for other common patterns.
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As usual, no change in generated .inc files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115882 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:35:28 +00:00
Chris Lattner
2b8d30d080
Define a new BinOpRI8 class and use it to define the imm8 versions of and.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:12:45 +00:00
Jakob Stoklund Olesen
635127a8c6
Constrain the offset register to a *_NOSP register class when inserting LEA
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instructions.
This unbreaks the machine code verifier and fixes PR8317.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:07:26 +00:00
Chris Lattner
78266110bf
add the pattern operator to match to X86TypeInfo, use this to
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convert AND64ri32 to use BinOpRI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:01:39 +00:00
Jakob Stoklund Olesen
8f42a19fb0
Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass.
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This function looks like it is about ready to be generated by TebleGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 23:56:46 +00:00
Jim Grosbach
fa7fb64fad
remove trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 22:46:47 +00:00
Jason W Kim
def9ac48b7
First in a sequence of ARM/MC/*ELF* specific work.
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Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 22:36:46 +00:00
Jim Grosbach
3c38f96af2
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115853 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 22:01:26 +00:00
Jim Grosbach
1d6111c5ac
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 21:36:43 +00:00
Jim Grosbach
35636281c7
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
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"lane" operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 21:22:32 +00:00
Jim Grosbach
65dc30340c
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
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pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115840 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 21:16:16 +00:00
Jim Grosbach
7cd2729d2a
Add a 'pattern' arg to the ARM PseudoNeonI class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 20:36:55 +00:00