Chris Lattner
9ee4aed3b6
implement support for finit, PR8258
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115156 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 16:42:53 +00:00
Chris Lattner
0bb83a84d4
add support for fstcw, PR8259
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115154 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 16:39:29 +00:00
Kevin Enderby
8ebf66236e
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
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for the dwarf .loc support to emit dwarf line number tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115153 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 16:38:07 +00:00
Jim Grosbach
2f24c4ece0
80 column fix
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 15:25:22 +00:00
Jason W Kim
a4c27248b5
Fix two tiny issues (ARM does not need COFF) and comment sanity.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 14:58:19 +00:00
Jim Grosbach
f73fd7278f
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115136 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 03:21:00 +00:00
Jim Grosbach
87dc3aa2d8
Remove misplaced ';'. Make buildbots happy, hopefully.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115135 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 03:20:34 +00:00
Rafael Espindola
a8c02c3bdd
Correctly produce R_X86_64_32 or R_X86_64_32S.
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With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 03:11:42 +00:00
Jason W Kim
afd1cc2578
Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
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Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115133 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 02:45:56 +00:00
Jim Grosbach
7ebc863c15
Go ahead and jump!
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Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 02:18:06 +00:00
Jason W Kim
d4d4f4f488
I added a new file ARMAsmBackend which stubs out in similar ways to
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the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)
Tested against -r115126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115129 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 02:17:26 +00:00
Jim Grosbach
a4e97de71d
Now that the pseudos that needed this are all custom lowered, we can go back
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to an empty PrintSpecial()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115128 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 02:02:22 +00:00
Jim Grosbach
2317e40539
Nuke it from orbit. It's the only way to be sure.
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(Kill the dead non-MC asm printer for the ARM target.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115127 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 01:57:53 +00:00
Evan Cheng
0e55fd61ae
ARM instruction itinerary fixes:
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1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 01:08:25 +00:00
Benjamin Kramer
9510a2538b
Add constant folding for strspn and strcspn to SimplifyLibCalls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115116 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 00:58:35 +00:00
Eric Christopher
a9a7a1a9a5
Refactor arm fast isel libcall handling so that pieces can be used
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for generic call handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115105 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 23:11:09 +00:00
Eric Christopher
e487b017e9
Noticed by inspection when looking for other cmov bits.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115100 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 23:00:29 +00:00
Evan Cheng
3881cb7a5d
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
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pipeline forwarding path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 22:42:35 +00:00
Eric Christopher
8cf6c60710
Add a convenience variable so I'm not chasing all over looking for
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a context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 22:24:45 +00:00
Jim Grosbach
828916203a
Add specializations of addrmode2 that allow differentiating those forms
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which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 19:03:54 +00:00
Nick Lewycky
8892b033e4
Add parens to fix GCC warning:
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lib/Target/X86/X86MCCodeEmitter.cpp: 190: error: suggest parentheses around '&&' within '||'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 18:56:57 +00:00
Chris Lattner
a25f933396
implement rdar://8491845 - Gas supports commuted forms of non-commutable instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115061 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 18:39:16 +00:00
Bob Wilson
7122ba7efb
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
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LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 17:54:10 +00:00
Jim Grosbach
be91232900
Add braces for legibility.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115043 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 17:32:29 +00:00
Jim Grosbach
b454cdaebc
One Printer to rule them all, One Printer to find them,
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One Printer to lower them all and in the back end bind them.
(Remove option to use the old non-MC asm printer.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115038 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 15:23:40 +00:00
Gabor Greif
05642a3eba
improve heuristics to find the 'and' corresponding to 'tst' to also catch opportunities on thumb2
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added some doxygen on the way
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115033 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 10:12:08 +00:00
Chris Lattner
6f42027263
fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 05:05:03 +00:00
Chris Lattner
f3654db458
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115027 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 04:55:40 +00:00
Chris Lattner
78a194693b
make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same
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order as cctools for diffability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115022 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 03:43:43 +00:00
Chris Lattner
8a5072903e
implement support for 32-bit address operands in 64-bit mode, which
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are defined to emit the 0x67 prefix byte. rdar://8482675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 03:33:25 +00:00
Chris Lattner
b2ef4c1235
add basic avx support to the disassembler, also teach it about ssmem/sdmem
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operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115019 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 02:57:56 +00:00
Chris Lattner
bf6018ac5a
add asmparser support for cvttpd2dq by removing some Int_ prefixes.
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Clean up cvttps2dq by removing some redundant implementations of the
same instruction. rdar://8456382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 02:36:32 +00:00
Chris Lattner
0c04e4f58f
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115017 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 02:24:57 +00:00
Chris Lattner
7c51a3172c
implement rdar://8456378 and PR7557 - support for the fstsw,
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an instruction that requires a WHOLE NEW wonderful kind of alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115015 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 01:50:45 +00:00
Chris Lattner
7036f8be4d
change the protocol TargetAsmPArser::MatchInstruction method to take an
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MCStreamer to emit into instead of an MCInst to fill in. This allows the
matcher extra flexibility and is more convenient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115014 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 01:42:58 +00:00
Eric Christopher
229207aa2e
Rework comparison handling to set a register on true/false. This avoids
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problems with phi-nodes in blocks that have hard and not virtual registers.
Accordingly update branch handling to compensate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115013 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 01:14:47 +00:00
Eric Christopher
f8476e6742
Remove unnecessary set ahead of time.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115011 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 00:50:57 +00:00
Evan Cheng
5d42c567c9
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115010 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 00:49:25 +00:00
Eric Christopher
98de5b4603
Remove assert, add comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115009 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 00:49:09 +00:00
Evan Cheng
7e1bf305cf
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 00:27:46 +00:00
Evan Cheng
63d66eed16
Add support to model pipeline bypass / forwarding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 23:50:49 +00:00
Eric Christopher
744c7c8e1b
32-bit constant ints only for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 22:47:54 +00:00
Oscar Fuentes
3609eb0de2
Removed a bunch of unnecessary target_link_libraries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114999 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 22:39:14 +00:00
Owen Anderson
654d5440a4
Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
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cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.
Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114995 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 21:57:50 +00:00
Eric Christopher
fd60980eb2
Integer materialization needed the same thinko change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 21:55:34 +00:00
Nick Lewycky
a6136b7156
Resolve this GCC warning:
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ARMTargetMachine.cpp:53: error: control reaches end of non-void function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114992 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 21:40:26 +00:00
Anton Korobeynikov
4f922f2cca
User proper libcall names & condcodes while compiling for ARM EABI.
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Patch by Evzen Muller!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 21:39:26 +00:00
Owen Anderson
b20b85168c
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
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Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114973 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 18:32:13 +00:00
Jim Grosbach
2d0f53bd63
Factor out dbg_value comment printing and teach MC asm printing to use it.
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This should make the arm-linux self-host buildbot happy again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 17:05:56 +00:00
Oscar Fuentes
c577c271b1
Use the canonical library name for library PIC16Passes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114953 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 14:24:47 +00:00
Oscar Fuentes
4dbb2dbf76
Added library LLVMPIC16passes to CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 14:02:45 +00:00
Oscar Fuentes
38e1390c29
Add ARM Disassembler to the CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114949 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 11:48:19 +00:00
Che-Liang Chiou
acf1d482bf
Remove trailing spaces of MipsMachineFunction.h
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114948 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 10:06:53 +00:00
Che-Liang Chiou
36919ac8a5
Remove trailing spaces of MipsTargetObjectFile.cpp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 09:55:24 +00:00
Eric Christopher
a99c3e9acd
80-col fixups.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 04:18:29 +00:00
Bob Wilson
02aba73a9e
Add a command line option "-arm-strict-align" to disallow unaligned memory
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accesses for ARM targets that would otherwise allow it. Radar 8465431.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 04:09:35 +00:00
Eric Christopher
7ed8ec94d9
Rework builtin handling and call setup. The builtin handling
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now takes a libcall operand, sets up the arguments correctly and
handles stack adjustments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 01:21:42 +00:00
Eric Christopher
5371cabfc2
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114931 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 00:35:33 +00:00
Eric Christopher
f5732c4ee5
Fix fp constant loads to have a destination register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 00:35:09 +00:00
Jim Grosbach
385cc5eede
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
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enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 22:28:11 +00:00
Jim Grosbach
5acb3de8b7
ARM-mode eh.sjlj.longjmp MC lowering
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 21:47:04 +00:00
Jim Grosbach
376ce97bac
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
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enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 21:28:44 +00:00
Daniel Dunbar
3b9569e70d
Hard to imagine there are still people using inferior compilers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 20:12:58 +00:00
Rafael Espindola
fd9493d74e
Odd additional stub framework for the ARM MC ELF emission.
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llc now recognizes the "intent" to support MC/obj emission for ARM, but
given that they are all stubs, it asserts on --filetype=obj --march=arm
Patch by Jason Kim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114856 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 18:31:37 +00:00
Dale Johannesen
a8bd1ff8c5
MMX parameters aren't handled here yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114844 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 17:29:47 +00:00
Chris Lattner
2956462742
yet more aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114822 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 07:24:57 +00:00
Chris Lattner
b1162fc05e
add a couple more aliases, rdar://8456378
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114821 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 07:21:41 +00:00
Chris Lattner
df967d6137
fix rdar://8470918 - llvm-mc can't assemble smovl
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 07:11:53 +00:00
Chris Lattner
cb296ec0b6
Fix rdar://8468087 - llvm-mc commutes fmul (and friend) operands.
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My previous fix for rdar://8456371 should only apply to fmulp/faddp,
not to fmul/fadd. Instruction set orthogonality is overrated or
something.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114818 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 07:08:21 +00:00
Chris Lattner
8048ebe91d
the latest assembler that runs on powerpc 10.4 machines doesn't
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support aligned comm. Detect when compiling for 10.4 and don't
emit an alignment for comm. THis will hopefully fix PR8198.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114817 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 06:44:54 +00:00
Chris Lattner
80945784f9
improve indentation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 06:34:01 +00:00
Eric Christopher
1127c720ed
Insert missing coherency in comment. Add a quick check for hardware
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divide support also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114813 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 06:08:12 +00:00
Eric Christopher
43b62beb4c
Mass rename for Jim.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114812 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 06:02:23 +00:00
Eric Christopher
722d315ac9
This code should never fire on non-darwin subtargets.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114811 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 06:01:51 +00:00
Chris Lattner
fd8fddd830
implement support for 'clr' alias. This is part of rdar://8416805,
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but balrog was wanting it on irc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 04:23:03 +00:00
Che-Liang Chiou
f9930da2ef
Add ret instruction to PTX backend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 07:46:17 +00:00
Rafael Espindola
73ffea47d2
Move ELF to HasReliableSymbolDifference=true. Also take the opportunity to put
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symbols defined in merge sections in independent atoms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114786 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 05:42:19 +00:00
Evan Cheng
5981fc6788
Fix IIC_iEXTAr itinerary class of Cortex-A9.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 01:09:28 +00:00
Evan Cheng
27fdcd1c95
Remove a unused instruction itinerary class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114782 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 01:06:02 +00:00
Evan Cheng
576a3968a2
Fix zero and sign extension instructions scheduling itineraries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114780 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 00:49:35 +00:00
Evan Cheng
bd30ce4311
More pseudo instruction scheduling itinerary fixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114768 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 22:41:41 +00:00
Evan Cheng
5be3922321
Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114766 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 22:03:46 +00:00
Jim Grosbach
433a5785cc
Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114758 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 20:47:58 +00:00
Evan Cheng
fff606d7b2
Enable code placement optimization pass for ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 19:07:23 +00:00
Dale Johannesen
c451051157
We can't return SSE/MMX vectors if SSE is disabled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 19:05:48 +00:00
Evan Cheng
de0e11c8f3
Fix a potential null dereference bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114723 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 05:18:35 +00:00
Owen Anderson
f523e476c2
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
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reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:45:25 +00:00
Bob Wilson
2a6e616142
Set alignment operand for NEON VST instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:42:37 +00:00
Jim Grosbach
453900814e
ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:33:56 +00:00
Jim Grosbach
b327e13740
#+4 --> #4 for consistency with other asm output
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114706 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:32:38 +00:00
Jim Grosbach
45d6c1777c
Fix formatting of output .s code
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114705 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:03:26 +00:00
Owen Anderson
71e416ac3a
Add isConditionalMove bits to X86 and ARM instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114703 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 22:57:01 +00:00
Bob Wilson
40ff01a030
Set alignment operand for NEON VLD instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 21:43:54 +00:00
Jim Grosbach
b2dda4bd34
never mind. I can't read, apparently
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114689 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 19:42:17 +00:00
Evan Cheng
676e258366
Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 19:42:03 +00:00
Jim Grosbach
24e6f2f802
Fix opcode value for the 'trap' instruction, keeping the type suffix on the
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constant. Hopefully the non-Darwin bots will like it...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 19:32:40 +00:00
Jim Grosbach
5c49b69609
explicit 'unsigned long' on constant value. Hopefully make bots happier.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114686 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 19:08:04 +00:00
Benjamin Kramer
c8ab9eb066
Unbreak build. Jim, please review.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114684 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 18:57:26 +00:00
Jim Grosbach
2e6ae13bf6
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
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(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.
Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114679 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 18:05:37 +00:00
Jim Grosbach
16c9a64c28
nuke unused var
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114676 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 17:58:00 +00:00
Evan Cheng
108c872466
If there are multiple unconditional branches terminating a block, eliminate all
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but the first one. Those will never be executed. There was logic to do this
but it was faulty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114632 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 06:54:40 +00:00
Jim Grosbach
637d89fe0e
Add support for ELF PLT references for ARM MC asm printing. Adding a
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new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure
there's a more straightforward way to get the printing difference captured.
(i.e., x86 uses @PLT, ARM uses (PLT)).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114613 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 23:27:36 +00:00
Jim Grosbach
b6ec8cae3c
Enable a few additional asserts in MC instruction lowering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 23:01:28 +00:00
Cameron Esfahani
4af1eaee70
Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 22:35:21 +00:00
Bob Wilson
b68987e4bf
Change VDUPLANE DAG combiner to just return the result instead of calling
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CombineTo to avoid putting the result on the worklist. I don't think it makes
much difference for now, but it might help someday as we add more DAG
combine optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114595 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 22:27:30 +00:00
Bob Wilson
0b8ccb8252
Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing one
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of those. Refactor to share code for handling BUILD_VECTOR(VMOVRRD).
I don't have a testcase that exercises this, but it seems like an obvious
good thing to do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114589 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 22:09:21 +00:00
Jim Grosbach
f0633e48eb
add FIXME
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114578 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 20:55:15 +00:00
Eric Christopher
56a8b817b1
Temporarily work around new address lowering while I figure out what
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needs to happen for darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114577 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 20:42:08 +00:00
Jim Grosbach
bfbe187593
Remove a few commented out bits
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 20:32:34 +00:00
Jim Grosbach
00d01f1a42
Add PrintSpecial() handling for in ARM MC instruction printer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 18:37:14 +00:00
Jim Grosbach
a2244cb387
Add MC instruction printer support for ARM and Thumb1 jump tables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114555 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 17:39:48 +00:00
Bob Wilson
eafca4e2b2
Attempt to fix llvm-gcc build. It was crashing when building gcov.o for an
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ARM cross-compiler on x86, because the MMO size did not match the type size.
This fixes the MMO size and also the size of the stack object to match the
type size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114554 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 17:35:14 +00:00
Jim Grosbach
205a5fa8e4
Add MC instruction printer support for TB[BH] style thumb2 jump tables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114553 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 17:15:35 +00:00
Jim Grosbach
1b935a3d2e
Clean up comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114550 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 16:45:13 +00:00
Chris Lattner
2c5291b563
fix rdar://8456371 - Handle commutable instructions written backward.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114536 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 06:26:39 +00:00
Chris Lattner
1eb1b68e3a
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
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x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly
named "callq", so this only impacted x86-32.
This fixes rdar://8456370 - llvm-mc rejects 'calll'
This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 05:49:14 +00:00
Chris Lattner
bc57c6db4a
fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"
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Teaching the code generator about CR8-15, how to rex them up, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114533 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 05:29:50 +00:00
Chris Lattner
c2b942acf6
add the missing aliases for fp stack cmovs, rdar://8456391
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:56:20 +00:00
Chris Lattner
f93b90c5df
reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:39:11 +00:00
Chris Lattner
33d60d5e56
Fix rdar://8456364 - llvm-mc rejects '%CS'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114528 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:11:10 +00:00
Chris Lattner
0c289c140e
fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp'
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-This line, and those below, will be ignored--
M test/MC/AsmParser/X86/x86_instructions.s
M lib/Target/X86/AsmParser/X86AsmParser.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114527 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:04:03 +00:00
Chris Lattner
61129252e4
fix rdar://8456361 - llvm-mc rejects 'rep movsd'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114526 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 03:50:32 +00:00
Chris Lattner
492a43e6f6
convert the last 4 X86ISD nodes that should have memoperands to have them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 01:28:21 +00:00
Chris Lattner
2156b79c49
give X86ISD::FNSTCW16m a memoperand, since it touches memory. It only
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can access the stack due to how it is generated though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114522 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 01:11:26 +00:00
Chris Lattner
0729093cd7
give FP_TO_INT16_IN_MEM and friends a memoperand. They are only
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used with stack slots, but hey, lets be safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 01:05:16 +00:00
Chris Lattner
8864155a35
give VZEXT_LOAD a memory operand, it now works with segment registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 00:34:38 +00:00
Chris Lattner
0b79cfee15
revert r114386 now that address modes work correctly, we get a nice
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call through gs-relative memory now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114510 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 00:11:31 +00:00
Chris Lattner
93c4a5bef7
give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:59:42 +00:00
Evan Cheng
691e64a54c
OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:49:07 +00:00
Jim Grosbach
882ef2b76a
Add start of support for MC instruction printer of ARM jump tables. Filling in
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the rest of it is next up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114500 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:28:16 +00:00
Owen Anderson
8614167572
Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes
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irrelevant, but add a new test for the new, improved functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 22:51:46 +00:00
Chris Lattner
b86faa17a4
reimplement support for GS and FS relative address space matching
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by having X86DAGToDAGISel::SelectAddr get passed in the parent node
of the operand match (the load/store/atomic op) and having it get
the address space from that, instead of having special FS/GS addr
mode operations that require duplicating the entire instruction set
to support.
This makes FS and GS relative accesses *far* more predictable and
work much better. It also simplifies the X86 backend a bit, more
to come.
There is still a pending issue with nodes like ISD::PREFETCH and
X86ISD::FLD, which really should be MemSDNode's but aren't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114491 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 22:07:31 +00:00
Owen Anderson
bc146b0a4d
Reimplement r114460 in target-independent DAGCombine rather than target-dependent, by using
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the predicate to discover the number of sign bits. Enhance X86's target lowering to provide
a useful response to this query.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 20:42:50 +00:00
Chris Lattner
52a261b3c1
fix a long standing wart: all the ComplexPattern's were being
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passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 20:31:19 +00:00
Chris Lattner
701cd62297
even though I'm about to rip it out, simplify the address mode stuff
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114468 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 19:41:58 +00:00
Chris Lattner
fc448ff89b
convert a couple more places to use the new getStore()
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 18:51:21 +00:00
Chris Lattner
6229d0acb8
update a bunch of code to use the MachinePointerInfo version of getStore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 18:41:36 +00:00
Owen Anderson
c004eec71b
When adding the carry bit to another value on X86, exploit the fact that the carry-materialization
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(sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.
This fixes <rdar://problem/8449754>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 18:41:19 +00:00
Bob Wilson
65ffec49f7
Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load
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and store intrinsics are represented with MemIntrinsicSDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 17:56:22 +00:00
Chris Lattner
8026a9d3ee
eliminate some uses of the getStore overload.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 17:50:43 +00:00
Chris Lattner
da2d8e1032
eliminate an old SelectionDAG::getTruncStore method, propagating
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MachinePointerInfo around more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114452 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 17:42:31 +00:00
Chris Lattner
3d6ccfba31
propagate MachinePointerInfo through various uses of the old
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SelectionDAG::getExtLoad overload, and eliminate it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114446 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 17:04:51 +00:00
Jim Grosbach
532baa5d53
Fix errant printing of [v]ldm instructions that aren't a pop
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114445 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 16:45:31 +00:00
Gabor Greif
8ff9bb189c
Fix buglet when the TST instruction directly uses the AND result.
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I am unable to write a test for this case, help is solicited, though...
What I did is to tickle the code in the debugger and verify that we do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114430 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 13:30:57 +00:00
Gabor Greif
04ac81d5db
Move the search for the appropriate AND instruction
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into OptimizeCompareInstr.
This necessitates the passing of CmpValue around,
so widen the virtual functions to accomodate.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114428 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 12:01:15 +00:00
Chris Lattner
d1c24ed81c
convert the targets off the non-MachinePointerInfo of getLoad.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 06:44:06 +00:00
Chris Lattner
e8639036b1
it's more elegant to put the "getConstantPool" and
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"getFixedStack" on the MachinePointerInfo class. While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114406 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 06:22:23 +00:00
Chris Lattner
51abfe490b
update the X86 backend to use the MachinePointerInfo version of one
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of the getLoad methods. This fixes at least one bug where an incorrect
svoffset is passed in (a potential combiner-aa miscompile).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 06:02:19 +00:00
Chris Lattner
e54b482d1c
Fix a bug where the x86 backend would lower memcpy/memset of segment relative operations
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into non-segment-relative copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114402 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 05:43:34 +00:00
Chris Lattner
e72f2027e9
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
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instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 05:40:29 +00:00
Chris Lattner
59db5496f4
convert targets to the new MF.getMachineMemOperand interface.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 04:39:43 +00:00
Chris Lattner
08bad54baf
fix rdar://8453210, a crash handling a call through a GS relative load.
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For now, just disable folding the load into the call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114386 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 03:37:00 +00:00
Jim Grosbach
1dc335a79f
Simplify ARM callee-saved register handling by removing the distinction
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between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.
For example, previously we would generate code like:
push {r4, r5, r6, r7, lr}
add r7, sp, #12
stmdb sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
push {r4, r5, r6, r7, r8, r10, r11, lr}
add r7, sp, #12
rdar://8445635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 19:32:20 +00:00
Chris Lattner
313a94c3d0
idiom recognition should catch this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114304 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-19 00:37:34 +00:00
Chris Lattner
702917d4e8
add a readme.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114303 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-19 00:34:58 +00:00
NAKAMURA Takumi
cd458be047
X86Subtarget.h: Fix Cygwin's TD.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114297 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 19:50:42 +00:00
Eric Christopher
50880d08ec
Add the exit instruction to the PTX target.
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Patch by Che-Liang Chiou <clchiou@gmail.com>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114294 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 18:52:28 +00:00
Michael J. Spencer
895dda6fb5
Fix build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114292 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 17:54:37 +00:00
Eric Christopher
c109556a0a
Thumb opcodes for thumb calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114263 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 02:32:38 +00:00
Eric Christopher
6dab137b88
Add addrmode5 fp load support. Swap float/thumb operand adding to handle
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thumb with floating point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114256 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 01:59:37 +00:00
Eric Christopher
b74558ad3e
Floating point stores have a 3rd addressing mode type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114254 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 01:23:38 +00:00
Jim Grosbach
988ce097b7
factor out a simple helper function to create a label for PC-relative
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instructions (PICADD, PICLDR, et.al.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 00:05:05 +00:00
Jim Grosbach
d30cfde935
PC-relative pseudo instructions are lowered and printed directly. Any encounter
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with one in the generic printing code is an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114242 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 00:04:53 +00:00
Benjamin Kramer
92aa1f7123
Fix vmov.f64 disassembly on targets where sizeof(long) != 8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 23:48:07 +00:00
Jim Grosbach
fbd1873041
Add MC-inst handling for tPICADD
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114237 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 23:41:53 +00:00
Bob Wilson
75f0288b7d
Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64
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value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert. Radar 8407927.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:59:05 +00:00
Jim Grosbach
e6be85e9ff
Teach the (non-MC) instruction printer to use the cannonical names for push/pop,
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and shift instructions on ARM. Update the tests to match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:36:38 +00:00
Eric Christopher
a5b1e68107
Rework arm fast isel branch and compare code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:28:18 +00:00
Jim Grosbach
74d7e6c64e
Hook up verbose asm comment printing for SOImm operands in MC printer
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114215 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:33:25 +00:00
Jim Grosbach
196b48b708
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114212 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:25:10 +00:00
Dan Gohman
d8c0a51362
Avoid emitting a PIC base register if no PIC addresses are needed.
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This fixes rdar://8396318.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:24:24 +00:00
Jim Grosbach
568eeedea7
Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:46:17 +00:00
Jim Grosbach
c686e33d12
handle the upper16/lower16 target operand flags on symbol references for MC
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instruction lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114191 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:25:25 +00:00
Chris Lattner
40cc3f8783
fix rdar://8444631 - encoder crash on 'enter'
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What a weird instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114190 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:02:29 +00:00
Jim Grosbach
a28abbe245
expand PICLDR MC lowering to handle other PICLDR and PICSTR versions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 16:25:52 +00:00
NAKAMURA Takumi
cdd7fb7853
AlphaSchedule.td: 7bit-ize.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114173 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 09:56:43 +00:00
Chris Lattner
35aa94b229
fix rdar://8438816 - unrecognized 'fildq' instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114116 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 20:46:38 +00:00
Jim Grosbach
b74ca9d631
MC-ization of the PICLDR pseudo. Next up, adding the other variants
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(PICLDRB, et. al.) and PICSTR*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 17:43:25 +00:00
Jim Grosbach
1d51c41a45
Make sure to promote single precision floats to double before extracting them
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from the APFloat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114096 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 17:37:30 +00:00
Kalle Raiskila
1cd1b0b283
Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.
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This cleans up after the mess r108567 left in the CellSPU backend.
ORCvt-instruction were used to reinterpret registers, and the ORs were then
removed by isMoveInstr(). This patch now removes 350 instrucions of format:
or $3, $3, $3
(from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is
checked for.
Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 12:29:33 +00:00
Bob Wilson
de0ae8f83d
Remove support for "dregpair" operand modifier, now that it is no longer being
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used for anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 04:55:00 +00:00
Bob Wilson
823611bfba
When expanding ARM pseudo registers, copy the existing predicate operands
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instead of using default predicates on the expanded instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 04:25:37 +00:00
Jim Grosbach
a8e47b3319
store MC FP immediates as a double instead of as an APFloat, thus avoiding an
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unnecessary dtor for MCOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 03:45:21 +00:00
Bob Wilson
ea606bb76b
Add missing break.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114048 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 00:31:32 +00:00
Bob Wilson
9d4ebc0eb8
Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after
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register allocation to VLDMD and VSTMD respectively. This avoids using the
dregpair operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 00:31:02 +00:00
Jim Grosbach
765c4d9477
Add support for the 'lane' modifier on vdup operands
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 22:13:23 +00:00
Jakob Stoklund Olesen
06f264e504
Remember VLDMQ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 21:40:11 +00:00
Jakob Stoklund Olesen
31bbc51ac9
Add missing break.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114025 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 21:40:09 +00:00
Jim Grosbach
60396975be
Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register
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moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 21:04:54 +00:00
Jim Grosbach
a4c3c8f28d
move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
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functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114016 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 20:26:25 +00:00
Jim Grosbach
f1c3eb37ae
simplify getRegisterNumbering(). Remove the unused isSPVFP argument and
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merge the common cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114013 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:52:17 +00:00
Jim Grosbach
7e2c04fd05
Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. Check
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if the register is a member of the SPR register class directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:44:57 +00:00
Jim Grosbach
d8be410d4b
Reduce dependencies in the ARM MC instruction printer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114009 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:27:50 +00:00
Jim Grosbach
8b7fa198c3
Fix spelling typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:26:50 +00:00
Jim Grosbach
754578b565
Factor out basic enums and hleper functions from ARM.h for cleaner sharing
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between the compiler back end and the MC libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114007 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:26:06 +00:00
Jim Grosbach
26edbcb8d5
Add support for floating point immediates to MC instruction printing. ARM
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VFP instructions use it for loading some constants, so implement that
handling.
Not thrilled with adding a member to MCOperand, but not sure there's much of
a better option that's not pretty fragile (like putting a double in the
union instead and just assuming that's good enough). Suggestions welcome...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 18:47:08 +00:00
Jakob Stoklund Olesen
d64816a8d0
Recognize VST1q64Pseudo and VSTMQ as stack slot stores.
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Recognize VLD1q64Pseudo as a stack slot load.
Reject these if they are loading or storing a subregister. The API (and
VirtRegRewriter) doesn't know how to deal with that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 17:27:09 +00:00
Bob Wilson
3a951829fe
Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem
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encountered while building llvm-gcc for arm. This is probably the same issue
that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator,
not a plain MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113983 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 17:12:08 +00:00
Gabor Greif
7602993f2d
the darwin9-powerpc buildbot keeps consistently crashing,
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backing out following to get it back to green,
so I can investigate in peace:
svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 16:53:07 +00:00
Jakob Stoklund Olesen
34327856d9
Move ARM is{LoadFrom,StoreTo}StackSlot closer to their siblings so they won't be
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forgotten in the future.
Coalesce identical cases in switch.
No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113979 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 16:36:26 +00:00