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14489 Commits

Author SHA1 Message Date
Johnny Chen
785516adc5 Add New NEON Format NVdImmFrm. 
Ref: A7.4.6 One register and a modified immediate value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99288 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 16:43:47 +00:00
Bob Wilson
c289a0252b Rename some instructions to match the corresponding NEON opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 06:26:18 +00:00
Bob Wilson
11d9899759 Change VST1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99265 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 06:20:33 +00:00
Bob Wilson
621f195243 Change VLD1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99261 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 05:25:43 +00:00
Daniel Dunbar
337055e62f MC: Add TargetAsmBackend::MayNeedRelaxation, for checking whether a particular instruction + fixups might need relaxation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99249 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 03:13:05 +00:00
Daniel Dunbar
8f9b80e5df MC: Add TargetAsmBackend::WriteNopData and use to eliminate some target dependencies in MCMachOStreamer and MCAssembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99248 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 02:36:58 +00:00
Daniel Dunbar
829680048c MC: Add TargetAsmBackend::RelaxInstruction callback, and custom X86 implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99245 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 01:39:09 +00:00
Bob Wilson
62ef3c8910 Rename one more NEON instruction that I missed earlier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 20:31:39 +00:00
Bob Wilson
052ba45bf8 Regroup some instructions. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99192 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 18:22:06 +00:00
Bob Wilson
a6979754da Rename some VLD1/VST1 instructions to match the implementation, i.e., the 
corresponding NEON instructions, instead of operation they are currently
used for.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99189 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 18:13:18 +00:00
Bob Wilson
58393bc3fd Remove some redundant instruction classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99187 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 18:02:38 +00:00
Bob Wilson
39842553e8 Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to 
specify encoding bits in arguments instead of "let" expressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99185 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 16:43:10 +00:00
Jakob Stoklund Olesen
e5b8bfa0c5 Completely remove Blackfin patterns that thought JustCC was i1. 
Thanks, Chris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99183 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 16:30:04 +00:00
Jeffrey Yasskin
fa72340ba0 Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 16:13:21 +00:00
Daniel Dunbar
f2de13f8d7 MC/X86: Fix an MCOperand link, when we parsing shrld $1,%eax and friends; I believe this fixes the last memory leaks under test/MC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99102 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 22:36:38 +00:00
Daniel Dunbar
5d067fe158 TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99097 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 22:36:22 +00:00
Bob Wilson
c88d072293 pr6652: Use LDM to restore PC to the return address on ARMv4. 
Patch by John Tytgat!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99096 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 22:20:40 +00:00
Bob Wilson
226036ee73 Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") 
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99095 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 22:13:40 +00:00
Bob Wilson
d5fadaf56e Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with 
address register writeback.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99094 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 21:57:36 +00:00
Bob Wilson
4f4f93f9d6 Add variants of VST2, VST3 and VST4 with address register writeback, and 
rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99093 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 21:45:18 +00:00
Bob Wilson
068b18be0d Add instructions for double-spaced VST3 and VST4 without address register 
writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99090 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 21:15:48 +00:00
Bob Wilson
25eb5013d0 Add VST1 instructions with address register writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99083 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 20:54:36 +00:00
Bob Wilson
a1023645f8 Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with 
address register writeback.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99082 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 20:47:18 +00:00
Bob Wilson
41315282f9 Tidy some more comments and whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99081 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 20:39:53 +00:00
Bob Wilson
92cb9321a1 Add variants of VLD2, VLD3 and VLD4 with address register writeback, and 
rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99080 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 20:10:51 +00:00
Bob Wilson
667a13e1be Tidy some comments and whitespace for consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99078 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 19:57:03 +00:00
Bob Wilson
95ffecd4fe Rename some instructions for consistency and sanity: use "_UPD" suffix for 
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99066 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 18:35:24 +00:00
Bob Wilson
00bf1d93d7 Add instructions for double-spaced VLD3 and VLD4 without address register 
writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99065 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 18:14:26 +00:00
Bob Wilson
99493b2b53 Add VLD1 instructions with address register writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99062 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 17:59:03 +00:00
Benjamin Kramer
dd70cea00c PIC16: Simplify code by using a std::set<std::string> instead of a sorted & uniqued std::list of leaked char*. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99061 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 17:41:18 +00:00
Bob Wilson
55c9cb5a22 Revert the rest of 98679. 
--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U    lib/Target/ARM/ARMInstrVFP.td


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99049 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 06:34:02 +00:00
Bob Wilson
98330ff8e3 Fix a very bad typo. Since the register number was off by one, the ARM 
load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99043 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 06:05:13 +00:00
Evan Cheng
f5b9d6cc82 If call result is in ST0 and it is not being passed to the caller's 
caller, then it is not safe to optimize the call into a sibcall since
the call result has to be popped off the x87 stack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99032 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 02:58:15 +00:00
Johnny Chen
caa608e97c Add NLdStFrm Format. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99014 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 00:17:00 +00:00
Johnny Chen
e86425f224 Revert r98679. The disassembler will be updated to depend on the existence of 
IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99013 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 23:50:27 +00:00
Bob Wilson
76a312b7d1 Revert this change, since it was causing ARM performance regressions. 
--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99010 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 22:51:32 +00:00
Chris Lattner
99521af212 remove the patterns that I commented out in r98930, Dan verified 
that they are dead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99000 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 21:43:36 +00:00
Kevin Enderby
b46b03b36f Fixed the encoding problems of the crc32 instructions. All had the Operand size 
override prefix and only the r/m16 forms should have had that.  Also for variant
one, the AT&T syntax, added suffixes to all forms.  Also added the missing
64-bit form for 'CRC32 r64, r/m8'.  Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98980 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 20:04:42 +00:00
Daniel Dunbar
0180daee02 MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98972 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 18:07:48 +00:00
Johnny Chen
81f04d59f6 Renumber LdStExFrm from 28 to 11 and shift the existing format values to make 
room for it.  This is in preparation for another patch which is adding NEON
subformats to facilitate disassembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98967 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 17:39:00 +00:00
Daniel Dunbar
1a9158c301 MC: Add TargetAsmBackend::createObjectWriter. 
- MCAssembler is now object-file independent, although we will surely need more work to fully support ELF/COFF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98955 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 10:43:26 +00:00
Daniel Dunbar
b36052f0e4 MCCodeEmitter: Add target independent fixup flag for is-pc-relative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98954 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 10:43:23 +00:00
Daniel Dunbar
cc5b84c6fb MC: Add TargetAsmBackend::isVirtualSection hook. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 09:29:03 +00:00
Daniel Dunbar
87190c473c MCAssembler: Move ApplyFixup to the TargetAsmBackend, this is a target specific not object writer specific task. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 09:28:12 +00:00
Jeffrey Yasskin
509bcb134d Remove a memory leak from the CBackend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98941 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 07:06:46 +00:00
Chris Lattner
60e9eac357 set SDNPVariadic on nodes throughout the rest of the targets that 
need them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98937 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 05:33:51 +00:00
Jeffrey Yasskin
c3e45f1ee2 Remove a memory leak from ThumbTargetMachine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98936 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 05:25:28 +00:00
Chris Lattner
e8cabf3c2e add a new SDNPVariadic SDNP node flag, and use it in 
dag isel gen instead of instruction properties.  This
allows the oh-so-useful behavior of matching a variadic
non-root node.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98934 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 05:07:09 +00:00
Chris Lattner
e9eda0f85d remove some damaged sign extend patterns that can never match. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98932 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 04:53:47 +00:00
Chris Lattner
2356ae9179 disable some illegal blackfin patterns. sext from i32 to i32 can never 
match.  Jakob, please take a look when you get a chance.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98931 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 04:53:21 +00:00