Evan Cheng
3a1f0f6785
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78622 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 23:56:04 +00:00
Dan Gohman
a407ca16c2
Fix a bug where DAGCombine was producing an illegal ConstantFP
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node after legalize, and remove the workaround code from the
ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78615 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 23:15:10 +00:00
Owen Anderson
e50ed30282
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 22:56:29 +00:00
David Goodwin
338268c67f
Use NEON for single-precision int<->FP conversions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78604 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 22:17:39 +00:00
Owen Anderson
d6662add68
SimpleValueType-ify a few more methods on TargetLowering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78595 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 20:46:15 +00:00
Evan Cheng
e2b861f7d9
Handle the constantfp created during post-legalization dag combiner phase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78594 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 20:25:59 +00:00
Owen Anderson
70671845ad
Continue the SimpleValueType-ification.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78593 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 20:18:46 +00:00
Chris Lattner
f9bdeddb96
split MachO section handling stuff out to its out .h/.cpp file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78576 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 18:15:01 +00:00
Chris Lattner
f3231de60b
arm only needs to emit one .align directive for hidden nlp's, not one
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per pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78574 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 18:02:16 +00:00
Chris Lattner
c076a97939
make sure that arm nonlazypointers are aligned properly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78573 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 18:01:34 +00:00
David Goodwin
bcf81629b8
Checkpoint scheduling itinerary changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78564 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 15:56:13 +00:00
Evan Cheng
65f2e7887a
Watch out for empty BB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78562 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 08:10:13 +00:00
Evan Cheng
8442d00a0e
rev, rev16, and revsh do not set CPSR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78561 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 07:58:45 +00:00
Evan Cheng
0d3007bb32
Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78560 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 07:20:37 +00:00
Evan Cheng
26cc252a43
CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78559 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 06:57:42 +00:00
Evan Cheng
19068ba71a
Add support for folding loads / stores into 16-bit moves used by Thumb2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78558 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 06:32:05 +00:00
Evan Cheng
2294645642
80 col violation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78557 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 05:51:48 +00:00
Evan Cheng
052053bbe3
Use tMOVgpr2gpr instead of t2MOVr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78556 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 05:49:43 +00:00
Evan Cheng
e8af1f9afe
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78550 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 02:37:24 +00:00
Evan Cheng
09d97354ed
Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78549 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 02:06:53 +00:00
Chris Lattner
ff4bc460c5
Make the big switch: Change MCSectionMachO to represent a section *semantically*
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instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78547 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 01:39:42 +00:00
Evan Cheng
a56c57e5f0
Add support to convert 32-bit instructions to 16-bit non-two-address ones.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78540 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-09 19:17:19 +00:00
Anton Korobeynikov
8e9ece75db
Use subclassing to print lane-like immediates (w/o hash) eliminating
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'no_hash' modifier. Hopefully this will make Daniel happy :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 23:10:41 +00:00
Chris Lattner
892e182393
1. Make MCSection an abstract class.
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2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78510 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 22:41:53 +00:00
Chris Lattner
0c0cb71233
now that getOrCreateSection is all object-file specific,
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give the impls an object-file-specific name. In the future
they can take different arguments etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78495 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 20:22:20 +00:00
Daniel Dunbar
cf1e764a1c
Update CMake
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78475 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 17:03:13 +00:00
Anton Korobeynikov
06af2ba809
Add insert_elt / extract_elt patterns for v4f32 stuff.
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Did anyone tests v4f32 ever?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78470 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 14:06:07 +00:00
Anton Korobeynikov
3405201bce
Lane number should be printed w/o hash
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78469 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 14:05:53 +00:00
Anton Korobeynikov
baf31088f1
Use VLDM / VSTM to spill/reload 128-bit Neon registers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78468 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 13:35:48 +00:00
Bob Wilson
b6ab51e829
Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
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so I generalized the class for VTRN in the .td file to handle all 3 of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78460 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 06:13:25 +00:00
Bob Wilson
64efd90f8c
Implement Neon VTRN instructions. For now, anyway, these are selected
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directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78459 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 05:53:00 +00:00
Evan Cheng
3eff16e27a
Add a skeleton Thumb2 instruction size reduction pass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78456 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 03:21:23 +00:00
Evan Cheng
8fb903604e
Code refactoring. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78455 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 03:20:32 +00:00
Evan Cheng
57834cdee5
tADDhirr should target GPR, not tGPR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78454 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 03:19:44 +00:00
Evan Cheng
34f8a029e3
I can type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78453 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 02:54:37 +00:00
Chris Lattner
41aefdcdd1
make printInstruction return void since its result is omitted. Make the
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error condition get trapped with an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78449 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 01:32:19 +00:00
David Goodwin
767a952a6f
Make NEON single-precision FP support the default for cortex-a8 (again).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78430 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 23:32:33 +00:00
Anton Korobeynikov
a55fd4a23f
Unbreak the stuff
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78425 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 22:51:13 +00:00
Anton Korobeynikov
32a1b25781
2 more vdup.32 cases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78419 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 22:36:50 +00:00
Evan Cheng
fcc716352b
A big oops. Thumb1 default CC is a def of CPSR, not a use of CPSR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78418 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 22:36:37 +00:00
Evan Cheng
d77c7aba83
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78410 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 21:19:10 +00:00
Evan Cheng
f12288e8aa
This is done.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78399 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 19:34:52 +00:00
Evan Cheng
e118cb6146
Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78398 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 19:34:35 +00:00
Evan Cheng
1d2426c470
Fix support to use NEON for single precision fp math.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78397 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 19:30:41 +00:00
Evan Cheng
b6879b2b84
Error out, rather than infinite looping, if constant island pass can't converge.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78377 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 07:35:21 +00:00
Evan Cheng
53c67c0218
tBfar is bl, which clobbers LR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78370 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 05:45:07 +00:00
Dan Gohman
7db949df78
Fix a bunch of namespace pollution.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78363 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 01:32:21 +00:00
Evan Cheng
861986401e
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
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This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 00:34:42 +00:00
Bob Wilson
b36ec86c01
Implement Neon VST[234] operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78330 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 18:47:44 +00:00
David Goodwin
8b7d7ade85
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78321 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 16:52:47 +00:00