Commit Graph

27466 Commits

Author SHA1 Message Date
Saleem Abdulrasool
d0fb7e49cc ARM ELF: ensure that the tag types are corrected
Ensure that the tag types are reflected on a replacement.  This is particularly
important for the compatibility tag which has multiple representations where the
last definition wins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199577 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-19 08:25:41 +00:00
Saleem Abdulrasool
70c092f3ec ARM: update build attributes for ABI r2.09
Update names for the names as per the current ABI errata.  Mark deprecated tags
as such.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199576 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-19 08:25:35 +00:00
Saleem Abdulrasool
467aa258ae Move ARM build attributes into Support
This moves the ARM build attributes definitions and support routines into the
Support library.  The support routines simply permit the conversion of the value
to and from a string representation.

The movement is prompted in order to permit access to the constants and string
representations from readobj in order to facilitate decoding of the attributes
section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199575 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-19 08:25:27 +00:00
Saleem Abdulrasool
bf329b3414 ARM IAS: remove unnecessary special case
Tag_nodefaults is even and greater than 32 and thus does not need the special
check to fall into the correct category.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199574 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-19 08:25:19 +00:00
Benjamin Kramer
c975958498 ARM: Let the assembler reject v5 instructions in v4 mode.
PR18524.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199559 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-18 19:03:19 +00:00
Juergen Ributzka
ceaf829339 Add two new calling conventions for runtime calls
This patch adds two new target-independent calling conventions for runtime
calls - PreserveMost and PreserveAll.
The target-specific implementation for X86-64 is defined as following:
  - Arguments are passed as for the default C calling convention
  - The same applies for the return value(s)
  - PreserveMost preserves all GPRs - except R11
  - PreserveAll preserves all GPRs and all XMMs/YMMs - except R11

Reviewed by Lang and Philip

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199508 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 19:47:03 +00:00
Daniel Sanders
41e1c04201 [mips][msa] Correct pattern for LSA
Summary:
$rs and $rt were the wrong way round in the .td and the testcase wasn't
strict enough to detect the mistake.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D2554

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199498 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 15:40:05 +00:00
Daniel Sanders
61a2eb1df5 [mips] Split IIIdiv int II_DIV, II_DIVU, II_DDIV, and II_DDIVU
No functional change since the InstrItinData's were duplicated



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199497 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 14:48:06 +00:00
Daniel Sanders
235a81cbbf [mips][sched] Split IIImul and IIImult into subclasses.
IIImul -> II_MUL
IIImult -> II_MULT, II_MULTU, II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_DMULT, II_DMULTU

No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199495 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 14:32:41 +00:00
Daniel Sanders
8821f3c6b2 [mips][sched] Split IIHiLo into II_MFHI_MFLO and II_MTHI_MTLO
No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199493 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 14:17:34 +00:00
Renato Golin
3e2346341c Add MLA alias for ARMv4 support.
Fix MLA defs to use register class GPRnopc.
Add encoding tests for multiply instructions.
(Alias for MUL/SMLAL/UMLAL added by r199026.)

Patch by Zhaoshi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199491 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 13:53:08 +00:00
Kevin Qin
b9536ac581 [AArch64 NEON] Expand vector for UDIV/SDIV/UREM/SREM/FREM as neon doesn't support these operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199485 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 09:54:30 +00:00
Craig Topper
3039306b76 Switch a few instructions to use RI instead I so they don't require REX_W to be explicitly specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 08:16:57 +00:00
Craig Topper
5f69be67b5 Add OpSize16 flags to 32-bit CRC32 instructions so they can be encoded correctly in 16-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199478 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 08:01:20 +00:00
Craig Topper
50a2b1672d Teach x86 asm parser to handle 'opaque ptr' in Intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199477 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 07:44:10 +00:00
Craig Topper
9d0b786f72 Teach X86 asm parser to understand 'ZMMWORD PTR' in Intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199476 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 07:37:39 +00:00
Craig Topper
5d59bb44ee Fix intel syntax for 64-bit version of FXSAVE/FXRSTOR to use '64' suffix instead of 'q'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199474 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 07:25:39 +00:00
Craig Topper
4b42f26ab5 VEX_PREFIX_66 doesn't need to set the hasOpSize flag since VEX instructions don't use the size fields it controls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199470 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 07:11:45 +00:00
Craig Topper
ad6662f202 Replace duplicated code with a existing helper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199468 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 06:42:38 +00:00
Hao Liu
84887ceca3 [AArch64]Fix the problem can't select f16_to_f32 and f32_to_f16.
Also add copy support for FPR16.
Also add a missing test case file belongs to commit r197361.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199463 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 06:23:30 +00:00
Kevin Qin
16511208f2 [AArch64 NEON] Custom lower conversion between vector integer and vector floating point if element bit-width doesn't match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199462 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 05:52:35 +00:00
Hao Liu
555f57f67b [AArch64]Fix the problem can't select concat_vectors of two v1i32 types.
Also fix the problem can't select scalar_to_vector from f32 to v2f32/v4f32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199461 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 05:44:46 +00:00
Daniel Sanders
fbe67dabad [mips][sched] Removed IIXfer. No instructions use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199403 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 17:23:08 +00:00
Daniel Sanders
89d1caaa1b [mips][sched] Put AND, OR, XOR, MOVT_I, and MOVF_I in the same itinerary class as their non-microMIPS counterparts.
No functional change since both classes have the same InstrItinData definition.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199402 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 17:13:57 +00:00
Rafael Espindola
640f8f65a7 Add an emitRawComment function and use it to simplify some uses of EmitRawText.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199397 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 16:28:37 +00:00
Daniel Sanders
1a6226f236 [mips][sched] Split IIseb into II_SEB and II_SEH
No functional change since there are no InstrItinData's.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199396 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 16:19:38 +00:00
Daniel Sanders
ba8f9dde32 [mips][sched] Split IILogic into II_AND, II_OR, II_XOR, II_ANDI, II_ORI, II_XORI
This is necessary because the classes are shared between all implementations.

No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199394 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 15:57:05 +00:00
Daniel Sanders
7bc4a7ced6 [mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
  II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
  II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
  II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
  II_SR[AL]V, II_SUBU, II_XOR

No functional change since the InstrItinData's have been duplicated.

This is necessary because the classes are shared between all schedulers.

Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
Daniel Sanders
31505363ca [mips] Correct itin class for MULT_MM and MULTu_MM to IIImult.
This matches the itin class used by the non-microMIPS equivalents of these
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199389 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:02:48 +00:00
Daniel Sanders
5655b118da [mips] IIImult should have an InstrItinData in the generic scheduler. Used the same one as for IIImul.
Affects:
  DMULT, DMULTu, MADD, MADD_MM, MADDU, MADDU_MM, MSUB, MSUB_MM, MSUBU,
  MSUBU_MM, MULT, MULTu

Does not affect MULT_MM, MULTu_MM since they are currently miscategorised
as IIImul.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199381 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 13:45:53 +00:00
Jiangning Liu
43a785be50 For ARM, fix assertuib failures for some ld/st 3/4 instruction with wirteback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199369 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 09:16:13 +00:00
Elena Demikhovsky
165f7ac98f AVX-512: fixed a compare pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199366 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 08:45:54 +00:00
Craig Topper
c3ab5de57c Copy segment register when optimizing to MOV8ao8/MOV16ao16/MOV32ao32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199365 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 07:57:45 +00:00
Craig Topper
85026d9375 Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199364 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 07:36:58 +00:00
Rafael Espindola
9dcfdf61a8 CommentColumn is always 40. Simplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199357 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 07:04:11 +00:00
Craig Topper
fab01c1908 Remove use of OpSize for populating VEX_PP field. A prefix encoding is now used instead. Simplify some other code. No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199353 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 06:14:45 +00:00
Reed Kotler
897473a28d Adjust offsets for max load instruction offsets. This is more pessimistic
than it needs to be by 1 bit but I need to finish some other things so 
that all the boundary cases will work in that situation. constpool.c
in test-suite will fail to assemble under our new internal test-suite sync
without this change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199343 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 00:47:46 +00:00
Bob Wilson
7fa843cfef Remove support for armv7f slice. <rdar://problem/12478440>
This was never used for anything so we should just get rid of it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199337 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-15 21:44:14 +00:00
Kevin Enderby
96f3b25e8a Update the X86 assembler for .intel_syntax to accept
the | and & bitwise operators.

rdar://15570412


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199323 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-15 19:05:24 +00:00
Zoran Jovanovic
814c8910f2 LL and SC decoder method fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199316 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-15 13:17:33 +00:00
Zoran Jovanovic
f5c2d3896b Added support for LWU microMIPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199315 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-15 13:01:18 +00:00
David Majnemer
f62176f047 WinCOFF: Transform IR expressions featuring __ImageBase into image relative relocations
MSVC on x64 requires that we create image relative symbol
references to refer to RTTI data. Seeing as how there is no way to
explicitly make reference to a given relocation type in LLVM IR, pattern
match expressions of the form &foo - &__ImageBase.

Differential Revision: http://llvm-reviews.chandlerc.com/D2523


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199312 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-15 09:16:42 +00:00
Elena Demikhovsky
a1bcd56f68 Fixed identation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199301 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-15 07:18:11 +00:00
Craig Topper
33ce2bd3de Add OpSize16 to the two byte forms of INC/DEC that we only use in 64-bit mode and a 64-bit only LEA. Even though we'll not be in 16-bit mode when we use them it makes their tables consistent with their 32-bit counterparts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199297 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-15 05:20:59 +00:00
Jiangning Liu
b6db372c96 For AArch64, lowering sext_inreg and generate optimized code by using SXTL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199296 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-15 05:08:01 +00:00
Rafael Espindola
574df95d7a Fix uninitialized variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199288 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-15 03:27:26 +00:00
Rafael Espindola
f6cb056e41 Only mark functions as micromips.
The GNU as behavior is a bit different and very strange. It will mark any
label that contains an instruction. We can implement that, but using the
type looks more natural since gas will not mark a function if a .word is
used to output the instructions!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199287 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-15 03:07:12 +00:00
Weiming Zhao
2a0c41756b PR 18466: Fix ARM Pseudo Expansion
When expanding neon pseudo stores, it may miss the implicit uses of sub
regs, which may cause post RA scheduler reorder instructions that
breakes anti dependency.

For example:
  VST1d64QPseudo %R0<kill>, 16, %Q9_Q10, pred:14, pred:%noreg
  will be expanded to
    VST1d64Q %R0<kill>, 16, %D18, pred:14, pred:%noreg;

An instruction that defines %D20 may be scheduled before the store by
mistake.

This patches adds implicit uses for such case. For the example above, it
emits:
  VST1d64Q %R0<kill>, 8, %D18, pred:14, pred:%noreg, %Q9_Q10<imp-use>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199282 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-15 01:32:12 +00:00
Tim Northover
196c8e5fbb ARM: correctly determine final tBX_LR in Thumb1 functions
The changes caused by folding an sp-adjustment into a "pop" previously
disrupted the forward search for the final real instruction in a
terminating block. This switches to a backward search (skipping debug
instrs).

This fixes PR18399.

Patch by Zhaoshi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199266 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 22:53:28 +00:00
Tim Northover
4e1247b836 AArch64: don't try to handle [SU]MUL_LOHI nodes
We should set them to expand for now since there are no patterns
dealing with them. Actually, there are no instructions either so I
doubt they'll ever be acceptable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199265 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 22:53:22 +00:00