Akira Hatanaka
3f92b439d9
Update ATUsed every time after expandRegLargeImmPair is called.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 20:23:26 +00:00
Mon P Wang
e32cdef38e
Fixed encoding for VEXTqf
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129101 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 19:56:12 +00:00
Akira Hatanaka
9777e7afd4
Fix handling of functions with internal linkage.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 19:51:44 +00:00
Johnny Chen
22dc4d9f59
Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
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Add some test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 19:28:58 +00:00
Johnny Chen
8dbda0b51b
Add sanity checking for invalid register encodings for saturating instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 19:02:08 +00:00
Johnny Chen
4d4e25740b
Add some more comments about checkings of invalid register numbers.
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And two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 18:33:19 +00:00
Tanya Lattner
0433b21c98
Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 15:24:20 +00:00
Johnny Chen
f16f4e09ec
Sanity check MSRi for invalid mask values and reject it as invalid.
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rdar://problem/9246844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 01:37:34 +00:00
Johnny Chen
8424a60fc9
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
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for USAD8 and USADA8.
rdar://problem/9247060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 01:05:52 +00:00
Evan Cheng
2c69f8eec6
Change -arm-divmod-libcall to a target neutral option.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129045 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 00:58:44 +00:00
Johnny Chen
2455268cdd
Should also check SMLAD for invalid register values.
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rdar://problem/9246650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 00:50:25 +00:00
Owen Anderson
df298c9ea6
Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 23:35:59 +00:00
Owen Anderson
ef7fb17936
Cleanups from Jim: remove redundant constraints and a dead FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129036 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 22:45:55 +00:00
Jim Grosbach
f22eefba68
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 22:35:47 +00:00
Johnny Chen
d8b4c4d74f
A8.6.393
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The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.
So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
vst2.32 {d0, d2}, [r3, :256], r3
we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129033 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 22:14:48 +00:00
Johnny Chen
4d81c9a6ba
A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"
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Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.
rdar://problem/9239922
rdar://problem/9239596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 20:49:02 +00:00
Johnny Chen
a9611549fe
Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
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Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.
rdar://problem/9240648
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 18:27:46 +00:00
Rafael Espindola
3d195faaad
Add another case we are not optimizing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129012 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 17:35:32 +00:00
Rafael Espindola
8617897aaa
The original issue has been fixed by not doing unnecessary sign extensions.
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Change the test to force a sign extension and expose the problem again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129011 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 17:19:35 +00:00
Johnny Chen
6a1220eeca
Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.
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Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid.
rdar://problem/9239347
rdar://problem/9239467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 01:18:32 +00:00
Owen Anderson
b48c791515
Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128965 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 23:55:28 +00:00
Johnny Chen
2c868d1eef
Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
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encodings for DisassembleArithMiscFrm().
rdar://problem/9238659
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 23:28:00 +00:00
Bob Wilson
61f3cf3bc9
Clean up some code for clarity.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 23:03:25 +00:00
Owen Anderson
493cba1b32
Revert r128946 while I figure out why it broke the buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 23:03:06 +00:00
Johnny Chen
c3281c10c9
A7.3 register encoding
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Qd -> bit[12] == 0
Qn -> bit[16] == 0
Qm -> bit[0] == 0
If one of these bits is 1, the instruction is UNDEFINED.
rdar://problem/9238399
rdar://problem/9238445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 22:57:07 +00:00
Owen Anderson
76634dfabb
Give RSBS and RSCS the pseudo treatment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 22:42:54 +00:00
Johnny Chen
5438d76416
ARM disassembler was erroneously accepting an invalid RSC instruction.
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Added checks for regs which should not be 15.
rdar://problem/9237734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 22:18:07 +00:00
Johnny Chen
c584e317e9
ARM disassembler was erroneously accepting an invalid LSL instruction.
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For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.
rdar://problem/9237693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 21:49:44 +00:00
Owen Anderson
7670601313
Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 21:48:57 +00:00
Johnny Chen
2c2130bc64
The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.
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Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.
rdar://problem/9236873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 20:32:23 +00:00
Johnny Chen
bbc65bbb90
ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128913 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 19:42:11 +00:00
Jim Grosbach
215e4fdbf9
Make second source operand of LDRD pre/post explicit.
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Finish what r128736 started.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 18:40:13 +00:00
Johnny Chen
12bb2958c4
Constants with multiple encodings (ARM):
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An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:
<byte> is the numeric value of abcdefgh, in the range 0-255
<rot> is twice the numeric value of rotation, an even number in the range 0-30.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 18:02:46 +00:00
Johnny Chen
b26d8d7c49
Check for invalid register encodings for UMAAL and friends where:
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if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
if dHi == dLo then UNPREDICTABLE;
rdar://problem/9230202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 17:43:10 +00:00
Owen Anderson
15b81b51d6
Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 17:24:25 +00:00
Bill Wendling
f05b1dcf87
Revamp the SjLj "dispatch setup" intrinsic.
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It needed to be moved closer to the setjmp statement, because the code directly
after the setjmp needs to know about values that are on the stack. Also, the
'bitcast' of the function context was causing a dead load. This wouldn't be too
horrible, except that at -O0 it wasn't optimized out, and because it wasn't
using the correct base pointer (if there is a VLA), it would try to access a
value from a garbage address.
<rdar://problem/9130540>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 01:37:43 +00:00
Eric Christopher
0435661582
Just use BL all the time. It's safer that way.
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Fixes rdar://9184526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128869 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 00:39:26 +00:00
Johnny Chen
157536b1fb
Fix SRS/SRSW encoding bits.
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rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS
Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 00:16:18 +00:00
Johnny Chen
597028cc28
A8.6.105 MUL
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Inst{15-12} should be specified as 0b0000.
rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 23:57:05 +00:00
Johnny Chen
670a456c83
RFE encoding should also specify the "should be" encoding bits.
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rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE
Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while
doing regression testings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 23:39:08 +00:00
Joerg Sonnenberger
c15a91dfc8
Make OpcodeMask an unsigned long long literal to deal with overflow.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 21:38:17 +00:00
Johnny Chen
2d66cec9dd
Fix incorrect alignment for NEON VST2b32_UPD.
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rdar://problem/9225433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 20:35:31 +00:00
Jakob Stoklund Olesen
5fcb81dace
Insert code in the right location when lowering PowerPC atomics.
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This causes defs to dominate uses, no instructions after terminators, and other
goodness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:57:29 +00:00
Bruno Cardoso Lopes
ac79e4c82f
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
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also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
index mode to print.
- Testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:18:19 +00:00
Akira Hatanaka
f49fde2877
Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:11:07 +00:00
Jakob Stoklund Olesen
cf3a74824f
PowerPC atomic pseudos clobber CR0, they don't read it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:07:09 +00:00
Jakob Stoklund Olesen
2684c5db84
Use X0 instead of R0 for the zero register on ppc64.
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The 32-bit R0 cannot be used where a 64-bit register is expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128828 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:07:06 +00:00
Joerg Sonnenberger
4a8ac8de1d
Add support for the VIA PadLock instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 16:58:13 +00:00
Joerg Sonnenberger
229e4523f2
Expand Op0Mask by one bit in preparation for the PadLock prefixes.
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Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128822 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 15:58:30 +00:00
Jay Foad
3e2f74e6d6
Remove some support for ReturnInsts with multiple operands, and for
...
returning a scalar value in a function whose return type is a single-
element structure or array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128810 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 07:44:02 +00:00