It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.
A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146124 91177308-0d34-0410-b5e6-96231b3b80d8
Compute alignment padding before and after basic blocks dynamically.
Heed basic block alignment.
This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size. It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.
This makes the ARMConstantIslandPass aware of aligned basic blocks.
It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size. If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected. This could cause constant
pool entries to move out of range.
To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly. Normal
functions should be unaffected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146118 91177308-0d34-0410-b5e6-96231b3b80d8
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146054 91177308-0d34-0410-b5e6-96231b3b80d8
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.
Eliminate one redundant AdjustBBOffsetsAfter call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146018 91177308-0d34-0410-b5e6-96231b3b80d8
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146007 91177308-0d34-0410-b5e6-96231b3b80d8
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145994 91177308-0d34-0410-b5e6-96231b3b80d8
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.
It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145971 91177308-0d34-0410-b5e6-96231b3b80d8
ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.
This should fix the many Thumb1 assembler errors in the nightly test
suite.
The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.
<rdar://problem/10534709>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145970 91177308-0d34-0410-b5e6-96231b3b80d8
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment
is set on the basic block.
This is in preparation of supporting ARM constant pool islands with
different alignments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145890 91177308-0d34-0410-b5e6-96231b3b80d8
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145881 91177308-0d34-0410-b5e6-96231b3b80d8
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145871 91177308-0d34-0410-b5e6-96231b3b80d8
