Devang Patel
c3f5f783a2
First cut at supporting .debug_loc section.
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This is used to track variable information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104649 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 23:40:22 +00:00
Benjamin Kramer
48aefe15d0
Properly promote operands when optimizing a single-character memcmp.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 22:53:43 +00:00
Bill Wendling
f10bc81b4e
Constify function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104646 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 22:02:22 +00:00
Dan Gohman
eddc114a66
Do one map lookup instead of two.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:59:42 +00:00
Dan Gohman
5b71dcedf0
Fix a missing newline in debug output.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104644 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:50:35 +00:00
Eric Christopher
04386ca726
Move the verbose asm output up a bit so it can be used in the special cases
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as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:49:43 +00:00
Bill Wendling
5edfbdc963
Okay, bear with me here...
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If you have a setjmp/longjmp situation, it's possible for stack slot coloring to
reuse a stack slot before it's really dead. For instance, if we have something
like this:
1: y = g;
x = sigsetjmp(env, 0);
switch (x) {
case 1:
/* ... */
goto run;
case 0:
run:
do_run(); /* marked as "no return" */
break;
case 3:
if (...) {
/* ... */
goto run;
}
/* ... */
break;
}
2: g = y;
"y" may be put onto the stack, so the expression "g = y" is relying upon the
fact that the stack slot containing "y" isn't modified between (1) and (2). But
it can be, because of the "no return" calls in there. A longjmp might come back
with 3, modify the stack slot, and then go to case 0. And it's perfectly
acceptable to reuse the stack slot there because there's no CFG flow from case 3
to (2).
The fix is to disable certain optimizations in these situations. Ideally, we'd
disable them for all "returns twice" functions. But we don't support that
attribute. Check for "setjmp" and "sigsetjmp" instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:44:26 +00:00
Eric Christopher
02b46bc942
Add support for initialized global data for darwin tls. Update comments
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and testcases accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:28:50 +00:00
Kevin Enderby
cf50a5390c
Changed the encoding of X86 floating point stack operations where both operands
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are st(0). These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0. To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used. To do this the same logical trick is use from the darwin assembler
in converting things like this:
fmul %st(0), %st
into this:
fmul %st(0)
by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand. This also has the add
benefit to allow things like:
fmul %st(1), %st
that llvm-mc did not assemble.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 20:52:34 +00:00
Jakob Stoklund Olesen
b53985239c
Separate unrelated cases that once shared a numeric value
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104629 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:40 +00:00
Jakob Stoklund Olesen
1fc8e759a7
Print symbolic SubRegIndex names on machine operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:38 +00:00
Jakob Stoklund Olesen
4fda9670f0
Remove NumberHack entirely.
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SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:33 +00:00
Daniel Dunbar
39e2dd7bab
MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104626 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:32 +00:00
Dale Johannesen
86234c30a7
Fix another variant of PR 7191. Also add a testcase
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Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite. 8023512.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104624 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:47:23 +00:00
Daniel Dunbar
79373680ed
MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:40:53 +00:00
Kevin Enderby
04ac770be9
The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required
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for the 64-bit version of the Bit Test instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:16:58 +00:00
Dale Johannesen
61734eb117
Fix PR 7191. I have been unable to create a .ll file that fails, sorry.
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(oye, a word which should be better known to people writing tree
traversals, means grandchild.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104619 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:50:03 +00:00
Eric Christopher
7e2f5aaa67
Make sure aeskeygenassist uses an unsigned immediate field.
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Fixes rdar://8017638
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:33:22 +00:00
Jakob Stoklund Olesen
48d0c163fb
Ignore NumberHack and give each SubRegIndex instance a unique enum value instead.
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This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.
Then I'll remove NumberHack entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104615 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:21:04 +00:00
Jakob Stoklund Olesen
c159fba712
Use enums instead of literals for SystemZ subregisters
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104612 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:04:18 +00:00
Jakob Stoklund Olesen
22c0e97c56
Use enums instead of literals for X86 subregisters.
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The cases in getMatchingSuperRegClass cannot be broken up until the enums have
unique values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104611 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:04:16 +00:00
Zonr Chang
f3c770a2cb
Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 10:23:52 +00:00
Zonr Chang
f86399be0c
Add support to MOVimm32 using movt/movw for ARM JIT
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104587 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 08:42:45 +00:00
Bob Wilson
a85df80ed7
Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.
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I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104583 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 04:51:47 +00:00
Bob Wilson
4876bdb69e
Fix up instruction classes for Thumb2 RSB instructions to be consistent with
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Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 04:43:08 +00:00
Bob Wilson
ab3912e3ce
Clean up indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104580 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 03:36:52 +00:00
Jakob Stoklund Olesen
b7a3170917
Disable invalid coalescer assertion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104574 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 00:15:18 +00:00
Jakob Stoklund Olesen
e00fa64c16
Use enums instead of literals in the ARM backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 00:15:15 +00:00
Bill Wendling
ef473bfc44
Print out the name of the function during SSC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104572 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 23:16:04 +00:00
Jakob Stoklund Olesen
33276d95ef
Switch SubRegSet to using symbolic SubRegIndices
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 23:03:18 +00:00
Bob Wilson
c21763fd99
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
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version of t2MVN already allowed that, but not the register versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 22:41:19 +00:00
Jakob Stoklund Olesen
f27462eb29
Lose the dummies
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104564 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:47:01 +00:00
Jakob Stoklund Olesen
09bc029865
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
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structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:46:58 +00:00
Evan Cheng
3946043a80
Avoid adding duplicate function live-in's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:33:37 +00:00
Dan Gohman
e350690e3b
Fix an mmx movd encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:51:08 +00:00
Kevin Enderby
ca956dc0f6
MC/X86: Add aliases for CMOVcc variants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:32:23 +00:00
Bob Wilson
d303846e16
Clean up some extra whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104544 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:08:34 +00:00
Bob Wilson
bb7ecb2bf5
Thumb2 RSBS instructions were being printed without the 'S' suffix.
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Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:44:06 +00:00
Devang Patel
295cdf8b82
Do not emit line number entries for unknown debug values.
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This fixes recent regression in store.exp from gdb testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:26:49 +00:00
Evan Cheng
c7cf10c97e
LR is in GPR, not tGPR even in Thumb1 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:00:18 +00:00
Jakob Stoklund Olesen
a1132276e7
Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are
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never used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104517 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 17:55:38 +00:00
Jakob Stoklund Olesen
d6be874e8c
Use SubRegIndex in SystemZ.
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Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 17:43:01 +00:00
Jakob Stoklund Olesen
fff916a960
SubRegIndex'ize Mips
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 17:42:58 +00:00
Jakob Stoklund Olesen
59f7199e16
SubRegIndex'ize MSP430
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 17:42:55 +00:00
Jakob Stoklund Olesen
7bb31e3187
Fix a few places that depended on the numeric value of subreg indices.
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Add assertions in places that depend on consecutive indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104510 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 17:13:28 +00:00
Jakob Stoklund Olesen
558661d271
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
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from ARMRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 16:54:32 +00:00
Jakob Stoklund Olesen
3458e9e4df
Rename X86 subregister indices to something shorter.
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Use the tablegen-produced enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:17 +00:00
Jakob Stoklund Olesen
73ea7bf450
Add the SubRegIndex TableGen class.
...
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:12 +00:00
Nicolas Geoffray
3816c25fdc
Encode the Caml frametable by following what the comment says: the number of descriptors
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is first emitted, and StackOffsets are emitted in 16 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104488 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 12:24:11 +00:00
Daniel Dunbar
414c0c43d3
llvm-mc: Use EmitIntValue where possible, which makes the API calls from the AsmParser and CodeGen line up better.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104467 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-23 18:36:38 +00:00
Daniel Dunbar
01777ff094
llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-23 18:36:34 +00:00
Daniel Dunbar
fdb5a86179
MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104463 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-23 17:44:06 +00:00
Bob Wilson
069e434868
VDUP doesn't support vectors with 64-bit elements.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-23 05:42:31 +00:00
Daniel Dunbar
62e4c671b6
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
...
addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:33 +00:00
Daniel Dunbar
54ddf3d9c7
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104452 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:29 +00:00
Daniel Dunbar
4c361972fd
MC/X86: Add alias for setz, setnz, jz, jnz.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 06:37:33 +00:00
Evan Cheng
2457f2c661
Implement @llvm.returnaddress. rdar://8015977.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 01:47:14 +00:00
Jim Grosbach
5eb1951539
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
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Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 01:06:18 +00:00
Bob Wilson
be751cfe9c
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
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copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:23:12 +00:00
Eric Christopher
8116ca5134
Add full bss data support for darwin tls variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104414 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:10:22 +00:00
Devang Patel
65eb482e8f
Collect variable information during endFunction() instead of beginFunction().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104412 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:04:14 +00:00
Bob Wilson
70fe6643d6
Clean up extra whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 23:53:55 +00:00
Eric Christopher
e81d010589
Make this LookAheadLimit, not the uninitialized LookAheadLeft.
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Evan please verify!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104408 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 23:40:03 +00:00
Chris Lattner
c2685a9c98
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 23:16:21 +00:00
Eric Christopher
070c1abbc9
Expand on comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 23:03:53 +00:00
Kevin Enderby
9d31d79493
Added retl for 32-bit x86 and added retq for 64-bit x86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104394 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 23:01:38 +00:00
Evan Cheng
835810bbf8
Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104385 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 21:22:19 +00:00
Eric Christopher
9b00685bb6
Fix section attribute name.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104381 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 21:08:52 +00:00
Bob Wilson
78f006acdf
Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
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so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104380 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 21:05:32 +00:00
Evan Cheng
1015ba7018
- Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
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that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 20:53:24 +00:00
Jakob Stoklund Olesen
18b2c9d3bf
Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction
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reads or writes a register.
This takes partial redefines and undef uses into account.
Don't actually use it yet. That caused miscompiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 20:02:01 +00:00
Devang Patel
379fe83dda
Simplify
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104338 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 18:49:09 +00:00
Dale Johannesen
acbf6348b1
Previous commit message should refer to 104308.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104337 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 18:44:47 +00:00
Dale Johannesen
e39859a838
Fix two bugs in 104348:
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Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104336 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 18:40:15 +00:00
Chris Lattner
a26a8471bd
now that fp reg kill insertion stuff happens as a separate
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pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.
The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes. Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross. It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).
Just do the scan on machine phis which is simpler, faster
and more correct. This fixes PR6828.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 18:17:54 +00:00
Chris Lattner
d596c90030
Use less evil form of switch stmt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104331 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 18:02:42 +00:00
Chris Lattner
d3d9ee1a4d
use continue to reduce nesting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104330 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 18:01:24 +00:00
Chris Lattner
637e073181
pull a nested loop of this pass out to its own function,
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eliminating the gymnastics around the ContainsFPCode var.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104328 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 17:57:03 +00:00
Chris Lattner
6f569aabb5
modernize this pass a bit, fit in 80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104326 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 17:49:07 +00:00
Chris Lattner
65569b8ddf
constify accessor.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104325 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 17:47:50 +00:00
Jakob Stoklund Olesen
19f5f71bba
Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read."
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This reverts r104322. I think it was causing miscompilations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen
00c53caa33
Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.
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This correctly handles partial redefines and undef uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen
2afb7505c5
Teach VirtRegRewriter to handle spilling in instructions that have multiple
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definitions of the virtual register.
This happens when spilling the registers produced by REG_SEQUENCE:
%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0
The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 16:36:13 +00:00
Jakob Stoklund Olesen
63e6a488cb
If the first definition of a virtual register is a partial redef, add an
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<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104320 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 16:32:16 +00:00
Matt Fleming
d8a33ddcfe
Currently, createMachOStreamer() is invoked directly in llvm-mc which
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isn't ideal if we want to be able to use another object file format.
Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104318 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 12:54:43 +00:00
Matt Fleming
7efaef6b82
Split out the x86_32 an x86_64 ELF backends as they handle ELF
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differently. This will make adding ELF support easier in the long run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104317 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 11:39:07 +00:00
Matt Fleming
924c5e58f2
Add support for parsing the ELF .type assembler directive.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104316 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 11:36:59 +00:00
Dale Johannesen
7d07b48b26
Fix i64->f64 conversion, x86-64, -no-sse. A bit
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tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104308 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 00:52:33 +00:00
Evan Cheng
f7d87ee158
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 00:43:17 +00:00
Evan Cheng
b11ac950d6
Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 00:42:32 +00:00
Devang Patel
c0c5a26dea
Simplify.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104302 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 00:10:20 +00:00
Daniel Dunbar
4ef6730632
Fix __crashreport_info__ declaration.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104300 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 23:50:19 +00:00
Evan Cheng
1cc3984148
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 23:26:43 +00:00
Dan Gohman
0fe46d9b48
DominatorTree.getNode can return null for unreachable blocks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104290 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 22:46:54 +00:00
Dan Gohman
9f383eb950
Minor code cleanups.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104287 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 22:25:20 +00:00
Mikhail Glushenkov
dcc44670f4
Print a space after the colon.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 21:11:37 +00:00
Dan Gohman
a552878508
Make Solve check its own post-condition, to reduce clutter in the
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top-level LSRInstance logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104278 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:59:23 +00:00
Dan Gohman
76c315a26c
Add comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:52:00 +00:00
Daniel Dunbar
4e7f8390c0
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:36:29 +00:00
Devang Patel
6ed0ce3240
Rename variable. add comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104274 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:35:24 +00:00