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44ec9fddc2
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20421 Commits

Author SHA1 Message Date
Craig Topper
44ec9fddc2 Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 256-bit integer instructions when AVX2 isn't enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144629 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 06:39:01 +00:00
Craig Topper
4c077a1f04 Properly qualify AVX2 specific parts of execution dependency table. Also enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144622 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 05:55:35 +00:00
Evan Cheng
eaa192af18 Add vmov.f32 to materialize f32 immediate splats which cannot be handled by 
integer variants. rdar://10437054


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 02:12:34 +00:00
Jim Grosbach
bfc9429c2b ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144606 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 01:46:57 +00:00
Jakob Stoklund Olesen
c2ecf3efbf Break false dependencies before partial register updates. 
Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.

The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.

The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144602 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 01:15:30 +00:00
Jim Grosbach
dd47e0b5d4 ARM parsing datatype suffix variants for non-writeback VST1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:43:46 +00:00
Jim Grosbach
e052b9afa1 ARM parsing datatype suffix variants for non-writeback VLD1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:32:59 +00:00
Jim Grosbach
04db7f7a7d Add explanatory comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144589 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:21:09 +00:00
Jim Grosbach
0530d0d5d9 Split out the plain '.{8|16|32|64}' suffix handling. 
Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144588 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:20:14 +00:00
Jim Grosbach
ef448767a3 ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144587 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:11:19 +00:00
Chad Rosier
2c42b8c912 Supporting inline memmove isn't going to be worthwhile. The only way to avoid 
violating a dependency is to emit all loads prior to stores.  This would likely
cause a great deal of spillage offsetting any potential gains.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:04:09 +00:00
Jim Grosbach
ffc658b056 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:03:21 +00:00
Chad Rosier
909cb4f2f2 Add support for inlining small memcpys. 
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144578 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 22:46:17 +00:00
Chad Rosier
e489af8dce Fix a performance regression from r144565. Positive offsets were being lowered 
into registers, rather then encoded directly in the load/store.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144576 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 22:34:48 +00:00
Jim Grosbach
02e3d9268f ARM assembly parsing type suffix options for VLDR/VSTR. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 22:28:39 +00:00
Evan Cheng
76c8f08567 Add a missing pattern for X86ISD::MOVLPD. rdar://10436044 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144566 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 20:35:52 +00:00
Chad Rosier
57b2997966 Add support for Thumb load/stores with negative offsets. 
rdar://10412592



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144565 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 20:22:27 +00:00
Benjamin Kramer
6296ee3ee2 Unbreak Release builds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 19:51:48 +00:00
Pete Cooper
a77214a4c4 Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom lowered 
Constant idx case is still done in tablegen but other cases are then expanded

Fixes <rdar://problem/10435460>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 19:38:42 +00:00
Akira Hatanaka
788dc0f4e5 32-to-64-bit extended load. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144554 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 19:06:14 +00:00
Akira Hatanaka
4961709688 AnalyzeCallOperands function for N32/64. 
N32/64 places all variable arguments in integer registers (or on stack),
regardless of their types, but follows calling convention of non-vaarg function
when it handles fixed arguments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144553 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 19:02:54 +00:00
Akira Hatanaka
bad53f41c2 Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144552 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 19:01:09 +00:00
Justin Holewinski
a3f7e229b6 PTX: Let LLVM use loads/stores for all mem* intrinsics, instead of relying on custom implementations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144551 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 18:58:20 +00:00
Akira Hatanaka
47a4ab84fe Remove variable that keeps the size of area used to save byval or variable 
argument registers on the callee's stack frame, along with functions that set
and get it.
    
It is not necessary to add the size of this area when computing stack size in
emitPrologue, since it has already been accounted for in
PEI::calculateFrameObjectOffsets.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144549 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 18:56:20 +00:00
Jim Grosbach
430052b084 Tidy up. 80 column. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144538 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 17:52:47 +00:00
Craig Topper
dcce244dd8 Add AVX2 version of instructions to load folding tables. Also add a bunch of missing SSE/AVX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144525 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 08:07:55 +00:00
Craig Topper
3426a3efef Add neverHasSideEffects, mayLoad, and mayStore to many patternless SSE/AVX instructions. Remove MMX check from LowerVECTOR_SHUFFLE since MMX vector types won't go through it anyway. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 06:46:21 +00:00
Chad Rosier
dc9205d9c2 Add support for ARM halfword load/stores and signed byte loads with negative 
offsets.
rdar://10412592



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144518 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 04:09:28 +00:00
Craig Topper
e6a6277d36 Add BLSI, BLSMSK, and BLSR to getTargetNodeName. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144502 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 17:31:07 +00:00
Chad Rosier
9eb674880b The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144494 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 09:44:21 +00:00
Chad Rosier
a517ab155b Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144492 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 05:14:43 +00:00
Chad Rosier
5be833de76 Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144490 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 04:25:02 +00:00
Chad Rosier
b29b950bf2 Add support for emitting both signed- and zero-extend loads. Fix 
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 02:23:59 +00:00
Craig Topper
7be5dfd1a1 Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144457 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 09:58:49 +00:00
Akira Hatanaka
7386612a16 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144453 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 02:38:12 +00:00
Akira Hatanaka
6df3e7b162 Implement Mips64's handling of byval arguments in LowerCall. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144452 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 02:34:50 +00:00
Akira Hatanaka
3a5257de21 Implement Mips64's handling of byval arguments in LowerFormalArguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144449 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 02:29:58 +00:00
Akira Hatanaka
deab22a556 64-bit arbitrary immediate pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144448 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 02:25:00 +00:00
Akira Hatanaka
2c5d65202e Function for handling byval arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144447 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 02:20:46 +00:00
Daniel Dunbar
b8ebca83f4 build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies. 
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144444 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 02:10:57 +00:00
Jim Grosbach
9588c10b69 ARM refactor simple immediate asm operand render methods. 
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144439 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 00:58:43 +00:00
Jim Grosbach
742c4bac07 Re-apply 144430, this time with the associated isel and disassmbler bits. 
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144437 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 00:31:53 +00:00
Jim Grosbach
4d06138d53 Oops. Missed the isel half of this. revert while I sort that out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144431 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:51:31 +00:00
Jim Grosbach
10a630dea6 ARM assembly parsing for VST1 two-register encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144430 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:45:47 +00:00
Jim Grosbach
c7352f8ca0 ARM optional size suffix for VLDR/VSTR syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:34:43 +00:00
Chad Rosier
11add26ec2 Add support in fast-isel for selecting memset/memcpy/memmove intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144426 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:31:03 +00:00
Daniel Dunbar
b12f97534c CMake: Fix CMake build for new Mips tblgen file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144423 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:12:56 +00:00
Jim Grosbach
7aef99b677 ARM vldm and vstm VFP instructions can take a data type suffix. 
It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.

Partial for rdar://10435264

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:08:10 +00:00
Daniel Dunbar
f779757ceb Target/LLVMBuild: Order components alphabetically. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 22:59:16 +00:00
Bruno Cardoso Lopes
47b92f3d83 Mips MC object code emission improvements: 
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144414 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 22:58:42 +00:00