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21884 Commits

Author SHA1 Message Date
Eric Christopher
4adbefebd2 Add support for the 'l' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156294 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:25:15 +00:00
Eric Christopher
1d5a392e2c Add support for the 'c' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156293 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:25:10 +00:00
Eric Christopher
54412a789a Add support for the 'P' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156292 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:25:02 +00:00
Craig Topper
ef2b8bda02 Fix some issues in the f16c instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156287 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:00:15 +00:00
Eric Christopher
1ce2034e43 Add support for the 'O' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156285 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:46:48 +00:00
Eric Christopher
60cfc7908e Add support for the 'N' inline asm constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156284 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:46:43 +00:00
Eric Christopher
5ac47bba83 Add support for the 'L' inline asm constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156283 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:46:37 +00:00
Eric Christopher
f49f846eec Add support for the inline asm constraint 'K'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156282 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:46:29 +00:00
Craig Topper
5f9cccc509 Add SSE4A MOVNTSS/MOVNTSD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156281 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:36:19 +00:00
Eric Christopher
e5076d484b Support the 'J' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156280 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 03:13:42 +00:00
Eric Christopher
50ab03954e Add support for the 'I' inline asm constraint. Also add tests 
from the previous 2 patches.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156279 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 03:13:32 +00:00
Eric Christopher
0ed1f764f4 Allow 64 bit integer values in gpu registers if arch and abi are 64 bit. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156278 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 03:13:22 +00:00
Eric Christopher
3ccbd47ecb When using inline asm constraints representing 
non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156277 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 03:13:16 +00:00
Craig Topper
d978c54e60 Use MVT instead of EVT as the argument to all the shuffle decode functions. Simplify some of the decode functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156268 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-06 19:46:21 +00:00
Craig Topper
bdcbcb3ae7 Add VPERMQ/VPERMPD to the list of target specific shuffles that can be looked through for DAG combine purposes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156266 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-06 18:54:26 +00:00
Craig Topper
156f5bb56e Add shuffle decode support for VPERMQ/VPERMPD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156265 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-06 18:44:02 +00:00
Jim Grosbach
e5f31ad55e Nuke a few dead remnants of the CBE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156241 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-05 17:45:12 +00:00
Benjamin Kramer
aaf723dd2b Add a new target hook "predictableSelectIsExpensive". 
This will be used to determine whether it's profitable to turn a select into a
branch when the branch is likely to be predicted.

Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM.

I'm not entirely happy with the name of this flag, suggestions welcome ;)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156233 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-05 12:49:14 +00:00
Benjamin Kramer
af87831519 NVPTX: Initialize the UseF32FTZ flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156232 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-05 11:22:02 +00:00
Eric Christopher
f2eed387d4 Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156226 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-05 01:16:06 +00:00
David Blaikie
03ba93e194 Fix warnings in release build. 
This fixes a couple of Clang warnings in release builds of LLVM:

* Missing return in ISelLowering
* Unused variable in NVPTXutil.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156216 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 22:34:16 +00:00
Kevin Enderby
3610a15c35 Tweak to the fix in r156212, as with the change in removing the shift the 
SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156213 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 22:09:52 +00:00
Kevin Enderby
ce734d5ffe Fix a bug in the ARM disassembler for wide branch conditional instructions 
where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://11387046


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156212 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 22:02:27 +00:00
Chandler Carruth
917644d0c3 Fix a Clang warning in the new NVPTX backend: 
In file included from ../lib/Target/NVPTX/VectorElementize.cpp:53:
../lib/Target/NVPTX/NVPTX.h:44:3: warning: default label in switch which covers all enumeration values [-Wcovered-switch-default]
  default: assert(0 && "Unknown condition code");
  ^
1 warning generated.

The prevailing pattern in LLVM is to not use a default label, and instead to
use llvm_unreachable to denote that the switch in fact covers all return paths
from the function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156209 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 21:35:49 +00:00
Justin Holewinski
49683f3c96 This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it. 
The new target machines are:

nvptx (old ptx32) => 32-bit PTX
nvptx64 (old ptx64) => 64-bit PTX

The sources are based on the internal NVIDIA NVPTX back-end, and
contain more functionality than the current PTX back-end currently
provides.

NV_CONTRIB

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 20:18:50 +00:00
Sebastian Pop
2c7e5c714c Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits 16-bits encoding of CMN instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156195 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 19:53:56 +00:00
Preston Gurd
3d142e58ef Adds Intel Atom scheduling latencies to X86InstrSystem.td. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156194 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 19:26:37 +00:00
Matt Beaumont-Gay
39af9449a2 Pacify GCC's -Wreturn-type 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156189 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 18:34:27 +00:00
Hans Wennborg
fd5abd546e Make ARM and Mips use TargetMachine::getTLSModel() 
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156162 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 09:40:39 +00:00
Craig Topper
31a207a3b7 Fix some loops to match coding standards. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156159 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 06:39:13 +00:00
Craig Topper
6643d9c180 Fix up some spacing. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156158 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 06:18:33 +00:00
Craig Topper
5da8a80377 Simplify broadcast lowering code. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156157 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 05:49:51 +00:00
Craig Topper
f3640d7ec1 Allow v16i16 and v32i8 shuffles to be rewritten as narrower shuffles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156156 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 04:44:49 +00:00
Craig Topper
11ac1f81a8 Simplify shuffle narrowing code a bit. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156154 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 04:08:44 +00:00
Jakob Stoklund Olesen
338607ae0d Remove the SubRegClasses field from RegisterClass descriptions. 
This information in now computed by TableGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 03:30:34 +00:00
Jakob Stoklund Olesen
ed277f3eeb Initialize SparcInstrInfo before SparcTargetLowering. 
The TargetLowering construction needs to use a valid TargetRegisterInfo
instance.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156146 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 02:16:39 +00:00
Jakob Stoklund Olesen
89e38f8721 Add a SuperRegClassIterator class. 
This iterator class provides a more abstract interface to the (Idx,
Mask) lists of super-registers for a register class. The layout of the
tables shouldn't be exposed to clients.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156144 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 01:48:29 +00:00
Jakob Stoklund Olesen
dd63a063e2 Use a shared implementation of getMatchingSuperRegClass(). 
TargetRegisterClass now gives access to the necessary tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156122 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 22:49:04 +00:00
Kevin Enderby
2d524b0765 Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits 
for the assembler and disassembler.  Which were not being set/read correctly
for offsets greater than 22 bits in some cases.

Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 22:41:56 +00:00
Sirish Pande
26f61a158b Support for target dependent Hexagon VLIW packetizer. 
This patch creates and optimizes packets as per Hexagon ISA rules.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156109 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 21:52:53 +00:00
Silviu Baranga
b422d0b65e Fixed disassembler for vstm/vldm ARM VFP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 16:38:40 +00:00
Sirish Pande
71d56462a1 Extensions of Hexagon V4 instructions. 
This adds new instructions for Hexagon V4 architecture.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156071 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 16:18:50 +00:00
Craig Topper
b607264550 Use 'unsigned' instead of 'int' in a few places dealing with counts of vector elements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156060 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 07:26:59 +00:00
Craig Topper
6b28d356c5 Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the lower half correctly. Missed in r155982. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156059 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 07:12:59 +00:00
Andrew Trick
f12f6dff97 Added TargetRegisterInfo::getAllocatableClass. 
The ensures that virtual registers always belong to an allocatable class.
If your target attempts to create a vreg for an operand that has no
allocatable register subclass, you will crash quickly.

This ensures that targets define register classes as intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156046 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 01:14:37 +00:00
Preston Gurd
c0f0a93936 For Intel Atom, use ILP scheduling always, instead of ILP for 64 bit 
and Hybrid for 32 bit, since benchmarks show ILP scheduling is better
most of the time.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156028 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-02 22:02:02 +00:00
Preston Gurd
79bbe855cd Change the Intel Atom detection code to recognize 
Lincroft and Medfield.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156025 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-02 21:38:46 +00:00
Jim Grosbach
2727930ab4 ARM: Add missing two-operand VBIC aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156019 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-02 21:11:56 +00:00
Preston Gurd
95f0cf0438 This patch continues the work of adding instruction latencies for X86 Atom, 
by providing the latencies for the instructions in X86InstrFPStack.td.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155996 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-02 16:03:35 +00:00
Manman Ren
e2849851b2 Revert r155853 
The commit is intended to fix rdar://10961709.
But it is the root cause of PR12720.
Revert it for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155992 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-02 15:24:32 +00:00