Jim Grosbach
940c8e5494
Recognize a few more documented register name aliases for ARM in the asm lexer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 23:19:54 +00:00
Bob Wilson
3c904694fc
Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions.
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If the basic block containing the BCCi64 (or BCCZi64) instruction ends with
an unconditional branch, that branch needs to be deleted before appending
the expansion of the BCCi64 to the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 22:45:49 +00:00
Chris Lattner
036609bd7d
Flag -> Glue, the ongoing saga
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 18:28:41 +00:00
Jim Grosbach
9584bd83e6
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22 23:26:02 +00:00
Bob Wilson
316009054e
Add ARM-specific DAG combining to cast i64 vector element load/stores to f64.
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Type legalization splits up i64 values into pairs of i32 values, which leads
to poor quality code when inserting or extracting i64 vector elements.
If the vector element is loaded or stored, it can be treated as an f64 value
and loaded or stored directly from a VPR register. Use the pre-legalization
DAG combiner to cast those vector elements to f64 types so that the type
legalizer won't mess them up. Radar 8755338.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122319 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 06:43:19 +00:00
Eric Christopher
c19aadb8b0
Arm and thumb call instructions are also in different orders.
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Fixes rdar://8782223
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122313 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 03:50:43 +00:00
Chris Lattner
f1b4eafbfe
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
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something that just glues two nodes together, even if it is
sometimes used for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 02:38:05 +00:00
Eric Christopher
6e90ce21cc
If we're not using reg+reg offset we're using reg+imm, set the opcode
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to be the one we want to use. bugpoint reduced testcase is a little large,
I'll see if I can simplify it down more.
Fixes part of rdar://8782207
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 02:12:07 +00:00
Bill Wendling
a519d57725
Fix a copy-pasto. When the tBR_JTr instruction was converted to using the
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tPseudoInst class, its size was changed from "special" to "2 bytes". This is
incorrect because the jump table will no longer be taken into account when
calculating branch offsets.
<rdar://problem/8782216>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122303 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 01:57:15 +00:00
Bill Wendling
9a4d2e40a0
Comment cleanups.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122302 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 01:54:40 +00:00
Rafael Espindola
1ec5bd31fe
Remove the MCObjectFormat class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 05:37:28 +00:00
Rafael Espindola
bff66a86e6
Move some data to the TargetWriter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 03:27:34 +00:00
Bill Wendling
a68a4fdf37
r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr to
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ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting
misaligned references to the jump table from an ADR instruction.
There is a test case, but unfortunately it's sensitive to random code changes.
<rdar://problem/8782223>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122131 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 02:13:59 +00:00
Bill Wendling
cd080249fc
RemoveUnusedCPEntries can change things. Track it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122129 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 01:53:06 +00:00
Bob Wilson
094dd80ecc
Rearrange some Neon multiclasses. No functional changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 00:42:58 +00:00
Bob Wilson
3deb45149a
Fix result type of Neon floating-point comparisons against zero.
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The result vector elements are always integers. Radar 8782191.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122112 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 00:04:33 +00:00
Bob Wilson
3a75b9bc8f
Add some missing entries in ARMTargetLowering::getTargetNodeName.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 00:04:26 +00:00
Bill Wendling
976ef86689
During local stack slot allocation, the materializeFrameBaseRegister function
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may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.
Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)
<rdar://problem/8782198>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 23:09:14 +00:00
Bob Wilson
9bb43e1675
Avoid report_fatal_error in ARM's PrintAsmOperand method.
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The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122100 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 23:06:42 +00:00
Jim Grosbach
a3dbd3a244
If The ARM WriteNopData() gets an unaligned byte count to pad out, fill in with
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a partial value. rdar://8782954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 19:03:02 +00:00
Jim Grosbach
f0db261e97
Add bits 31-28 to the Thumb2 encoding of TBB/TBH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122076 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 18:42:56 +00:00
Jim Grosbach
6ec6eeb692
Handle 2 and 4 byte data blob fixup values for ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122075 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 18:39:10 +00:00
Rafael Espindola
6024c97ffa
Stub out explicit MCELFObjectTargetWriter interface.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 17:45:22 +00:00
Rafael Espindola
285b3e5b61
Move createELFObjectWriter to its own header.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 16:59:53 +00:00
Daniel Dunbar
1139d5090a
MC/ARM: Use aggressive symbol folding (important for jump tables, for example).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122044 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 06:00:24 +00:00
Daniel Dunbar
7b62afac0a
MC/Target: Remove HasScatteredSymbols target hook variable, which has been
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superceded and was effectively dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122024 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 02:06:08 +00:00
Bob Wilson
a1f544b62e
Use PairDRegs to implement ConcatVectors. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122017 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 01:21:08 +00:00
Jim Grosbach
3efad8fad4
Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 19:11:16 +00:00
Daniel Dunbar
5d05d9769e
MC/Mach-O: Lift some MachObjectWriter arguments into the target specific
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interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121981 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 17:21:02 +00:00
Daniel Dunbar
ae5abd595f
MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121973 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 16:09:19 +00:00
Daniel Dunbar
aa4b7dd13b
MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121971 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 16:08:33 +00:00
Daniel Dunbar
2761fc4270
MC: Move target specific fixup info descriptors to TargetAsmBackend instead of
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the MCCodeEmitter, which seems like a better organization.
- Also, cleaned up some magic constants while in the area.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121953 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 03:20:06 +00:00
Matt Beaumont-Gay
656b3d22f7
Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by Clang
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(see PR4579).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121939 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 01:34:26 +00:00
Bill Wendling
6baf46dbea
Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for
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it. I.e., it was always an immediate value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121932 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 00:50:33 +00:00
Bill Wendling
5a54516adf
Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi
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respectively.
It may be a bug that these opcodes are getting this far into machine code
generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121931 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 00:49:54 +00:00
Bill Wendling
dedec2b89d
Add encodings for Thumb1 Spill and Restore pseudos.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 00:38:41 +00:00
Jim Grosbach
3e333637f1
Thumb1 had two patterns for the same load-from-constant-pool instruction.
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Canonicalize on tLDRpci and remove tLDRcp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121920 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 23:52:36 +00:00
Eric Christopher
836c6245ad
Don't handle -arm-long-calls in fast isel for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 23:47:29 +00:00
Bill Wendling
7a905a82f7
If we're changing the frame register to a physical register other than SP, we
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need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 23:32:27 +00:00
Bill Wendling
dc3813750e
Whitespace cleanups.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121914 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 23:31:24 +00:00
Bob Wilson
0406356cd4
Add Neon VCVT instructions for f32 <-> f16 conversions.
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Clang is now providing intrinsics for these and so we need to support them
in the backend. Radar 8068427.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 22:14:12 +00:00
Jim Grosbach
d481110ef7
Tweak a few pseudo-inst pattern base classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 19:03:16 +00:00
Jim Grosbach
41b1d4e472
The new t2LEApcrel* pseudo instructions need the size specified.
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rdar://8768390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 18:48:45 +00:00
Owen Anderson
47dbd429da
Implement cleanups suggested by Daniel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 18:48:27 +00:00
Bill Wendling
22447ae54b
Add fixups for Thumb LDR/STR instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 08:51:02 +00:00
Bill Wendling
bc4224bc6b
Reapply r121808 now that the missing patterns have been supplied.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 01:03:19 +00:00
Bill Wendling
415af3452e
Add some missing patterns now that tLDRB and tLDRH are split into reg and
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immediate versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 00:58:57 +00:00
Bill Wendling
7d1d8db54a
Revert r121808 until I can fix the build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 00:04:00 +00:00
Jim Grosbach
9d04dc52a5
thumb adr fixup needs alignment just like the t2 version.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121812 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 23:47:35 +00:00
Bill Wendling
345cdb6475
Comments and cleaning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 23:42:48 +00:00
Bill Wendling
2af0fd3fee
Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In
...
particular, we want
ldr r2, [r3]
to be equivalent to
ldr r2, [r3, #0 ]
and not
ldr r2, [r3, r0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 23:40:49 +00:00
Jim Grosbach
d40963c406
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 22:28:03 +00:00
Bill Wendling
ee2b350d83
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121797 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 22:26:49 +00:00
Bill Wendling
b6faf65215
Multiclassify the LDR/STR encoding patterns. The only functionality difference
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is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 22:10:49 +00:00
Jim Grosbach
8d6d7d6e30
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121792 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 21:28:29 +00:00
Jim Grosbach
40edf73a62
Refactor a bit for legibility.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 21:10:47 +00:00
Jim Grosbach
00f25fa43e
trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 20:46:39 +00:00
Jim Grosbach
eb61272150
Make sure to propagate the predicate operands for LEApcrel to ADR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 20:45:47 +00:00
Owen Anderson
86abd48fd0
Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 19:42:53 +00:00
Daniel Dunbar
abfbac52df
MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121772 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 17:37:16 +00:00
Jim Grosbach
e8eb1ea6ac
Trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 16:25:15 +00:00
Bill Wendling
971321bb70
Use the integer scheduling intrinsic for integer loads and stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121765 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 12:33:05 +00:00
Bill Wendling
f4caf69720
The tLDR et al instructions were emitting either a reg/reg or reg/imm
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instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 03:36:38 +00:00
Evan Cheng
0c1aec1891
bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 03:22:07 +00:00
Owen Anderson
a838a25d59
Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
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process cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 00:36:49 +00:00
Bob Wilson
4711d5cda3
Remove the rest of the *_sfp Neon instruction patterns.
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Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now. It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior. Since that isn't obviously wrong, I've just
changed the test file. This completes the work for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 23:02:37 +00:00
Bob Wilson
0e6d540d17
Simplify N2VSPat, removing some unnecessary type arguments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121729 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 23:02:31 +00:00
Owen Anderson
6b8719fd7d
Revert r121721, which broke buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 22:51:08 +00:00
Owen Anderson
e8d02539d7
Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
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which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121721 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 22:29:52 +00:00
Bob Wilson
4dedddce93
Delete a line that I forgot to revert previously.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121719 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 22:05:55 +00:00
Bob Wilson
1e6f59608b
Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.
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Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns. The pattern
gets pretty ugly but it seems to work well. Partial fix for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121718 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 21:58:05 +00:00
Bob Wilson
3a6756cb1c
Use pseudo instructions for 2-register Neon instructions for scalar FP.
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Partial fix for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121716 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 21:05:52 +00:00
Bob Wilson
6dbcea1f8e
Remove unused instruction class arguments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121715 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 21:05:44 +00:00
Evan Cheng
30fb13f97a
Generalize BFI isel lowering a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 20:32:54 +00:00
Owen Anderson
c266600bec
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
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as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 19:31:11 +00:00
Jim Grosbach
56a2535474
Use 32-bit types for 32-bit values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 19:25:46 +00:00
Jim Grosbach
7e294cfcf9
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121708 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 19:18:13 +00:00
Evan Cheng
a9688c4b57
(or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-11 04:11:38 +00:00
Jim Grosbach
092e2cd569
Add FIXME
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121598 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 23:41:10 +00:00
Owen Anderson
63ee22065d
Attempt to get Thumb2 branch fixups working properly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121593 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 23:02:28 +00:00
Owen Anderson
5fd873d8e8
Fix merge error in my last fix to Thumb2 vldr fixups.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:53:48 +00:00
Owen Anderson
e2e0f58809
Fixups for Thumb2 vldr's need to have the effective PC aligned as well.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121587 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:46:47 +00:00
Bill Wendling
1591b293d6
The MCFixupKindInfo table needs to be in the order that the enums were
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declared. Add a note specifying this and spruce up the list a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121586 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:37:19 +00:00
Owen Anderson
ac00e96273
Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121585 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:32:08 +00:00
Bob Wilson
746fa17d59
Add float patterns for Neon vld1-lane/dup and vst1-lane operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121583 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:13:32 +00:00
Bob Wilson
20d5515aa5
Remove unused arguments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:13:24 +00:00
Owen Anderson
0f4b60d43a
Fix encoding of Thumb1 LDRB and STRB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121581 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:11:13 +00:00
Jim Grosbach
7bf4c02789
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121580 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 21:57:34 +00:00
Owen Anderson
808c7d1482
Fix Thumb2 encodings of STREX and LDREX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121579 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 21:52:38 +00:00
Jim Grosbach
0be099da79
Correct encoding of rotation immediate for Thumb2 instructions. rdar://8755999
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121525 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 21:24:18 +00:00
Jim Grosbach
90cc533fda
Fix encoding of 'U' bit for Thumb2 STRD/LDRD instructions. rdar://8755726
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 21:05:07 +00:00
Jim Grosbach
683fc3e9af
More trivial cleanup. No need to define the EncoderMethod property type. Can
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just assign to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 20:53:44 +00:00
Jim Grosbach
04da9bf9f1
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121522 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 20:51:35 +00:00
Jim Grosbach
a79bd0e1e0
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 20:47:29 +00:00
Bob Wilson
a92bac64cb
Fix some invalid alignments for Neon vld-dup and vld/st-lane instructions.
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Alignments smaller than the total size of the memory being loaded or stored,
unless the alignment is 8 bytes, are not allowed. Add tests for this, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 19:37:42 +00:00
Jim Grosbach
568f528c99
Teach isCSRestore() that ARM/Thumb2 functions will use post-modify LDR
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instructions to restore a single register rather than an LDM instruction.
rdar://8754999
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121498 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 18:41:15 +00:00
Jim Grosbach
e246717c3a
Thumb unconditional branch binary encoding. rdar://8754994
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 18:21:33 +00:00
Jim Grosbach
0108645139
Thumb conditional branch binary encodings. rdar://8745367
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 17:13:40 +00:00
Kevin Enderby
44a9e8f869
Fix the leak from r121401 of the Operands erased in the list but not deleted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121450 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 01:41:56 +00:00
Bill Wendling
272df516d7
Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the
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t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121417 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 21:49:07 +00:00