Justin Holewinski
4ddde0cba9
PTX: fixup test cases for register changes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 16:45:51 +00:00
Devang Patel
1dd4e56d55
Do not unnecessarily use AT_specification DIE because it does not add any value.
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Few weeks ago, llvm completely inverted the debug info graph. Earlier each debug info node used to keep track of its compile unit, now compile unit keeps track of important nodes. One impact of this change is that the global variable's do not have any context, which should be checked before deciding to use AT_specification DIE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140282 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 23:41:11 +00:00
Akira Hatanaka
4d77ae61f1
Remove +.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140266 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 17:43:48 +00:00
Akira Hatanaka
0b4a61548f
Re-enable some of the disabled tests. Use FileCheck instead of grep to check
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output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140263 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 17:36:30 +00:00
Nadav Rotem
d7e0ceaa59
add another testcase for pr10902
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140257 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 17:13:40 +00:00
Nadav Rotem
1147248e6f
[VECTOR-SELECT] Address one of the bugs in pr10902.
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Vector SetCC result types need to be type-legalized.
This code worked before because scalar result types are known to be legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140249 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 14:34:38 +00:00
Eric Christopher
eeef9e8180
Remove llvm-gcc and various compiler handling from llvm. It's not needed
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here anymore and has been migrated to the test-suite project.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140216 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 23:58:15 +00:00
Bill Wendling
4d1d86bac9
This test is completely invalid with the modern EH model. Delete.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140213 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 23:52:09 +00:00
Bruno Cardoso Lopes
e97190fdf8
Add a DAGCombine for subvector extracts to remove useless chains of
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subvector inserts and extracts. Initial patch by Rackover, Zvi with
some tweak done by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140204 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 23:19:33 +00:00
Bruno Cardoso Lopes
f4b841d4e2
Revert r140097, working on a better approach
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 23:19:29 +00:00
Evan Cheng
0d18174f0f
Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140181 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 21:38:18 +00:00
NAKAMURA Takumi
6aaf0561ae
test/CodeGen/X86/avx-minmax.ll: Unbreak Win32.
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On Windows x64, 128-bit arguments are not passed by reg but by indirect. eg.
maxpd:
vmovapd (%rcx), %xmm0
vmaxpd (%rdx), %xmm0, %xmm0
FIXME: I don't care YMM on x64 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140143 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 14:11:35 +00:00
Craig Topper
3699261d3f
Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140140 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 07:38:59 +00:00
Andrew Trick
4815d56bb2
ARM isel bug fix for adds/subs operands.
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Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 03:17:40 +00:00
Bruno Cardoso Lopes
278cbfb3f5
Attempt to fix -mtriple=i686-{cygwin|mingw|win32} regressions. Nakamura,
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if this doesn't work, please provide more details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 00:08:12 +00:00
Bruno Cardoso Lopes
97136c922e
Based on the small opt Zvi's patch was trying to achieve, eliminate
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128-bit undef subvector insertion into a 256-bit vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140097 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:36:50 +00:00
Eli Friedman
17569fe05b
Some additional tests for Thumb atomic load and store (which I somehow forgot to commit earlier).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140074 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 22:02:33 +00:00
Bruno Cardoso Lopes
97dc60b759
Match X86ISD::FSETCCsd and X86ISD::FSETCCss while in AVX mode. This fix
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PR10955 and PR10948.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140069 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 21:29:24 +00:00
Nadav Rotem
354efd88db
setOperationAction should be done on the return value of the type, not the operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-18 14:57:03 +00:00
Nadav Rotem
91e43fd17a
When promoting integer vectors we often create ext-loads. This patch adds a
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dag-combine optimization to implement the ext-load efficiently (using shuffles).
For example the type <4 x i8> is stored in memory as i32, but it needs to
find its way into a <4 x i32> register. Previously we scalarized the memory
access, now we use shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-18 10:39:32 +00:00
Benjamin Kramer
5778fef314
Apply Duncan's test fix from r139986 to the avx version of that test too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-18 00:41:38 +00:00
Duncan Sands
6bcd2196e5
Synthesize x86 max/min instructions also for vectors (i.e. produce
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maxps and maxpd). This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it. Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-17 16:49:39 +00:00
Andrew Trick
cc32efd592
Test case trial and error. Not sure the proper way to check MBB names.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 03:57:19 +00:00
Andrew Trick
17bd2c5d68
Reduced a stronger test case for coalescer bug PR10920.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139898 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 03:46:49 +00:00
Eli Friedman
331120b1a4
Some legalization fixes for atomic load and store.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 21:20:49 +00:00
Jakob Stoklund Olesen
01afdb3a45
VirtRegMap is counting spill slots, not register spills.
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Fix the stats counters to reflect that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139819 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 18:31:13 +00:00
Bruno Cardoso Lopes
0c4b9ff077
Change all checks regarding the presence of any SSE level to always
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take into consideration the presence of AVX. This change, together with
the SSEDomainFix enabled for AVX, makes AVX codegen to always (hopefully)
emit the same code as SSE for 128-bit vector ops. I don't
have a testcase for this, but AVX now beats SSE in performance for
128-bit ops in the majority of programas in the llvm testsuite
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139817 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 18:27:36 +00:00
Andrew Trick
b1afbac64b
[regcoalescing] bug fix for RegistersDefinedFromSameValue.
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An improper SlotIndex->VNInfo lookup was leading to unsafe copy removal.
Fixes PR10920 401.bzip2 miscompile with no IV rewrite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139765 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 01:09:33 +00:00
Nadav Rotem
436fe8498a
Add integer promotion support for vselect
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139692 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 14:42:15 +00:00
Bruno Cardoso Lopes
5ca0d14915
Vector shuffle mask <i32 4, i32 5, i32 2, i32 3> should yield "movsd", not "movss".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139686 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 02:36:14 +00:00
Devang Patel
d2aaaf3a75
Remove ancient debug info constructs from test cases, they are not relevant to test case's main objective.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 00:29:50 +00:00
Devang Patel
64789c582c
Remove unnecessary old test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 00:28:54 +00:00
Akira Hatanaka
8395c91d56
Delete test cases that generate code for allegrex/psp and cannot be repurposed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139652 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 22:29:13 +00:00
Eli Friedman
fe731214d2
Error out on CodeGen of unaligned load/store. Fix test so it isn't accidentally testing that case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 20:50:54 +00:00
Akira Hatanaka
a4b97f327d
Add pattern used to match MipsLo, which is needed when the instruction selector
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tries to match a dead MipsLo node (explanation in the link below).
http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139634 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 20:13:58 +00:00
Akira Hatanaka
302fdecf9d
Disable tests which generate code for allegrex or psp.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139632 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 20:00:35 +00:00
Nadav Rotem
e1490d1e43
update checked pattern
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 19:59:18 +00:00
Nadav Rotem
aec5861bb6
Add vselect target support for targets that do not support blend but do support
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xor/and/or (For example SSE2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 19:17:42 +00:00
Andrew Trick
3c8015aa6c
Generalize this test's CHECK statements to handle different indvars modes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139577 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 02:46:27 +00:00
Bruno Cardoso Lopes
8970060a4c
Change testcase commandline to be more strict and silence buildbots
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139554 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 22:59:26 +00:00
Bruno Cardoso Lopes
5fc48100ee
Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
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destination types are equal!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 22:59:23 +00:00
Bruno Cardoso Lopes
457d53d9ce
Revert the wrong part of r139528, and fix testcases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139541 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 21:24:07 +00:00
Bruno Cardoso Lopes
8e03a821f9
Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
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However with this fix it does now.
Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139528 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 19:30:40 +00:00
Eli Friedman
9f3b6a5a2a
Fix mistake in test runline.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 17:32:58 +00:00
Richard Osborne
a1d16b53e8
Associate a MemOperand with LDWCP nodes introduced during ISel.
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This information is required if we want LDWCP to be hoisted out of loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 14:43:23 +00:00
Eli Friedman
cfeb55cdbc
Really un-XFAIL the testcase, like I said I would in r139458.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139459 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 02:02:27 +00:00
Richard Trieu
2db8628085
Fixed an assert from:
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assert("not implemented for target shuffle node");
to:
assert(0 && "not implemented for target shuffle node");
This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 01:26:21 +00:00
Akira Hatanaka
33ff5aeaa8
Fix test cases.
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Generate code for Mips32r1 unless a Mips32r2 feature is tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:14:58 +00:00
Eli Friedman
9db817fd0c
Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 21:04:06 +00:00
Akira Hatanaka
8ddf6531b8
Drop support for Mips1 and Mips2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:45:50 +00:00