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4fea38f773
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20188 Commits

Author SHA1 Message Date
Craig Topper
4fea38f773 Add X86 MULX instruction for disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142738 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-23 00:33:32 +00:00
Craig Topper
272895f0ab Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 multiply instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142737 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-22 23:13:53 +00:00
Benjamin Kramer
1a2f9886a2 Move various generated tables into read-only memory, fixing up const correctness along the way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-22 16:50:00 +00:00
Nadav Rotem
5b2bba6122 Fix pr11193. 
SHL inserts zeros from the right, thus even when the original
sign_extend_inreg value was of 1-bit, we need to sra.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142724 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-22 12:39:25 +00:00
Bill Wendling
b8dcb314f7 The different flavors of ARM have different valid subsets of registers. Check 
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142706 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-22 00:29:28 +00:00
Jim Grosbach
224180e81b Assembly parsing for 4-register sequential variant of VLD2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 23:58:57 +00:00
Jim Grosbach
4661d4cac3 Assembly parsing for 2-register sequential variant of VLD2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 22:21:10 +00:00
Jim Grosbach
b6310316db Assembly parsing for 4-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:35:01 +00:00
Jim Grosbach
cdcfa28056 Assembly parsing for 3-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:02:19 +00:00
Jim Grosbach
280dfad489 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 18:54:25 +00:00
Owen Anderson
7784f1d2d8 Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142669 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 18:43:28 +00:00
Jim Grosbach
7926db8268 Nuke an #if0 that got accidentally left in. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142658 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 16:59:08 +00:00
Jim Grosbach
293a5f69fa whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142657 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 16:56:40 +00:00
Jim Grosbach
fe7b4998c6 Remove some outdated comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142653 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 16:14:12 +00:00
Craig Topper
b4c945716f Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 06:55:01 +00:00
Richard Smith
ed8db320af Fix unused variable warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142630 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 01:22:04 +00:00
Owen Anderson
cd20c58e98 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 22:23:58 +00:00
Dan Gohman
5bdab4a63c Disable the PPC hazard recognizer. It currently only supports 
top-down scheduling and top-down scheduling is going away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142621 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 21:45:36 +00:00
Owen Anderson
a3a6f215d0 Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142618 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 21:24:38 +00:00
Bill Wendling
767f8be9ee Add missing operand. <rdar://problem/10313323> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142615 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 20:37:11 +00:00
Lang Hames
1dda3d511e Haven't yet found a nice way to handle TargetData verification in the 
AsmParser. This patch adds validation for target data layout strings upon
construction of TargetData objects. An attempt to construct a TargetData object
from a malformed string will trigger an assertion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142605 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 19:24:44 +00:00
Jim Grosbach
01817c39a9 Tidy up. Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142591 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 17:28:20 +00:00
Jim Grosbach
6b09c77b7a ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 15:04:25 +00:00
Jim Grosbach
d0b614754e ARM VTBX (one register) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142581 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 14:48:50 +00:00
Chad Rosier
6690bca623 Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :( 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 00:07:12 +00:00
Evan Cheng
fd230df463 Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10291355 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142550 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 22:22:54 +00:00
James Molloy
cdd8e46bec Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size. 
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.

The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.

Fixes PR11087.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142530 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 14:11:07 +00:00
Bill Wendling
922ad78776 Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142485 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 09:24:02 +00:00
Bill Wendling
b677a135ac Remove some dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142484 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 09:04:11 +00:00
Craig Topper
717cdb0df8 Rename PEXTR to PEXT. Add intrinsics for BMI instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 07:48:35 +00:00
Bill Wendling
15a1a226be Emit the MOVT instruction only if the # LPads is > 64K. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142460 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 23:19:55 +00:00
Bill Wendling
a5871dc104 For Thumb mode, we need to use a constant pool if the value is too large to be 
used with the CMP instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 23:11:05 +00:00
Eric Christopher
857bf83414 Revert "Turn on the vzeroupper pass by default." 
This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142455 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 23:10:11 +00:00
Jim Grosbach
862019c37f ARM VTBL (one register) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142441 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 23:02:30 +00:00
Bill Wendling
85f3a0a4c4 Use the integer compare when the value is small enough. Use the "move into a 
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142440 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 22:52:20 +00:00
Eric Christopher
7e8ae57be9 Turn on the vzeroupper pass by default. 
I'll remove/rename the option in a few days.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142439 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 22:50:17 +00:00
Bill Wendling
952cb50fee Use the integer compare when the value is small enough. Use the "move into a 
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142437 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 22:49:07 +00:00
Lang Hames
e482471402 Teach fast isel about vector stores, and make DoSelectCall return false when it fails to emit a store. This fixes <rdar://problem/10215997>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142432 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 22:11:33 +00:00
Bill Wendling
564392bd3f The value we're comparing against may be too large for the ARM CMP 
instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142431 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 22:11:18 +00:00
Bill Wendling
b9fecf4e07 The immediate may be too large for the CMP instruction. Move it into a register 
and use that in the CMP.
<rdar://problem/10305266>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142429 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 21:55:58 +00:00
Jim Grosbach
a7d2e759ee Yet more ARM NEON assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142416 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 20:21:17 +00:00
Jim Grosbach
aead579017 ARM vmla/vmls assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142413 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 20:14:56 +00:00
Jim Grosbach
687656c630 ARM vmov assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142412 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 20:10:47 +00:00
Andrew Trick
90b7b12f01 Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. 
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142397 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 19:18:52 +00:00
Bob Wilson
9d45de252c Use isIntN and isUIntN to check for valid signed/unsigned numbers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142395 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:46:49 +00:00
Andrew Trick
7f5f0dae33 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142394 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:40:53 +00:00
Bill Wendling
f7b0207f1e A landing pad could have more than one predecessor. In that case, we want that 
predecessor to remove the jump to it as well. Delay clearing the 'landing pad'
flag until after the jumps have been removed. (There is an implicit assumption
in several modules that an MBB which jumps to a landing pad has only two
successors.)
<rdar://problem/10304224>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142390 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:30:49 +00:00
Jim Grosbach
9120088979 ARM vmla/vmls assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142389 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:27:07 +00:00
Jim Grosbach
0a0374018f ARM vqdmulh assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142386 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:12:09 +00:00
Jim Grosbach
970f787a7e ARM vmul assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142381 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:01:52 +00:00