Commit Graph

154 Commits

Author SHA1 Message Date
Chandler Carruth
0b8c9a80f2 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 11:36:10 +00:00
Dmitri Gribenko
344df79cc0 Add a missing 'else'. Found by grep '} if'
No testcase because it is apparently not so trivial to construct.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170595 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 22:13:01 +00:00
Jakob Stoklund Olesen
9466bdebb7 Verify bundle flags for consistency in MachineVerifier.
The new bidirectional bundle flags are redundant, so inadvertent bundle
tearing can be detected in the machine code verifier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170463 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-18 22:55:07 +00:00
Chandler Carruth
d04a8d4b33 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 16:50:05 +00:00
Chad Rosier
3d71688476 [inline asm] Implement mayLoad and mayStore for inline assembly. In general,
the MachineInstr MayLoad/MayLoad flags are based on the tablegen implementation.
For inline assembly, however, we need to compute these based on the constraints.

Revert r166929 as this is no longer needed, but leave the test case in place. 
rdar://12033048 and PR13504

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167040 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30 19:11:54 +00:00
Jakob Stoklund Olesen
feab72c20a Remove unused BitVectors from getAllocatableSet().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16 00:05:06 +00:00
Jakob Stoklund Olesen
fb9ebbf236 Switch most getReservedRegs() clients to the MRI equivalent.
Using the cached bit vector in MRI avoids comstantly allocating and
recomputing the reserved register bit vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 21:57:41 +00:00
Roman Divacky
5932429765 Stop casting away const qualifier needlessly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163258 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 22:26:57 +00:00
Jakob Stoklund Olesen
daddf07497 Move tie checks into MachineVerifier::visitMachineOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 18:38:28 +00:00
Jakob Stoklund Olesen
90a4f78d3b Verify the consistency of inline asm operands.
The operands on an INLINEASM machine instruction are divided into groups
headed by immediate flag operands. Verify this structure.

Extract verifyTiedOperands(), and only call it for non-inlineasm
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162849 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 18:11:05 +00:00
Jakob Stoklund Olesen
ca71c5debe Verify the tied operand flags.
WHen running with -verify-machineinstrs, check that tied operands come
in matching use/def pairs, and that they are consistent with MCInstrDesc
when it applies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 00:38:03 +00:00
Craig Topper
96601ca332 Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22 06:07:19 +00:00
Jakob Stoklund Olesen
e7fdef420d Don't add CFG edges for redundant conditional branches.
IR that hasn't been through SimplifyCFG can look like this:

  br i1 %b, label %r, label %r

Make sure we don't create duplicate Machine CFG edges in this case.

Fix the machine code verifier to accept conditional branches with a
single CFG edge.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-20 21:39:52 +00:00
Jakob Stoklund Olesen
b254c6d77a Add CFG checks to MachineVerifier.
Verify that the predecessor and successor lists are consistent and free
of duplicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162223 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-20 20:52:06 +00:00
Richard Smith
11a4fa4523 Fix undefined behavior: don't perform array indexing through a potentially null
pointer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161919 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15 01:39:31 +00:00
Jakob Stoklund Olesen
804468916a Verify regunit intervals along with virtreg intervals.
Don't cause regunit intervals to be computed just to verify them. Only
check the already cached intervals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161183 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02 16:36:50 +00:00
Jakob Stoklund Olesen
79240f9539 Add report() functions that take a LiveInterval argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02 14:31:49 +00:00
Jakob Stoklund Olesen
e5c79a5c25 Extract some methods from verifyLiveIntervals.
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161149 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02 00:20:20 +00:00
Jakob Stoklund Olesen
a62e1e8bc6 Also verify RegUnit intervals at uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161147 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01 23:52:40 +00:00
Jakob Stoklund Olesen
eba2bbb58c Verify two-address constraints more carefully.
Include <undef> operands and virtual registers after leaving SSA form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25 16:49:11 +00:00
Pete Cooper
b97c57a8b7 Fix crash in machine verifier when trying to print the def of a register which has no def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160531 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19 23:40:38 +00:00
Bill Wendling
96cb112852 Remove tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160475 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19 00:04:14 +00:00
Jakob Stoklund Olesen
bb0721680c Check for extra kill flags on live-out virtual registers.
This would previously get reported as the misleading "Virtual register
def doesn't dominate all uses."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29 21:00:00 +00:00
Jakob Stoklund Olesen
a4e6397fd9 Enforce stricter liveness rules for PHIs.
Verify that all paths from the entry block to a virtual register read
pass through a def. Enable this check even when MRI->isSSA() is false.

Verify that the live range of a virtual register is live out of all
predecessor blocks, even for PHI-values.

This requires that PHIElimination sometimes inserts IMPLICIT_DEF
instruction in predecessor blocks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-25 18:18:27 +00:00
Jakob Stoklund Olesen
f935e945c0 Also verify the def index for early clobbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159039 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22 22:23:58 +00:00
Jakob Stoklund Olesen
12a7be9ba4 Fix some more LiveInterval enumerations.
Deterministically enumerate the virtual registers instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158872 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20 23:23:59 +00:00
Akira Hatanaka
6b0cd9b9c6 Make machine verifier check the first instruction of the last bundle instead of
the last instruction of a basic block.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158468 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14 20:51:13 +00:00
Pete Cooper
83569cb062 Move terminator machine verification to check MachineBasicBlock::instr_iterator instead of MBB::iterator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07 17:41:39 +00:00
Jakob Stoklund Olesen
1f9c3ec831 Properly verify liveness with bundled machine instructions.
Bundles should be treated as one atomic transaction when checking
liveness. That is how the register allocator (and VLIW targets) treats
bundles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06 22:34:30 +00:00
Jakob Stoklund Olesen
396618b43a Switch all register list clients to the new MC*Iterator interface.
No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01 23:28:30 +00:00
Evan Cheng
cac58aa80e Optional def can be either a def or a use (of reg0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157640 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29 19:40:44 +00:00
Jakob Stoklund Olesen
e3da8c6286 Fix a verifier bug.
Make sure useless (def-only) intervals also get verified.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157000 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17 18:32:40 +00:00
Jakob Stoklund Olesen
397fc4874e Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 22:10:26 +00:00
Jakob Stoklund Olesen
78811669d5 Enable machine code verification after PreSched2 passes.
The late scheduler depends on accurate liveness information if it is
breaking anti-dependencies, so we should be able to verify it.

Relax the terminator checking in the machine code verifier so it can
handle the basic blocks created by if conversion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28 23:31:15 +00:00
Jakob Stoklund Olesen
948a44458c Skip liveness verification when MRI->tracksLiveness() is false.
Extract the liveness verification into its own method.

This makes it possible to run the machine code verifier after liveness
information is no longer required to be valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153596 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28 20:47:35 +00:00
Jakob Stoklund Olesen
ff0275ea53 Report the defining instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10 00:44:11 +00:00
Jakob Stoklund Olesen
64ffa83c9b Add SSA verification to MachineVerifier.
Somehow we never verified SSA dominance before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152458 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10 00:36:06 +00:00
Jakob Stoklund Olesen
1efd6b94a9 Use SmallPtrSet instead of DenseSet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152457 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10 00:36:04 +00:00
Craig Topper
9ebfbf8b9f Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 05:37:41 +00:00
Jakob Stoklund Olesen
30e98a03a3 Move the operand iterator into MachineInstrBundle.h where it belongs.
Extract a base class and provide four specific sub-classes for iterating
over const/non-const bundles/instructions.

This eliminates the mystery bool constructor argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151684 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 00:33:41 +00:00
Jakob Stoklund Olesen
9ca12d2e2f Handle regmasks in the machine code verifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 01:42:41 +00:00
Jakob Stoklund Olesen
121b179edf Update machine code verifier.
After the SlotIndex slot names were updated, it is possible to apply
stricter checks to live intervals.

Also treat bundles as bags of operands when checking live intervals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151531 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 18:24:30 +00:00
Lang Hames
03698deb25 Update MachineVerifier to check the new physreg live-in rules.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150496 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14 19:17:48 +00:00
Evan Cheng
ddfd1377d2 - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
  and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
  prevent IT blocks from being broken apart.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 02:11:42 +00:00
Evan Cheng
5a96b3dad2 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:15:52 +00:00
Benjamin Kramer
a7b0cb7594 Remove all remaining uses of Value::getNameStr().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144648 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 16:27:03 +00:00
Jakob Stoklund Olesen
194eb71a11 Use getVNInfoBefore() when it makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 01:39:36 +00:00
Jakob Stoklund Olesen
2debd48ca7 Rename SlotIndexes to match how they are used.
The old naming scheme (load/use/def/store) can be traced back to an old
linear scan article, but the names don't match how slots are actually
used.

The load and store slots are not needed after the deferred spill code
insertion framework was deleted.

The use and def slots don't make any sense because we are using
half-open intervals as is customary in C code, but the names suggest
closed intervals.  In reality, these slots were used to distinguish
early-clobber defs from normal defs.

The new naming scheme also has 4 slots, but the names match how the
slots are really used.  This is a purely mechanical renaming, but some
of the code makes a lot more sense now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144503 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 20:45:27 +00:00
Jakob Stoklund Olesen
b4a0221e85 Fix sub-register operand verification.
PhysReg operands are not allowed to have sub-register indices at all.

For virtual registers with sub-reg indices, check that all registers in
the register class support the sub-reg index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 22:12:57 +00:00
Jakob Stoklund Olesen
5adc07ebe8 Verify that terminators follow non-terminators.
This exposes a -segmented-stacks bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140429 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 22:45:39 +00:00