Commit Graph

48 Commits

Author SHA1 Message Date
Dale Johannesen
874ae251c3 Revert 72707 and 72709, for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02 03:12:52 +00:00
Dale Johannesen
ca46fdd284 Add missing file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72709 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01 23:48:58 +00:00
Stefanus Du Toit
8cf5ab153d Update CPU capabilities for AMD machines
- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10

New processor names match those used by gcc.

Patch by Paul Redmond!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72434 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-26 21:04:35 +00:00
Dan Gohman
f75e5b4d8c Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has
SSE2, however it's possible to disable SSE2, and the subtarget support
code thinks that if 64-bit implies SSE2 and SSE2 is disabled then
64-bit should also be disabled. Instead, just mark all the 64-bit
subtargets as explicitly supporting SSE2.

Also, move the code that makes -march=x86-64 enable 64-bit support by
default to only apply when there is no explicit subtarget. If you
need to specify a subtarget and you want 64-bit code, you'll need to
select a subtarget that supports 64-bit code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63575 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-03 00:04:43 +00:00
Evan Cheng
0be6d3fb2a Add Intel processors core i7 and atom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61603 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-03 04:24:44 +00:00
Evan Cheng
ccb6976a69 Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61557 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-02 05:35:45 +00:00
Evan Cheng
027fdbe3ba Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-24 07:34:46 +00:00
Dale Johannesen
2194d46624 Accept -march=i586, because gcc does (a synonym
for pentium).  Fixes
gcc.target/i386/20000720-1.c
gcc.target/i386/pr26826.c



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57528 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-14 22:06:33 +00:00
Anton Korobeynikov
ef93cecd80 Add ability to override segment (mostly for code emitter purposes).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57380 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-11 19:09:15 +00:00
Andrew Lenharth
ea7da50e5a Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47795 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-01 13:37:02 +00:00
Dale Johannesen
b4c9a687eb nocona, core2 and penryn support 64 bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47149 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-15 01:22:41 +00:00
Nate Begeman
63ec90a6a8 SSE 4.1 Intrinsics and detection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
Arnold Schwaighofer
48abc5cf6b Corrected many typing errors. And removed 'nest' parameter handling
for fastcc from X86CallingConv.td.  This means that nested functions
are not supported for calling convention 'fastcc'.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42934 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-12 21:30:57 +00:00
Bill Wendling
cd6cea0823 We only need to specify the most-implied feature for an architecture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37275 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-22 05:15:37 +00:00
Bill Wendling
11d8fdaf6a 3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36860 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-06 07:56:19 +00:00
Bill Wendling
4222d806fa Add an "implies" field to features. This indicates that, if the current
feature is set, then the features in the implied list should be set also.
The opposite is also enforced: if a feature in the implied list isn't set,
then the feature that owns that implies list shouldn't be set either.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36756 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-04 20:38:40 +00:00
Bill Wendling
3f3a17dd62 Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers
clobbered by a call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36448 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25 21:31:48 +00:00
Bill Wendling
bb1ee05253 Add support for our first SSSE3 instruction "pmulhrsw".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35869 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-10 22:10:25 +00:00
Chris Lattner
31c8a6d511 Add a description of the X86-64 calling convention and the return
conventions.  This doesn't do anything yet, but may in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34636 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-26 18:17:14 +00:00
Evan Cheng
a26eb5e1a7 Still need to support -mcpu=<> or cross compilation will fail. Doh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30764 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-06 09:17:41 +00:00
Evan Cheng
abc346ceda Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3, and 64-bit support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30763 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-06 08:21:07 +00:00
Evan Cheng
25ab690a43 Committing X86-64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-08 06:48:29 +00:00
Evan Cheng
751458dac9 ImmMask should be 3 for a two-bit field; Compact X86II
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28381 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-18 06:27:15 +00:00
Evan Cheng
0f3ac8d8d4 getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-18 00:12:58 +00:00
Evan Cheng
c01d497255 Remove PointerType from class Target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28368 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 21:20:27 +00:00
Evan Cheng
3c55c54a87 - Use xor to clear integer registers (set R, 0).
- Added a new format for instructions where the source register is implied
  and it is same as the destination register. Used for pseudo instructions
  that clear the destination register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25872 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 06:13:50 +00:00
Chris Lattner
259e97cc72 * Fix 80-column violations
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25854 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 19:43:35 +00:00
Jeff Cohen
b8643ac476 Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25760 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 03:45:35 +00:00
Evan Cheng
559806f575 x86 CPU detection and proper subtarget support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25679 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 08:10:46 +00:00
Chris Lattner
cedc6f4b30 PHI and INLINEASM are now built-in instructions provided by Target.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 01:46:15 +00:00
Evan Cheng
97c7fc351e Added preliminary x86 subtarget support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25645 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-26 09:53:06 +00:00
Nate Begeman
16b04f3d5e Get closer to fully working scalar FP in SSE regs. This gets singlesource
working, and Olden/power.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22441 91177308-0d34-0410-b5e6-96231b3b80d8
2005-07-15 00:38:55 +00:00
Nate Begeman
f63be7d395 First round of support for doing scalar FP using the SSE2 ISA extension and
XMM registers.  There are many known deficiencies and fixmes, which will be
addressed ASAP.  The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.

The x86 backend will still default to x87 style FP.  To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.

An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
                        Sum += P[i]; return Sum; }

The inner loop looks like the following:
x87:
.LBB_foo_1:     # no_exit
        fldl (%esp)
        faddl (%eax,%ecx,8)
        fstpl (%esp)
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

SSE2:
        addsd (%eax,%ecx,8), %xmm0
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22340 91177308-0d34-0410-b5e6-96231b3b80d8
2005-07-06 18:59:04 +00:00
Chris Lattner
9a3e49a1b3 Add support for the -x86-asm-syntax flag, which can be used to choose between
Intel and AT&T style assembly language.  The ultimate goal of this is to
eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission
is not fully operational.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16639 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-03 20:36:57 +00:00
Chris Lattner
c96bb817aa Remove a bunch of ad-hoc target-specific flags that were only used by the
old asmprinter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15660 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-11 07:12:04 +00:00
Chris Lattner
a35ce87e2e Eliminate 3 of the X86 printImplicit* flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15398 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 08:23:17 +00:00
Chris Lattner
266538350a Add support for the printImplicitDefsBefore flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12893 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-13 17:18:39 +00:00
John Criswell
4ffff9e2fa Added the llvm.readport and llvm.writeport intrinsics for x86. These do
I/O port instructions on x86.  The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output.  This required adjustment to some
methods so that a leading comma would or would not be printed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12782 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-08 20:31:47 +00:00
Chris Lattner
1c54a85447 Add FP conditional move instructions, which annoyingly have special properties
that require the asmwriter to be extended (printing implicit uses before the
explicit operands)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12574 91177308-0d34-0410-b5e6-96231b3b80d8
2004-03-31 22:02:13 +00:00
Alkis Evlogimenos
5ab29b504d Each instruction now has both an ImmType and a MemType. This describes
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11967 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-28 22:02:05 +00:00
John Criswell
856ba76200 Added LLVM copyright header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9321 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-21 15:17:13 +00:00
Chris Lattner
2959b6ec49 Completely eliminate the isVoid TSFlag, shifting over all other fields
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7636 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-06 15:32:20 +00:00
Chris Lattner
e5bb2d94d9 There is nothing special about noops anymore
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7568 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-04 05:11:37 +00:00
Chris Lattner
c8f4587efd transition to using let instead of set
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7564 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-04 04:59:56 +00:00
Chris Lattner
1cca5e3a29 Add new TableGen instruction definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7537 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 21:54:21 +00:00
Chris Lattner
b77eb78afc Add Target class for X86 target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7523 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 18:19:37 +00:00
Chris Lattner
762fb5f704 Initial checkin of X86.td file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7510 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:47:49 +00:00