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41 Commits

Author SHA1 Message Date
Zoran Jovanovic
4d24300247 Implementation of 16-bit microMIPS instructions MFHI and MFLO. 
Differential Revision: http://llvm-reviews.chandlerc.com/D3141


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205532 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-03 12:47:34 +00:00
Zoran Jovanovic
077aa54e4e Fixed issue with microMIPS JAL instruction. 
Differential Revision: http://llvm-reviews.chandlerc.com/D3200


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205185 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 14:00:10 +00:00
Zoran Jovanovic
37fb9b9591 Provide an operand for microMIPS wait instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204329 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-20 10:41:37 +00:00
Zoran Jovanovic
3ac3e7451b Implementation of microMIPS 16-bit instructions MOVE and JALR. 
Differential Revision: http://llvm-reviews.chandlerc.com/D3112


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204325 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-20 10:18:24 +00:00
Zoran Jovanovic
2a80d7db79 Fixed operand of SC microMIPS instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202526 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-28 18:22:56 +00:00
Daniel Sanders
f862a4aefe [mips][sched] Split IILoad into II_L[BHWD], II_L[BHW]U, II_L[WD][LR], and II_RESTORE 
No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199749 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-21 15:21:14 +00:00
Daniel Sanders
61a2eb1df5 [mips] Split IIIdiv int II_DIV, II_DIVU, II_DDIV, and II_DDIVU 
No functional change since the InstrItinData's were duplicated



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199497 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-17 14:48:06 +00:00
Daniel Sanders
235a81cbbf [mips][sched] Split IIImul and IIImult into subclasses. 
IIImul -> II_MUL
IIImult -> II_MULT, II_MULTU, II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_DMULT, II_DMULTU

No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199495 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-17 14:32:41 +00:00
Daniel Sanders
89d1caaa1b [mips][sched] Put AND, OR, XOR, MOVT_I, and MOVF_I in the same itinerary class as their non-microMIPS counterparts. 
No functional change since both classes have the same InstrItinData definition.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199402 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-16 17:13:57 +00:00
Daniel Sanders
1a6226f236 [mips][sched] Split IIseb into II_SEB and II_SEH 
No functional change since there are no InstrItinData's.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199396 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-16 16:19:38 +00:00
Daniel Sanders
7bc4a7ced6 [mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. 
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
  II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
  II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
  II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
  II_SR[AL]V, II_SUBU, II_XOR

No functional change since the InstrItinData's have been duplicated.

This is necessary because the classes are shared between all schedulers.

Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-16 14:27:20 +00:00
Daniel Sanders
31505363ca [mips] Correct itin class for MULT_MM and MULTu_MM to IIImult. 
This matches the itin class used by the non-microMIPS equivalents of these
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199389 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-16 14:02:48 +00:00
Zoran Jovanovic
814c8910f2 LL and SC decoder method fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199316 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-15 13:17:33 +00:00
Zoran Jovanovic
f5c2d3896b Added support for LWU microMIPS instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199315 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-15 13:01:18 +00:00
Zoran Jovanovic
7dc193619e Support for microMIPS load effective address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198010 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-25 10:14:07 +00:00
Zoran Jovanovic
bd2926b056 Support for microMIPS control instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197696 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-19 16:25:00 +00:00
Zoran Jovanovic
4267b16e78 Support for microMIPS LL and SC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197692 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-19 16:12:56 +00:00
Akira Hatanaka
92b8543819 [mips] Redefine TAILCALL as a pseudo instruction. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195896 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-27 23:58:32 +00:00
Zoran Jovanovic
1206f1968b Support for microMIPS trap instruction with immediate operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194569 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-13 13:15:03 +00:00
Zoran Jovanovic
9f471750fa Support for microMIPS trap instructions 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-07 14:35:24 +00:00
Zoran Jovanovic
5c042162be Support for microMIPS branch instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-04 14:53:22 +00:00
Zoran Jovanovic
1aaf43c2a2 Support for microMIPS jump instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193623 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-29 16:38:59 +00:00
Akira Hatanaka
243702b95a [mips] Fix definition of mfhi and mflo instructions to read from the whole 
accumulator instead of its sub-registers, $hi and $lo. 

We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:

mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2     // read lower 32-bit result from $lo.
mtlo $4     // write to $lo. the content of $hi becomes unpredictable.
mfhi $3     // read higher 32-bit from $hi, which has an unpredictable value.

I don't have a test case for this change that reliably reproduces the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 18:49:46 +00:00
Zoran Jovanovic
ab48d10eff Support for microMIPS DIV instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190745 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-14 07:15:21 +00:00
Zoran Jovanovic
47b33528d1 Support for misc microMIPS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190744 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-14 06:49:25 +00:00
Akira Hatanaka
69f8e0935a [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit 
into a 5-bit or 6-bit field.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190226 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-07 00:02:02 +00:00
Vladimir Medic
638382e6f1 This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190154 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 13:08:00 +00:00
Vladimir Medic
dadd1fba32 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190152 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:53:21 +00:00
Vladimir Medic
bf7f7b5e0e This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190148 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:41:17 +00:00
Vladimir Medic
a674463aac This patch adds support for microMIPS disassembler and disassembler make check tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190144 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:30:36 +00:00
Akira Hatanaka
a98a486ad1 [mips] Resolve register classes dynamically using ptr_rc to reduce the number of 
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-20 21:08:22 +00:00
Akira Hatanaka
93877b3cbc [mips] Guard micromips instructions with predicate InMicroMips. Also, fix 
assembler predicate HasStdEnd so that it is false when the target is micromips.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188824 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-20 20:46:51 +00:00
Akira Hatanaka
cbaf6d0cc3 [mips] Rename HIRegs and LORegs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-14 00:47:08 +00:00
Jack Carter
da0860f78e [Mips] Support for unaligned load/store microMips instructions 
This includes instructions lwl, lwr, swl and swr.

Patch by Zoran Jovnovic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188312 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-13 20:19:16 +00:00
Akira Hatanaka
1858786285 [mips] Rename register classes CPURegs and CPU64Regs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 23:08:38 +00:00
Akira Hatanaka
a1fe9ef62e [mips] Replace usages of register classes with register operands. Also, remove 
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 22:20:40 +00:00
Akira Hatanaka
52b7321a48 [mips] Define instruction itineraries IIArith and IILogic. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187468 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 00:55:34 +00:00
Jack Carter
d761004bfd Mips td file formatting: white space and long lines 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182047 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-16 20:08:49 +00:00
Akira Hatanaka
089741479b [mips] Add definitions of micromips load and store instructions. 
Patch by Zoran Jovanovic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180241 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-25 01:21:25 +00:00
Akira Hatanaka
385de77303 [mips] Add definitions of micromips shift instructions. 
Patch by Zoran Jovanovic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180238 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-25 01:11:15 +00:00
Akira Hatanaka
f530aff9de [mips] First patch which adds support for micromips. 
This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.

Patch by Zoran Jovanovic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179873 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 19:03:11 +00:00