Commit Graph

72 Commits

Author SHA1 Message Date
Benjamin Kramer
b619dd5d5b X86: Shrink certain forms of movsx.
In particular:
movsbw %al, %ax   --> cbtw
movswl %ax, %eax  --> cwtl
movslq %eax, %rax --> cltq

According to Intel's manual those have the same performance characteristics but
come with a smaller encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186174 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 18:06:44 +00:00
David Blaikie
0187e7a9ba DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-16 20:34:27 +00:00
Tim Northover
e5609f3732 X86: Stop LEA64_32r doing unspeakable things to its arguments.
Previously LEA64_32r went through virtually the entire backend thinking it was
using 32-bit registers until its blissful illusions were cruelly snatched away
by MCInstLower and 64-bit equivalents were substituted at the last minute.

This patch makes it behave normally, and take 64-bit registers as sources all
the way through. Previous uses (for 32-bit arithmetic) are accommodated via
SUBREG_TO_REG instructions which make the types and classes agree properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 20:43:49 +00:00
Tim Northover
3ba14fab1b Revert r183069: "TMP: LEA64_32r fixing"
Very sorry, it was committed from the wrong branch by mistake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183070 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 10:23:46 +00:00
Tim Northover
4d3ace4da0 TMP: LEA64_32r fixing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183069 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 10:21:54 +00:00
Tim Northover
85c622d6b6 X86: change MOV64ri64i32 into MOV32ri64
The MOV64ri64i32 instruction required hacky MCInst lowering because it
was allocated as setting a GR64, but the eventual instruction ("movl")
only set a GR32. This converts it into a so-called "MOV32ri64" which
still accepts a (appropriate) 64-bit immediate but defines a GR32.
This is then converted to the full GR64 by a SUBREG_TO_REG operation,
thus keeping everyone happy.

This fixes a typo in the opcode field of the original patch, which
should make the legact JIT work again (& adds test for that problem).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183068 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 09:55:14 +00:00
Eric Christopher
34431085de Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as it
seems to have caused PR16192 and other JIT related failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183059 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 23:30:45 +00:00
Tim Northover
43887bf3e6 X86: change MOV64ri64i32 into MOV32ri64
The MOV64ri64i32 instruction required hacky MCInst lowering because it was
allocated as setting a GR64, but the eventual instruction ("movl") only set a
GR32. This converts it into a so-called "MOV32ri64" which still accepts a
(appropriate) 64-bit immediate but defines a GR32. This is then converted to
the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182991 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 09:57:13 +00:00
Tim Northover
15983b80a0 X86: use sub-register sequences for MOV*r0 operations
Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions,
it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg")
and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is
smaller and partial register updates can sometimes be avoided.

Until recently, this sequence was a barrier to rematerialization though. That
should now be fixed so it's an appropriate time to make the change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182928 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-30 13:19:42 +00:00
Tim Northover
da0416b935 X86: change zext moves to use sub-register infrastructure.
32-bit writes on amd64 zero out the high bits of the corresponding 64-bit
register. LLVM makes use of this for zero-extension, but until now relied on
custom MCLowering and other code to fixup instructions. Now we have proper
handling of sub-registers, this can be done by creating SUBREG_TO_REG
instructions at selection-time.

Should be no change in functionality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182921 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-30 10:43:18 +00:00
Craig Topper
8647750dfb Add X86 code emitter support AVX encoded MRMDestReg instructions.
Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-16 03:44:31 +00:00
Craig Topper
599521f167 Teach X86 MC instruction lowering that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177011 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 07:09:57 +00:00
David Sehr
693c37aa86 Two changes relevant to LEA and x32:
1) allows the use of RIP-relative addressing in 32-bit LEA instructions under
   x86-64 (ILP32 and LP64)
2) separates the size of address registers in 64-bit LEA instructions from
   control by ILP32/LP64.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174208 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01 19:28:09 +00:00
Chandler Carruth
0b8c9a80f2 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 11:36:10 +00:00
Chandler Carruth
d04a8d4b33 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 16:50:05 +00:00
Benjamin Kramer
ed9e442cf0 Decouple MCInstBuilder from the streamer per Eli's request.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168597 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-26 18:05:52 +00:00
Benjamin Kramer
391271f3bb Add MCInstBuilder, a utility class to simplify MCInst creation similar to MachineInstrBuilder.
Simplify some repetitive code with it. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-26 13:34:22 +00:00
Michael Liao
281ae5abf5 Fix setjmp on models with non-Small code model nor non-Static relocation model
- MBB address is only valid as an immediate value in Small & Static
  code/relocation models. On other models, LEA is needed to load IP address of
  the restore MBB.
- A minor fix of MBB in MC lowering is added as well to enable target
  relocation flag being propagated into MC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166084 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17 02:22:27 +00:00
Craig Topper
fdc054c3a3 Move X86MCInstLower class definition into implementation file. It's not needed outside.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16 06:01:50 +00:00
Craig Topper
ff9d51b994 Move expansion of SETB_C(8/16/32/64)r from MCInstLower to ExpandPostRAPseudos and mark them as pseudos in the td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05 06:05:15 +00:00
Craig Topper
d902194631 Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162740 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 07:30:47 +00:00
Craig Topper
13897fb263 Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162738 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 07:05:28 +00:00
Chad Rosier
a20e1e7ef5 Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01 18:39:17 +00:00
Rafael Espindola
c07f5bbd3b Use a base register instead of an index register with the local dynamic model.
Fixes pr13048.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158158 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07 18:39:19 +00:00
Hans Wennborg
f0234fcbc9 Implement the local-dynamic TLS model for x86 (PR3985)
This implements codegen support for accesses to thread-local variables
using the local-dynamic model, and adds a clean-up pass so that the base
address for the TLS block can be re-used between local-dynamic access on
an execution path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01 16:27:21 +00:00
Jim Grosbach
3e96531186 Refactor data-in-code annotations.
Use a dedicated MachO load command to annotate data-in-code regions.
This is the same format the linker produces for final executable images,
allowing consistency of representation and use of introspection tools
for both object and executable files.

Data-in-code regions are annotated via ".data_region"/".end_data_region"
directive pairs, with an optional region type.

data_region_directive := ".data_region" { region_type }
region_type := "jt8" | "jt16" | "jt32" | "jta32"
end_data_region_directive := ".end_data_region"

The previous handling of ARM-style "$d.*" labels was broken and has
been removed. Specifically, it didn't handle ARM vs. Thumb mode when
marking the end of the section.

rdar://11459456

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-18 19:12:01 +00:00
Hans Wennborg
228756c744 Implement initial-exec TLS model for 32-bit PIC x86
This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156611 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 10:11:01 +00:00
Craig Topper
79aa3417eb Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17 18:46:09 +00:00
Jakob Stoklund Olesen
527a08b253 Use the same CALL instructions for Windows as for everything else.
The different calling conventions and call-preserved registers are
represented with regmask operands that are added dynamically.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 17:56:02 +00:00
Anton Korobeynikov
d4a19b6a72 Add support for implicit TLS model used with MS VC runtime.
Patch by Kai Nacke!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150307 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11 17:26:53 +00:00
Craig Topper
6d1263acb9 Convert assert(0) to llvm_unreachable in X86 Target directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149809 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 05:38:58 +00:00
Jakob Stoklund Olesen
71f0fc1ca8 Ignore register mask operands when lowering instructions to MC.
This is similar to implicit register operands.  MC doesn't understand
register liveness and call clobbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148437 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 23:52:19 +00:00
Craig Topper
12216172c0 Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148108 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 08:12:35 +00:00
Jakob Stoklund Olesen
0edd83bfff Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:27:25 +00:00
Craig Topper
745a86bac9 Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 22:34:59 +00:00
Rafael Espindola
e840e88239 This commit introduces two fake instructions MORESTACK_RET and
MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET
followed by a MOV respectively.  Having a fake instruction prevents
the verifier from seeing a MachineBasicBlock end with a
non-terminator (MOV).  It also prevents the rather eccentric case of a
MachineBasicBlock ending with RET but having successors nevertheless.

Patch by Sanjoy Das.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 21:12:27 +00:00
Owen Anderson
2fec6c5ff1 Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 23:26:17 +00:00
Jakob Stoklund Olesen
92fb79b7a6 Expand the x86 V_SET0* pseudos right after register allocation.
This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 05:10:54 +00:00
Eli Friedman
d5ccb0558f Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).
This isn't exactly ideal, but it is good enough for the moment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 18:48:32 +00:00
Bruno Cardoso Lopes
863bd9d5cf Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128
This also fixes PR10452

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:05:32 +00:00
Evan Cheng
1abf2cb59b Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135219 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 23:50:31 +00:00
Stuart Hastings
0e29ed081b Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.
rdar://problem/8614450


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 19:04:40 +00:00
Stuart Hastings
d22f036c2a Reverting 131641 to investigate 'bot complaint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131654 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 17:54:42 +00:00
Stuart Hastings
b6dcf3c514 Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer be
pseudos.  rdar://problem/8614450


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 16:59:50 +00:00
Nate Begeman
3c49706a61 Add support for AVX to materialize +0.0 when doing scalar FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 21:43:51 +00:00
Rafael Espindola
d652dbe720 Move lowering of TLS_addr32 and TLS_addr64 to X86MCInstLower.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120263 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-28 21:16:39 +00:00
Chris Lattner
21d272874b tidy up, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119092 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 23:32:42 +00:00
Chris Lattner
142b531e02 move the pic base symbol stuff up to MachineFunction
since it is trivial and will be shared between ppc and x86.
This substantially simplifies the X86 backend also.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119089 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 22:48:15 +00:00
Chris Lattner
4fd0ea0166 simplify getPICBaseSymbol a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119088 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 22:37:11 +00:00
Rafael Espindola
de42e5c09b handle X86::EH_RETURN64 and X86::EH_RETURN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117378 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 18:09:55 +00:00