Jakob Stoklund Olesen
59f7199e16
SubRegIndex'ize MSP430
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 17:42:55 +00:00
Jakob Stoklund Olesen
7bb31e3187
Fix a few places that depended on the numeric value of subreg indices.
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Add assertions in places that depend on consecutive indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104510 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 17:13:28 +00:00
Jakob Stoklund Olesen
558661d271
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
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from ARMRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 16:54:32 +00:00
Jakob Stoklund Olesen
3458e9e4df
Rename X86 subregister indices to something shorter.
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Use the tablegen-produced enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:17 +00:00
Jakob Stoklund Olesen
73ea7bf450
Add the SubRegIndex TableGen class.
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This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:12 +00:00
Bob Wilson
069e434868
VDUP doesn't support vectors with 64-bit elements.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-23 05:42:31 +00:00
Daniel Dunbar
62e4c671b6
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
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addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:33 +00:00
Daniel Dunbar
54ddf3d9c7
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104452 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:29 +00:00
Daniel Dunbar
4c361972fd
MC/X86: Add alias for setz, setnz, jz, jnz.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 06:37:33 +00:00
Evan Cheng
2457f2c661
Implement @llvm.returnaddress. rdar://8015977.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 01:47:14 +00:00
Jim Grosbach
5eb1951539
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
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Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 01:06:18 +00:00
Bob Wilson
be751cfe9c
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
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copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:23:12 +00:00
Chris Lattner
c2685a9c98
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 23:16:21 +00:00
Kevin Enderby
9d31d79493
Added retl for 32-bit x86 and added retq for 64-bit x86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104394 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 23:01:38 +00:00
Evan Cheng
1015ba7018
- Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
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that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 20:53:24 +00:00
Dale Johannesen
acbf6348b1
Previous commit message should refer to 104308.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104337 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 18:44:47 +00:00
Dale Johannesen
e39859a838
Fix two bugs in 104348:
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Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104336 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 18:40:15 +00:00
Chris Lattner
a26a8471bd
now that fp reg kill insertion stuff happens as a separate
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pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.
The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes. Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross. It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).
Just do the scan on machine phis which is simpler, faster
and more correct. This fixes PR6828.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 18:17:54 +00:00
Chris Lattner
d596c90030
Use less evil form of switch stmt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104331 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 18:02:42 +00:00
Chris Lattner
d3d9ee1a4d
use continue to reduce nesting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104330 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 18:01:24 +00:00
Chris Lattner
637e073181
pull a nested loop of this pass out to its own function,
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eliminating the gymnastics around the ContainsFPCode var.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104328 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 17:57:03 +00:00
Chris Lattner
6f569aabb5
modernize this pass a bit, fit in 80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104326 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 17:49:07 +00:00
Matt Fleming
d8a33ddcfe
Currently, createMachOStreamer() is invoked directly in llvm-mc which
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isn't ideal if we want to be able to use another object file format.
Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104318 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 12:54:43 +00:00
Matt Fleming
7efaef6b82
Split out the x86_32 an x86_64 ELF backends as they handle ELF
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differently. This will make adding ELF support easier in the long run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104317 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 11:39:07 +00:00
Dale Johannesen
7d07b48b26
Fix i64->f64 conversion, x86-64, -no-sse. A bit
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tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104308 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 00:52:33 +00:00
Evan Cheng
f7d87ee158
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 00:43:17 +00:00
Evan Cheng
1cc3984148
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 23:26:43 +00:00
Daniel Dunbar
4e7f8390c0
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:36:29 +00:00
Daniel Dunbar
1fe591da3e
X86: Model i64i32imm properly, as a subclass of all immediates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104272 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:39 +00:00
Daniel Dunbar
0306e3ddbf
X86: Fix immediate type of FOO64i32 operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104271 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:35 +00:00
Bob Wilson
63b8845e78
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
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This fixes the remaining issue with pr7167.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104257 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 18:39:53 +00:00
Dan Gohman
53e184980d
Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't
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have a pattern and it had an invalid encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104244 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 18:05:01 +00:00
Dale Johannesen
5f07d5224d
The PPC MFCR instruction implicitly uses all 8 of the CR
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registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems. 7739628.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104238 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 17:48:26 +00:00
Dan Gohman
e5e4ff974d
Fix assembly parsing and encoding of the pushf and popf family of
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104231 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 16:16:00 +00:00
Dan Gohman
100804f494
Set neverHasSideEffects on 64-bit pushf and popf, for consistency with
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16-bit and 32-bit pushf and popf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104228 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 15:42:55 +00:00
Dan Gohman
14aaeac5cf
Define the x86 pause instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 01:35:50 +00:00
Dan Gohman
ee5673b622
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
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doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104203 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 01:23:41 +00:00
Evan Cheng
211ffa1351
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:19:50 +00:00
Daniel Dunbar
d94406a940
MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 17:20:58 +00:00
Daniel Dunbar
52322e7b8b
MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same
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prefix byte problem as in r104062.
- As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 15:26:43 +00:00
Daniel Dunbar
7d4bd203be
MC/X86: Strip spurious operands from TAILJMPr64 as we do for CALL64r and
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CALL64pcrel32, for the same reason.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104116 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 08:07:12 +00:00
Evan Cheng
9085f98b32
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 07:28:01 +00:00
Evan Cheng
27fa722311
Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104114 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 07:26:50 +00:00
Daniel Dunbar
597f17d5f1
MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104112 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 06:20:44 +00:00
Evan Cheng
5fd1c9be2d
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 06:07:03 +00:00
Evan Cheng
3c3195cbf1
Target instruction selection should copy memoperands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104110 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 06:06:09 +00:00
Daniel Dunbar
9248b3208a
MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to
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avoid same prefix byte problem as in r104062.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 04:31:36 +00:00
Evan Cheng
ea420b20d4
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 01:52:25 +00:00
Dan Gohman
7c2e03916c
Factor out the code for picking integer arithmetic with immediate
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opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104091 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 00:53:19 +00:00
Dan Gohman
f8c1ef0510
Teach mode load folding and unfolding code about CMP32ri8 and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:54:15 +00:00