3793 Commits

Author SHA1 Message Date
Bill Wendling
5cc88a205d A few more thumb instruction MC encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119913 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 22:52:33 +00:00
Eric Christopher
827656dab4 Rewrite address handling to use a structure with all the possible address
mode variables. Handle frame indexes in load/store and allocas again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 22:38:27 +00:00
Eric Christopher
13df1a0bac STRH only needs the additional operand, not t2STRH. Also invert conditional
to match the one from the load emitter above.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 22:01:38 +00:00
Anton Korobeynikov
82f58740c7 Move some more hooks to TargetFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 15:59:32 +00:00
Bill Wendling
a09cc2b429 Add more Thumb add instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 01:18:47 +00:00
Bill Wendling
95a6d1759d Add Thumb encodings for some add instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119882 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 01:00:29 +00:00
Bill Wendling
6179c31e07 Add more encodings for Thumb instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119881 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 00:53:35 +00:00
Bill Wendling
20272a7c5a Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the same
value that the one in ARMMCCodeEmitter.cpp does.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 00:26:37 +00:00
Jim Grosbach
078e239f69 Fix ARM LDR* post-indexed operand encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 23:14:43 +00:00
Bill Wendling
1228038ed9 Encodings for the compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119868 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 23:14:32 +00:00
Owen Anderson
b16926940e The Vm and Vn register fields must be the same for a register-register vmov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119867 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 23:12:43 +00:00
Evan Cheng
ff96b63d6f Fix a cut-n-paste-error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119866 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 23:01:16 +00:00
Jim Grosbach
7b6ab402fe Operand names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119864 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 22:43:08 +00:00
Jim Grosbach
a30a51b16a trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119863 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 22:42:55 +00:00
Eric Christopher
b371658083 Don't need to save piecemeal now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 22:39:56 +00:00
Eric Christopher
2d630d7bc9 Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 22:37:58 +00:00
Bill Wendling
0ae28e4447 Add encodings for some of the thumb ADD instructions. Tests will come once the
asm parser can handle them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 22:37:33 +00:00
Eric Christopher
88de86b550 Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 22:36:41 +00:00
Jim Grosbach
efaeb41aec Clarify operand names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 22:36:02 +00:00
Eric Christopher
0d58122e12 Refactor address mode handling into a single struct (ala x86), this
should give allow a wider range of addressing modes.

No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119856 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 22:30:02 +00:00
Jim Grosbach
6571101cb7 Fix encoding for ARM MLS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119855 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 22:22:37 +00:00
Jim Grosbach
2aeb6121a1 Add ARM encoding information for STRD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 22:14:31 +00:00
Jim Grosbach
a1b4175b8e Shuffle things around a bit to keep like things together. Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119851 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 22:06:57 +00:00
Bill Wendling
ba46dc06e6 Revert accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 22:06:18 +00:00
Bill Wendling
a898166d38 Change long binary encodings to use hex instead. It's more readable. Also
initialize missing bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119849 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 22:02:18 +00:00
Jim Grosbach
953557f445 Factor out operand encoding bits for ARM addressing mode 2 store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119846 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 21:35:06 +00:00
Jim Grosbach
e2d54af47f Delete another dead class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119844 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 21:16:08 +00:00
Jim Grosbach
fc0cb4b906 whitespace tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 21:14:37 +00:00
Jim Grosbach
9ef65cbbc6 Refactor PICSTR* instructions to really be pseudos. Nuke dead classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119841 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 21:14:02 +00:00
Jim Grosbach
9558b4cdc4 Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119840 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 21:07:51 +00:00
Jim Grosbach
9cb15b5be5 Add ARM binary encoding information for the rest of the indexed loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119821 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 19:41:26 +00:00
Jim Grosbach
0c2283a910 Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 18:18:37 +00:00
Jim Grosbach
f1ce7cc1d1 ARM LDRD binary encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119812 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 18:16:46 +00:00
Jim Grosbach
3ea4daaf50 Remove hard tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119810 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 18:01:37 +00:00
Jim Grosbach
7a08864860 Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119806 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 17:11:02 +00:00
Benjamin Kramer
7920d96964 Avoid release build warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119804 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 16:36:02 +00:00
Owen Anderson
8b8640a964 Fix decoding ambiguities of stdrex and ldrex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119801 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 13:11:50 +00:00
Evan Cheng
1f190c8bdf These instructions are thumb2 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119793 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 06:28:11 +00:00
Evan Cheng
e8e67e13d4 Fix an obvious oversight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119792 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 06:15:10 +00:00
Bill Wendling
602890dd8e Add MC encodings for some Thumb instructions. Test for a few of them. The "bx
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119774 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 01:33:10 +00:00
Bill Wendling
cb21d1c9fd Use array_pod_sort because the list is contiguous.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 00:38:19 +00:00
Owen Anderson
91a7c59134 Provide Thumb2 encodings for strex and ldrex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119768 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 00:28:38 +00:00
Jim Grosbach
817c1a6ddd Minor cleanups to a few llvm_unreachable() calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 00:27:09 +00:00
Bill Wendling
d1fadd8c5d An 'unreachable' shouldn't have a '0 &&' prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 00:05:15 +00:00
Bill Wendling
50d0f58944 Add support for parsing the writeback ("!") token.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18 23:43:05 +00:00
Jason W Kim
837caa9313 Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18 23:37:15 +00:00
Owen Anderson
71c11825bf Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119755 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18 23:29:56 +00:00
Jim Grosbach
75b7b879c0 ARM Encoding information for UXTAH and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18 23:24:22 +00:00
Tanya Lattner
9684a7c128 Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first).
Added test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119749 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18 22:06:46 +00:00
Bill Wendling
24d22d2764 Don't allocate the SmallVector of Registers. It gets messy figuring out who
should delete what when the object gets copied around. It's also making valgrind
upset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18 21:50:54 +00:00