Commit Graph

82288 Commits

Author SHA1 Message Date
Craig Topper
5f9cccc509 Add SSE4A MOVNTSS/MOVNTSD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156281 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 05:36:19 +00:00
Eric Christopher
e5076d484b Support the 'J' constraint.
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156280 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 03:13:42 +00:00
Eric Christopher
50ab03954e Add support for the 'I' inline asm constraint. Also add tests
from the previous 2 patches.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156279 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 03:13:32 +00:00
Eric Christopher
0ed1f764f4 Allow 64 bit integer values in gpu registers if arch and abi are 64 bit.
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156278 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 03:13:22 +00:00
Eric Christopher
3ccbd47ecb When using inline asm constraints representing
non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156277 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 03:13:16 +00:00
Jim Grosbach
f09769067f Tidy up. Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156276 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 02:25:53 +00:00
Craig Topper
d978c54e60 Use MVT instead of EVT as the argument to all the shuffle decode functions. Simplify some of the decode functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156268 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 19:46:21 +00:00
Craig Topper
bdcbcb3ae7 Add VPERMQ/VPERMPD to the list of target specific shuffles that can be looked through for DAG combine purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156266 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 18:54:26 +00:00
Craig Topper
156f5bb56e Add shuffle decode support for VPERMQ/VPERMPD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156265 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 18:44:02 +00:00
Jim Grosbach
8e27c96159 TableGen: AsmMatcher diagnostic when missing instruction mnemonic.
Previously, if an instruction definition was missing the mnemonic,
the next line would just assert(). Issue a real diagnostic instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156263 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 17:33:14 +00:00
Chris Lattner
eb034f4af3 make SourceMgr tolerate empty SMLoc()'s better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156260 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 16:20:49 +00:00
Benjamin Kramer
77c4ef8a47 Switch the select to branch transformation on by default.
The primitive conservative heuristic seems to give a slight overall
improvement while not regressing stuff. Make it available to wider
testing. If you notice any speed regressions (or significant code
size regressions) let me know!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156258 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 14:25:16 +00:00
Jakub Staszak
58c1da84f2 Remove trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156257 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 13:52:31 +00:00
NAKAMURA Takumi
dc736b0a3e Unix/Process.inc: Give more useful random seed to srand. Workaround for PR12743.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156252 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 08:24:24 +00:00
NAKAMURA Takumi
24cddd5c9a Support/Process: Move llvm::sys::Process::GetRandomNumber() from Process.cpp to Unix/Process.inc.
FIXME: GetRandomNumber() is not implemented in Win32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 08:24:18 +00:00
Chris Lattner
77eafd940a reapply my patch, with a fix for an off-by-one error. Turned out to be a lot
of work for a drive-by fix :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156246 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 22:17:32 +00:00
Chris Lattner
c18e6d9375 revert my patches, which are causing problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156245 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 22:11:04 +00:00
Chris Lattner
b3a6194eba add missing header <shame>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156244 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 22:04:11 +00:00
Chris Lattner
bf0e32368e refactor some code to expose column numbers more and make diagnostic printing slightly more efficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 21:39:51 +00:00
Jim Grosbach
e5f31ad55e Nuke a few dead remnants of the CBE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156241 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 17:45:12 +00:00
Daniel Dunbar
c94e593060 [Support] Add missing include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 16:49:11 +00:00
Daniel Dunbar
463a719d36 [Support] Fix up comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156239 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 16:39:22 +00:00
Daniel Dunbar
92bb514612 [Support] Rewrite sys::fs::unique_file to not be stupid with /dev/urandom.
- Just use sys::Process::GetRandomNumber instead of having two poor
   implementations.
 - This is ~70 times (!) faster on my OS X machine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156238 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 16:36:24 +00:00
Daniel Dunbar
9c69e6ae69 [Support] Add sys::Process::GetRandomNumber().
- Primitive API, but we rarely have need for random numbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156237 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 16:36:20 +00:00
Daniel Dunbar
e0b0e7b295 [build] Add build check for ::arc4random().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156236 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 16:36:16 +00:00
Benjamin Kramer
0017180e70 Update all outdated autoconf files in the sample project.
We might just use symlinks here, but I'm afraid of possible portability issues.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156235 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 15:02:39 +00:00
Benjamin Kramer
59957500f9 CodeGenPrepare: Add a transform to turn selects into branches in some cases.
This came up when a change in block placement formed a cmov and slowed down a
hot loop by 50%:

	ucomisd	(%rdi), %xmm0
	cmovbel	%edx, %esi

cmov is a really bad choice in this context because it doesn't get branch
prediction. If we emit it as a branch, an out-of-order CPU can do a better job
(if the branch is predicted right) and avoid waiting for the slow load+compare
instruction to finish. Of course it won't help if the branch is unpredictable,
but those are really rare in practice.

This patch uses a dumb conservative heuristic, it turns all cmovs that have one
use and a direct memory operand into branches. cmovs usually save some code
size, so we disable the transform in -Os mode. In-Order architectures are
unlikely to benefit as well, those are included in the
"predictableSelectIsExpensive" flag.

It would be better to reuse branch probability info here, but BPI doesn't
support select instructions currently. It would make sense to use the same
heuristics as the if-converter pass, which does the opposite direction of this
transform.


Test suite shows a small improvement here and there on corei7-level machines,
but the actual results depend a lot on the used microarchitecture. The
transformation is currently disabled by default and available by passing the
-enable-cgp-select2branch flag to the code generator.

Thanks to Chandler for the initial test case to him and Evan Cheng for providing
me with comments and test-suite numbers that were more stable than mine :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 12:49:22 +00:00
Benjamin Kramer
aaf723dd2b Add a new target hook "predictableSelectIsExpensive".
This will be used to determine whether it's profitable to turn a select into a
branch when the branch is likely to be predicted.

Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM.

I'm not entirely happy with the name of this flag, suggestions welcome ;)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 12:49:14 +00:00
Benjamin Kramer
af87831519 NVPTX: Initialize the UseF32FTZ flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 11:22:02 +00:00
Stepan Dyatkovskiy
3f71cf14b2 Small fix in InstCombineCasts.cpp. Restored "alloca + bitcast" reducing for case when alloca's size is calculated within the "add/sub/... nsw".
Also added fix to 2011-06-13-nsw-alloca.ll test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156231 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 07:09:40 +00:00
Eric Christopher
f2eed387d4 Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 01:16:06 +00:00
Jakob Stoklund Olesen
a93090ccd9 Order register classes by spill size first, members last.
This is still a topological ordering such that every register class gets
a smaller enum value than its sub-classes.

Placing the smaller spill sizes first makes a difference for the
super-register class bit masks. When looking for a super-register class,
we usually want the smallest possible kind of super-register. That is
now available as the first bit set in the bit mask.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156222 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 23:12:22 +00:00
Jakob Stoklund Olesen
7fc4d9cbc5 Make sure findRepresentativeClass picks the widest super-register.
We want the representative register class to contain the largest
super-registers available. This makes the function less sensitive to the
register class numbering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156220 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 22:53:28 +00:00
Jakob Stoklund Olesen
41afb9da2c Remove extra comma in debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156219 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 22:53:26 +00:00
David Blaikie
03ba93e194 Fix warnings in release build.
This fixes a couple of Clang warnings in release builds of LLVM:

* Missing return in ISelLowering
* Unused variable in NVPTXutil.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156216 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 22:34:16 +00:00
Kevin Enderby
3610a15c35 Tweak to the fix in r156212, as with the change in removing the shift the
SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156213 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 22:09:52 +00:00
Kevin Enderby
ce734d5ffe Fix a bug in the ARM disassembler for wide branch conditional instructions
where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://11387046


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156212 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 22:02:27 +00:00
Chandler Carruth
917644d0c3 Fix a Clang warning in the new NVPTX backend:
In file included from ../lib/Target/NVPTX/VectorElementize.cpp:53:
../lib/Target/NVPTX/NVPTX.h:44:3: warning: default label in switch which covers all enumeration values [-Wcovered-switch-default]
  default: assert(0 && "Unknown condition code");
  ^
1 warning generated.

The prevailing pattern in LLVM is to not use a default label, and instead to
use llvm_unreachable to denote that the switch in fact covers all return paths
from the function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156209 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 21:35:49 +00:00
Chandler Carruth
30ba82933c Teach the code extractor how to extract a sequence of blocks from
RegionInfo's RegionNode. This mirrors the logic for automating the
extraction from a Loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156208 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 21:33:30 +00:00
Chandler Carruth
7c52c97a22 Rename the Region::block_iterator to Region::block_node_iterator, and
add a new Region::block_iterator which actually iterates over the basic
blocks of the region.

The old iterator, now call 'block_node_iterator' iterates over
RegionNodes which contain a single basic block. This works well with the
GraphTraits-based iterator design, however most users actually want an
iterator over the BasicBlocks inside these RegionNodes. Now the
'block_iterator' is a wrapper which exposes exactly this interface.
Internally it uses the block_node_iterator to walk all nodes which are
single basic blocks, but transparently unwraps the basic block to make
user code simpler.

While this patch is a bit of a wash, most of the updates are to internal
users, not external users of the RegionInfo. I have an accompanying
patch to Polly that is a strict simplification of every user of this
interface, and I'm working on a pass that also wants the same simplified
interface.

This patch alone should have no functional impact.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156202 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 20:55:23 +00:00
Justin Holewinski
49683f3c96 This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it.
The new target machines are:

nvptx (old ptx32) => 32-bit PTX
nvptx64 (old ptx64) => 64-bit PTX

The sources are based on the internal NVIDIA NVPTX back-end, and
contain more functionality than the current PTX back-end currently
provides.

NV_CONTRIB

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 20:18:50 +00:00
Sebastian Pop
2c7e5c714c Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits 16-bits encoding of CMN instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156195 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 19:53:56 +00:00
Preston Gurd
3d142e58ef Adds Intel Atom scheduling latencies to X86InstrSystem.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156194 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 19:26:37 +00:00
Matt Beaumont-Gay
39af9449a2 Pacify GCC's -Wreturn-type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156189 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 18:34:27 +00:00
Chandler Carruth
90cb7089e3 Factor the computation of input and output sets into a public interface
of the CodeExtractor utility. This allows speculatively computing input
and output sets to measure the likely size impact of the code
extraction.

These sets cannot be reused sadly -- we mutate the function prior to
forming the final sets used by the actual extraction.

The interface has been revamped slightly to make it easier to use
correctly by making the interface const and sinking the computation of
the number of exit blocks into the full extraction function and away
from the rest of this logic which just computed two output parameters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156168 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 11:20:27 +00:00
Chandler Carruth
50955031b8 Rather than trying to gracefully handle input sequences with repeated
blocks, assert that this doesn't happen. We don't want to bother trying
to support this call pattern as it isn't necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156167 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 11:17:06 +00:00
Chandler Carruth
6a81f64ab6 Fix a goof with my previous commit by completely returning when we
detect an in-eligible block rather than just breaking out of the loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 11:14:19 +00:00
Chandler Carruth
27742c1a76 Hoist a safety assert from the extraction method into the construction
of the extractor itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156164 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 10:26:45 +00:00
Chandler Carruth
99650c9088 Move the CodeExtractor utility to a dedicated header file / source file,
and expose it as a utility class rather than as free function wrappers.

The simple free-function interface works well for the bugpoint-specific
pass's uses of code extraction, but in an upcoming patch for more
advanced code extraction, they simply don't expose a rich enough
interface. I need to expose various stages of the process of doing the
code extraction and query information to decide whether or not to
actually complete the extraction or give up.

Rather than build up a new predicate model and pass that into these
functions, just take the class that was actually implementing the
functions and lift it up into a proper interface that can be used to
perform code extraction. The interface is cleaned up and re-documented
to work better in a header. It also is now setup to accept the blocks to
be extracted in the constructor rather than in a method.

In passing this essentially reverts my previous commit here exposing
a block-level query for eligibility of extraction. That is no longer
necessary with the more rich interface as clients can query the
extraction object for eligibility directly. This will reduce the number
of walks of the input basic block sequence by quite a bit which is
useful if this enters the normal optimization pipeline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156163 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 10:18:49 +00:00
Hans Wennborg
fd5abd546e Make ARM and Mips use TargetMachine::getTLSModel()
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 09:40:39 +00:00